High mobility heterojunction transistor and method

[0002] This invention relates generally to semiconductor transistors, and more particularly the invention relates to a field effect transistor having a heterostructure quantum well as a conducting channel between a source and drain, each comprising a semiconductor alloy and having heterojunctions.

[0003] Cost effective scaling has become a major challenge in silicon MOSFET technology. Traditional techniques are starting to fail in reducing certain undesirable physical effects as device dimensions shrink down to the sub-0.1 micron regime. However, bandgap engineering can provide one more degree of freedom in device design. In order to reduce bulk punchthrough and drain-induced barrier lowering (DIBL), a type of heterojunction MOSFET (HJMOSFET) with band offset at the source/drain junctions has been proposed by Hareland, Tasch, and Mazier in “New Structural Approach For Reducing Punchthrough Current in Deep Submicrometer MOSFETs and Extending MOSFETs Scaling”, IEEE Electronics Letters, Vol. 29, No. 21, pages 1894-1896, (October 1993), and in “Analysis of a Heterojunction MOSFET Structure For Deep Submicron Scaling”, Proceedings of the21st International Symp. on Compound Semiconductors, pages 18-22, (September 1994). See also Verheyen et al., “A Vertical Si/Si_1−xGe_xHeterojunction pMOSFET With Reduced DIBL Sensitivity, Using a Novel Gate Dielectric Approach”, 1999 International Symp. On VLSI Technology, System and Applications, pages 19-22 (1999). In this structure, Bandgap Engineering is performed horizontally to tailor the potential along the channel. Compared to a silicon control device, a HJMOSFET has lower off-state leakage current and a smaller subthreshold swing. However, the drive current in a HJMOSFET is normally 50-60% lower because most of the carriers have to quantum mechanically tunnel through the potential barrier between the source and drain. See also U.S. Pat. No. 5,155,571 which discloses a MOSFET in which source and drain are formed in a silicon substrate with a GeSi channel region therebetween.

[0004] In accordance with the invention, the performance of a MOSFET is improved by incorporating a heterostructure quantum well in the conducting channel in HJMOSFETs. The band offsets between the source/drain and the channel are eliminated while the band offsets between the source/drain and the semiconductor substrate are retained. Thus, Bandgap Engineering is now performed in both the horizontal and vertical dimensions.

[0005] More particularly, the high mobility heterojunction transistor in accordance with the invention includes a semiconductor body of one conductivity type, a source region and a drain region of opposite conductivity type formed in the semiconductor body with each of the source and the drain separated from the substrate by a heterojunction. A channel region is provided between the source region and the drain region which comprises an undoped layer of an alloy of the material of the semiconductor body, and a layer of the material of the semiconductor body overlying the undoped layer. A gate electrode is provided between the source and drain regions on an insulating layer formed on the semiconductor layer.

[0006] In a preferred embodiment, the source and drain regions are formed in the semiconductor substrate by implanting dopant of the opposite conductivity type and a material in the alloy of the semiconductor material which are annealed to form an alloy of the semiconductor material under the heterostructure quantum well of the channel region. The doped layer of semiconductor material overlying the undoped alloy layer is oxidized to form a gate dielectric on which the gate electrode is formed.

[0007] The invention and objects and features thereof will be more readily apparent for the following detailed description and appended claims when taken with the drawings.

[0008] FIG. 1 is a section view illustrating a high mobility heterojunction transistor in accordance with one embodiment of the invention.

[0009] FIGS. 2a-2care section views illustrating steps in fabricating the heterojunction transistor of FIG. 1.

[0010] FIG. 1 is a section view illustrating a preferred embodiment of a p-channel, high mobility heterojunction transistor (PHMHJT) in accordance with the invention. In this embodiment, the transistor is fabricated in an n-doped silicon substrate 10 with spaced-apart source region 12 and drain region 14 separated by a channel region over which is formed a polysilicon gate 16 on a silicon oxide layer 18. The sides of polysilicon gate 16 adjacent to source 12 and drain 14 have oxidized layers 20 and silicon oxide spacers 22, and silicide layers and metal contacts 24 are made on the surfaces of source 12 and drain 14. The silicide can be a refractory metal silicide with the contact being aluminum, for example.

[0011] The channel region of the transistor comprises a silicon germanium alloy layer 30 with a p⁺ silicon layer 32 under SiGe layer 30 and a cap layer 34 of silicon (doped or undoped) overlying SiGe layer 30. Unlike a traditional SiGe MODFET, the total thickness of silicon cap layer 34 and SiGe channel layer 30 is very thin, roughly on the order of the inversion layer thickness.

[0012] Each of source 12 and drain 14 comprises a p⁺ SiGe region which forms a heterojunction with the silicon substrate 10 and suppresses bulk punchthrough and DIBL. The doped source and drain regions extend to the surface of layer 34.

[0013] Device performance is significantly enhanced in the device of FIG. 1 with a large drive current similar to a SiGe MODFET and better subthreshold characteristics similar to a SiGe HJMOSFET. This translates to higher switching speeds and transconductances, lower transit times, and lower off-gate leakage current than in a conventional silicon pMOSFET.

[0014] The use of a heterostructure quantum well channel with the SiGe layer 30 improves drive current because there are no heterojunction-induced potential barriers to tunnel through in the on-state condition for the carriers in the channel. Therefore, source injection is significantly enhanced compared to a HJMOSFET. Further, the carriers are confined in the smaller-bandgap channel where the mobility is very high. With the pHMHJT, high mobility is achieved due to strain-induced reduced hole effective mass and reduced inter-valley scattering, less surface roughness scattering in the buried channel, and less ionized impurity scattering if the channel has a modulated doping profile. Also, the absolute value of the threshold voltage is reduced due to the smaller flat-band voltage in the SiGe channel. Further, the build-in potential barriers provided by the heterojunctions in the bulk semiconductor material are not easily influenced by applied voltages. Therefore, this reduces the subthreshold swing, the shift and threshold voltage due to DIBL, and the off-date leakage current caused by bulk punchthrough and DIBL.

[0015] Consider now FIG. 2aand the fabrication of a Si/SiGe pHMHJT with two-dimensional bandgap engineering in a planar configuration using crystal growth technique such as molecular beam epitaxy (MBE) or known chemical vapor deposition (CVD) processing. First, a thin in situ modulation doped p⁺ silicon layer 32 is grown on the n-silicon (100) substrate 10, and then an undoped Si_1−xGe_xepitaxial layer 30 is grown. Carriers from p⁺ silicon layer 32 will spill over into the undoped Si_1−xGe_xlayer 30 and form the channel of the transistor. This is followed by the deposition of silicon layer 34 which results in another thin layer of modulation doped p⁺ silicon or an undoped silicon layer. Layer 34 serves as a cap layer as well as a sacrificial layer for gate oxidation. Without the cap layer 34, poor interface between the strained SiGe layer 30 and the gate oxide 22 would deteriorate the device performance.

[0016] After the layers are grown, gate oxidation is performed to form oxide layer 18 followed by the polysilicon gate layer fabrication. The polysilicon gate is doped, photolithographically patterned, an etched to form gate 16, followed by sidewall 20 formation by reoxidation as shown in FIG. 2a.

[0017] Thereafter, as shown in FIG. 2b, boron is implanted and high energy germanium is implanted followed by low temperature anneal in order to form the crystallized strained SiGe regions 12′, 14′ using solid phase epitaxy (SPE). The boron can be activated without undue diffusion and extends the source and drain regions to the surface of layer 34. However, the step needs to be controlled such that the p⁺ dopant will not diffuse beyond the heterojunctions of the source and drain into the bulk silicon of the substrate. Otherwise, the benefit of the built-in band offsets will be greatly decreased. The SiGe layer 30 extends into the source and drain regions.

[0018] Finally, as shown in FIG. 2c, oxide spacers 22 are formed in abutment with sidewall oxide layers 20 adjacent to the source and drain, and then contacts are made to the source and drain by forming silicide layers of a refractory metal, for example, on the source and drain, and then a metal such as aluminum forming ohmic contacts 24 to the silicide layers.

[0019] A device in accordance with the invention may not need lightly doped drain (LDD) or ultrashallow source/drain extensions in a sub-0.1 micron HMHJT since hot carrier effects may not be significant due to scaled voltages, and bulk punchthrough and DIBL should be greatly suppressed by the potential barriers at the heterojunctions with the bulk silicon. This significantly simplifies the fabrication process, however such features could be included in the device structure to further enhance performance. While the invention has been described with reference to SiGe pMOSFETs, the invention can be realized in both n- and -p MOSFET with any suitable heterostructure material system. Such devices are particularly applicable in very high speed, low leakage sub-100 nm devices and microwave circuits for telecommunications applications, for example. Any problem of transient enhanced diffusion (TED) of boron in the SiGe PHMHJT can be solved by incorporating a small amount of carbon in the SiGe layer.

[0020] Thus, while the invention has been described with reference to a specific embodiment, the description is illustrative of the invention and is not to be construed as limiting the invention. Various modifications and applications may occur to those skilled in the art without departing from the true spirit and scope of the invention as defined by the appended claims.