Gated clock design supporting method, gated clock design supporting apparatus, and computer readable memory storing gated clock design supporting program

[0002] 1. Field of the Invention

[0003] This invention relates to automation of logic circuit design using a computer and particularly to a gated clock design supporting system intended to reduce load of procedure for clock gating in the design of a gated clock.

[0004] 2. Description of the Related Art

[0005] Recently, semiconductor chips like LSI have tended to be highly integrated and enlarged, so that power consumption also has simultaneously increased. The gated clock design method has been developed to generate a logic circuit having a small power consumption.

[0006] Here, the aforementioned gated clock deign will be described simply. In a subsequent description, the changing of the logic circuit by the gated clock design is referred to as clock gating.

[0007] FIG. 1 is a partial circuit diagram showing a part of a synchronous logic circuit to be subjected to logic design, indicating a logic circuit not clock-gated. In the same Figure, FF0, FF1, . . . FF31 indicate D flip-flops and a 32-bit register is formed of 32 flip-flops. A clock signal is supplied to clock input port (CK) of each flip-flop at the same timing and data calculated in data operating circuit 11 is written through data input port D at the same timing as the rise of the clock signal. It has been known that in such a logic circuit, a large amount of power is consumed when the flip-flop is actuated at a rise and fall of the clock. However, because the clock signal is inputted to the flip-flop always at a constant time frame, wasted power is wasted when data fetch is not required.

[0008] FIG. 2 is a circuit structure diagram of a clock-gated logic circuit, indicating an example in which an AND gate 12 is inserted on a clock line of FIG. 1 as a gating circuit. An enable logic circuit (not shown) for controlling clock output is connected to this AND gate 12, so that enable logic output of “1” or “0” is supplied from the enable logic circuit to the AND gate 12 corresponding to a timing of the clock signal.

[0009] In FIG. 2, when the enable logic output is set to “1”, data write is carried out because AND is established when the clock signal rises. On the other hand, if the enable logic output is set to “0”, data write is not carried out because AND is not established even if the clock signal rises. When data write is not required, it is possible to prevent consumption of waste power at the flip-flops by making enable logic output to be “0” corresponding to clock timing.

[0010] In the aforementioned gated clock design, enable logic circuit for clock gating must be added to the logic circuit at a logical design stage. However, according to the prior art, addition and correction of description in an enable logic circuit in a net list describing a composition of the logic circuit are carried out manually by a designer. Thus, it takes much labor and time when the list is modified and there is a fear that a correction error may occur. Further, for an added enable logic circuit to operate normally in a logic circuit, an enable logic portion needs to satisfy an independent timing constraint different from a data transfer portion. However, this timing constraint differs depending on a method for clock gating, for example, which of the AND gate or OR gate is used in the gating circuit. Therefore, the designer must produce a complicated timing constraint to be supplied to a design supporting CAD.

[0011] As described above, in the prior art gated clock design, it takes much labor and time for correction of a list or calculation for timing constraint when an enable logic circuit is added. Further, if a correction error or calculation error occurs, the same work must be repeated, so that it takes further time.

[0012] Accordingly, an object of the present invention is to automate various procedures of gated clock design so as to largely reduce a design period.

[0013] To achieve the above object, there is provided a gated clock design supporting method comprising the steps of: inputting information about logic circuit not clock-gated, information about enable logic for controlling clock output and information about a gating circuit; generating timing constraint to be supplied to the enable logic; calculating a delay time in the enable logic; determining whether or not the enable logic satisfies the timing constraint based on the delay time; when the enable logic satisfies the timing constraint, adding the gating circuit and a circuit composed of the enable logic to the logic circuit not clock-gated so as to generate a clock-gated logic circuit; and outputting information about the clock-gated logic circuit and the timing constraint to be secured for the enable logic.

[0014] According to a preferred embodiment of the present invention, the gating circuit includes a circuit for securing normal operation of a logic circuit.

[0015] According to another embodiment of the present, a step of generating information about gate on clock line of the clock-gated logic circuit is further contained.

[0016] According to still another embodiment of the invention, when the enable logic does not satisfy the timing constraint, an error message saying that a timing constraint error has occurred relating to an enable logic portion which does not satisfy the timing constraint is outputted.

[0017] According to further embodiment of the present invention, information about the clock-gated logic circuit and the timing constraint to be secured for the enable logic are displayed on a display unit.

[0018] According to still further embodiment of the present invention, information about the logic circuit not clock-gated, information about the enable logic and information about the gating circuit are inputted in the form of text information through a key board.

[0019] According to still further embodiment of the present invention, information about the logic circuit not clock-gated is inputted by drawing on a screen of a display unit.

[0020] Further, to achieve the above object, there is provided a gated clock design supporting apparatus comprising: a circuit information input portion for inputting information about logic circuit not clock-gated, information about enable logic for controlling clock output and information about a gating circuit; an enable logic timing constraint generating portion for generating timing constraint to be secured for the enable logic; an enable logic timing determination portion for calculating a delay time in the enable logic and determining whether or not the enable logic satisfies the timing constraint based on the delay time; a clock gating execution portion for, when the enable logic satisfies the timing constraint, adding the gating circuit and a circuit composed of the enable logic to the logic circuit not clock-gated so as to generate a clock-gated logic circuit; and a circuit information output portion for outputting information about the clock-gated logic circuit and the timing constraint to be secured for the enable logic.

[0021] Further to achieve the above object, there is provided a computer-readable memory storing gated clock design supporting program, the gated clock design supporting program comprising the steps of: inputting information about logic circuit not clock-gated, information about enable logic for controlling clock output and information about a gating circuit; generating timing constraint to be secured for the enable logic; calculating a delay time in the enable logic; determining whether or not the enable logic satisfies the timing constraint based on the delay time; when the enable logic satisfies the timing constraint, adding the gating circuit and a circuit composed of the enable logic to the logic circuit not clock-gated so as to generate a clock-gated logic circuit; and outputting information about the clock-gated logic circuit and the timing constraint to be secured for the enable logic.

[0022] The nature, principle and utility of the invention will become more apparent from the following detailed description when read in conjunction with the accompanying drawings.

[0023] In the accompanying drawings:

[0024] FIG. 1 is a partial circuit diagram showing a part of a synchronous logic circuit to be subjected to logical design;

[0025] FIG. 2 is a circuit structure diagram of a clock-gated logic circuit;

[0026] FIG. 3 is a block diagram showing a functional composition of a gated clock design supporting system according to an embodiment of the present invention;

[0027] FIG. 4 is a schematic structure diagram of a computer system to which the gated clock design supporting system is applied;

[0028] FIG. 5 is a flow chart showing steps of procedure of clock gating by the gated clock design supporting system;

[0029] FIG. 6 shows an example of enable logic to be inputted;

[0030] FIG. 7 is a circuit diagram showing an example of a logic circuit not clock-gated;

[0031] FIG. 8 is an explanatory diagram showing information about enable logic;

[0032] FIG. 9 is an explanatory diagram showing gating information;

[0033] FIG. 10 is a timing chart showing operation of clock signal;

[0034] FIG. 11 is an explanatory diagram showing an example of timing constraint relating to enable logic;

[0035] FIG. 12 is a circuit diagram showing a clock gated logic circuit;

[0036] FIG. 13 is an explanatory diagram showing an example of clock line gate information;

[0037] FIG. 14 is an explanatory diagram showing information about enable logic;

[0038] FIG. 15 is an explanatory diagram showing gating information;

[0039] FIG. 16 is an explanatory diagram showing an example of timing constraint relating to enable logic;

[0040] FIG. 17 is a circuit diagram showing a clock-gated logic circuit; and

[0041] FIG. 18 is an explanatory diagram showing an example of clock line gate information.

[0042] Hereinafter, an embodiment of gated clock design supporting method, gated clock design supporting apparatus and a computer readable memory storing a gated clock design supporting program will be described.

[0043] FIG. 3 is a block diagram showing a functional structure of a gated clock design supporting system according to the present embodiment. A gated clock design supporting system 10 shown in FIG. 3 includes a circuit information I/O portion 1, an enable logic input portion 2, a gating information input portion 3, a circuit information storage portion 4, a control portion 5, an enable logic timing determination portion 6, an enable logic timing constraint generating portion 7, a clock gating execution portion 8 and a clock line gate information generating portion 9.

[0044] The circuit information I/O portion 1 receives circuit information about logic circuit not clock-gated and then stores this information in the circuit information storage portion 4. Further, the circuit information I/O portion fetches clock-gated circuit information and timing constraint related to enable logic out of the circuit information storage portion 4 and outputs them.

[0045] The enable logic input portion 2 inputs enable logic in which circuit structure of an enable logic circuit for controlling clock output is described to the control portion 5 together with flip-flop name (e.g., FF0, FF1 . . . , etc.) subjected to the enable logic.

[0046] The gating information input portion 3 inputs gating information, clock signal frequency and duty ratio to the control portion 5. The gating information is referred to as information in which a structure of gating circuit is described. The gating circuit of the present embodiment includes a circuit for securing a normal operation of the logic circuit when an enable logic circuit is connected to the logic circuit. For example, if the enable logic circuit is directly connected to the gating circuit comprising an AND gate, such problem may occur that irregular clock pulses are inputted to the flip-flop. However, by structuring the gating circuit in the form of a circuit containing the flip-flop or inverter as well as the AND gate as shown in FIG. 9, this problem can be solved. Meanwhile, depending on the structure of the gating circuit, the other circuit does not have to be added as shown in, for example, FIG. 15.

[0047] The circuit information storage portion 4 stores circuit information about a logic circuit to be subjected to clock gating and circuit information about the logic circuit clock-gated.

[0048] The control portion 5 controls the operation of the respective portions according to an algorithm shown in a flow chart described later in order to execute clock gating for a given logic circuit.

[0049] The enable logic timing determination portion 6 calculates a delay time of enable logic based on virtual wiring delay information to determine whether or not that delay time satisfies the timing constraint, that is, whether or not a delay time from enable logic input to enable logic output is smaller than a delay time from clock rise to an edge of clock rise or clock fall. The virtual wiring delay information mentioned here refers to calculation information for use in estimating a delay of a logic circuit after the layout is completed.

[0050] The enable logic timing constraint generating portion 7 calculates timing constraint to be given to enable logic inputted to the control portion 5 by clock signal frequency and duty ratio.

[0051] The clock gating execution portion 8 adds gating circuit and enable logic circuit to a logic circuit stored in the circuit information storage portion 4 based on enable logic and gating information inputted to the control portion 5 to generate a clock-gated logic circuit. Circuit information about a newly generated logic circuit is described in a net list.

[0052] The clock line gate information portion 9 generates information about gate existing on a clock line in the form of clock line gate information. The clock line gate information refers to a list in which clock signal, gate circuit name, flip-flop name of each clock line are described.

[0053] The gated clock design supporting system 10 having the above described components is applied to a computer system shown in FIG. 4. This computer system includes CPU 21, ROM 22, RAM 23, magnetic disk unit 24, key board 25, mouse 26, write pen 27, flexible disk unit 28, display unit 29, and printer 30. In the same Figure, respective interface units are omitted. Here, typically circuit information about the logic circuit subjected to clock gating, enable logic and gating information are inputted through the key board 25. Further, they can be inputted through the flexible disk unit 28. The circuit information about a logic circuit subjected to clock gating can be also displayed on the display unit 29 through the mouse 26 and write pen 27 and then inputted. The circuit information about a clock-gated logic circuit is outputted to the display unit 29 and printer 30. Typically, the circuit information storage portion 4 in FIG. 3 corresponds to the magnetic disk unit 24.

[0054] Next, a processing procedure of clock gating in the gated clock design supporting system having the structure shown in FIG. 3 will be described with reference to a flow chart shown in FIG. 5. In a subsequent description, any circuit connected to the logic circuit for clock gating is generally called clock gating circuit.

[0055] First, circuit information about a logic circuit not clock-gated is inputted through the circuit information I/O portion 1 and stored in the circuit information storage portion 4 (step 101). Next, enable logic is inputted to the control portion 5 from the enable logic input portion 2 for clock gating together with the name of a flip-flop subjected to this logic. At the same time, gating information, clock signal frequency and duty ratio are inputted to the control portion 5 from the gating information input portion 3 (step 102). An example of the enable logic to be inputted is shown in FIG. 6.

[0056] Then, the control portion 5 calls the enable logic timing constraint generating portion 7, which obtains timing constraint to be secured for the enable logic inputted at step 102 according to clock signal frequency and duty ratio (step 103). Subsequently, the control portion 5 calls the enable logic timing determination portion 6 and then the enable logic timing determination portion 6 calculates a delay time of the enable logic according to virtual wiring delay and at the same time, determines whether or not that calculated enable logic delay time satisfies the timing constraint (steps 104, 105).

[0057] If it is determined that the timing constraint is not satisfied, the control portion 5 outputs an error message saying that a timing constraint error has occurred relating to an enable logic portion which does not satisfy the timing constraint, and terminates the processing (step 106). That is, an error message is displayed, for example, on the display unit 29. If it is determined that the timing constraint is satisfied, the control portion 5 calls the enable logic timing constraint generating portion 7, so that the enable logic timing constraint generating portion 7 generates timing constraint relating to the enable logic (step 107). The timing constraint generated here is used for realizing a layout satisfying the timing constraint in an automatic layout tool for logic elements. Next, the control portion 5 calls the clock gating execution portion 8 and the clock gating execution portion 8 adds information about clock gating circuit including enable logic circuit and gating circuit to circuit information stored in the circuit information storage portion 4 according to the enable logic and gating information inputted at step 102. Further, the control portion 5 calls the clock line gate information generating portion 9, and then the clock line gate information generating portion 9 generates information about the gate in which the generated clock signal and enable signal are inputted, in the form of the clock line gate information (step 108). The clock line gate information generated here is used for carrying out clock wiring without clock skew in automatic layout tool for the logic elements. Next, the control portion 5 fetches circuit information about the clock-gated logic circuit and timing constraint about enable logic, stored in the circuit information storage portion 4 and outputs them through the circuit information I/O portion 1 (step 109). That is, they are displayed on the display unit 29. Further, they can be printed through the printer 30.

[0058] Next, a concrete example of the aforementioned clock gating will be described and the operation of each component shown in FIG. 3 will be described in detail.

[0059] First, an example in which the gating circuit is formed of a circuit including an AND gate will be described.

[0060] Assume that a logic circuit having a partial circuit shown in FIG. 7 is inputted through the circuit information I/O portion 1. In FIG. 7, FF0, FF1, . . . FF31 indicate flip-flops and signal CLK indicates clock signal. In each flip-flop, D port indicates data input port and CK port indicates clock input port.

[0061] Assume that, for the flip-flops FF0, FF1, . . . FF31, enable logic information shown in FIG. 8 and gating information shown in FIG. 9 are inputted respectively from the enable logic input portion 2 and gating information input portion 3 to the circuit information storage portion 4. At the same time, assume that information saying that the clock signal cycle is 20 ns (nanosecond) and duty ratio is 50% is supplied from the gating information input portion 3 as shown by a timing chart of FIG. 10.

[0062] Then, the enable logic timing constraint generating portion 7 introduces timing constraint to be secured for the enable logic shown in FIG. 8 according to gating information shown in FIG. 9.

[0063] For example, in the case of the gating information 1, clock input of the enable flip-flop (EF1) is inverted by the inverter circuit. Thus, enable logic output must be fixed until the clock signal falls. That is, enable logic of the enable information 1 is secured with timing constraint of 10 ns.

[0064] In the case of gating information 2 shown in FIG. 9, assuming that enable F/F clock signal (ECLK) is the same as clock signal in terms of frequency and duty ratio and phase difference is 15 ns, because clock input to the enable flip-flop (EF2) is a signal having a phase difference of 15 ns relative to the clock signal, the enable logic of the enable information 2 shown in FIG. 8 is secured with timing constraint of 15 ns.

[0065] The enable logic timing determination portion 6 calculates a delay time of the enable logic according to virtual wiring delay and then determines whether or not the enable logic satisfies the timing constraint. In this case, it is assumed that it is satisfied. Here, the enable logic timing generating portion 7 generates timing constraint about the enable logic as shown in FIG. 11. Meanwhile, the timing constraint generated here is outputted as a final result.

[0066] Then, the clock gating execution portion 8 adds the enable logic circuit and gating circuit to the circuit information shown in FIG. 8 stored in the circuit information storage portion 4 according to the enable logic shown in FIG. 8 and gating information shown in FIG. 9 so as to produce circuit information about a logic circuit shown in FIG. 12. Further, the clock line gate information generating portion 9 generates information about a gate which inputs the generated clock signal and enable signal, in the form of clock line gate information as shown in FIG. 13.

[0067] The circuit information about the clock-gated logic circuit, timing constraint about the enable logic and clock line gate information, thus generated, are outputted through the circuit information I/O portion 1. That is, they are outputted to, for example, the display unit 29 or printer 30.

[0068] Next, as another specific example, a case in which the gating circuit is formed of OR gate will be described.

[0069] Assume that the logic circuit having a partial circuit shown in FIG. 7 is inputted through the circuit information I/O portion 1. Here, assume that, for the flip-flops FF0, FF1, . . . FF31, the information about enable logic shown in FIG. 14 and gating information shown in FIG. 15 are inputted respectively from the enable logic input portion 2 and gating information input portion 3 to the circuit information storage portion 4. Further, assume that as shown by a timing chart of FIG. 10, information saying that clock signal cycle is 20 ns and duty ratio is 50% is supplied through the gating information input portion 3.

[0070] Then, the enable logic timing constraint generating portion 7 introduces timing constraint to be secured for the enable logic shown in FIG. 14 according to the gating information shown in FIG. 15. In the case of gating information 1 shown in FIG. 15, the enable logic output must be fixed until the clock signal falls. That is, the enable logic of the enable information 1 of FIG. 14 is secured with the timing constraint of 10 ns.

[0071] Next, the enable logic timing determination portion 6 calculates a delay time of the enable logic according to virtual wiring delay so as to determine whether or not the delay time of the enable logic satisfies the timing constraint. In this case, it is assumed that it is satisfied. Here, the enable logic timing constraint generating portion 7 generates the timing constraint relating to the enable logic shown in FIG. 16. Then, the clock gating execution portion 8 adds the enable logic circuit and gating circuit to circuit information shown in FIG. 7 stored in the circuit information storage portion 4 according to the enable logic shown in FIG. 14 and gating information shown in FIG. 15 so as to generate circuit information about logic circuit shown in FIG. 17. The clock line gate information generating portion 9 generates clock line gate information shown in FIG. 18. The generated circuit information is outputted through the circuit information I/O portion 1. That is, it is outputted to the display unit 29 or printer 30.

[0072] As described above, according to the gated clock design supporting system of the present embodiment, by inputting the logic circuit not clock-gated as shown in FIG. 7, information about enable logic as shown in FIG. 8 (14), and gating information as shown in FIG. 9 (15), logic circuit clock-gated as shown in FIG. 12 (17), timing constraint relating to the enable logic as shown in FIG. 11 (16) and clock line gate information as shown in FIG. 13 (17) can be generated and then outputted.

[0073] Therefore, unlike conventional art, a designer does not have to carry out manually addition and correction about description of the enable logic circuit in a net list, so that design time can be reduced. Further, because there is no possibility that human correction error may occur, he is released from repeating the same work, so that time wasted in design work can be eliminated. Further, because the designer does not have to produce a complicated timing constraint to be given to design supporting CAD, reductions of design time and load on the designer are achieved. As explained here, the gated clock design supporting system according to the present embodiment is capable of automating various procedures of the gated clock design, so that a large reduction of design period can be attained.

[0074] Meanwhile, a program for achieving operation of the above described gated clock design supporting system can be stored in a computer readable memory. By reading that program from the memory by computer and executing the program to control the computer, the above gated clock design supporting system can be achieved. The memory mentioned here includes all recording mediums capable of recording the program, such as a memory device, a magnetic disk, a optical disk and the like.

[0075] It should be understood that many modifications and adaptations of the invention will become apparent to those skilled in the art and it is intended to encompass such obvious modifications and changes in the scope of the claims appended hereto.