Method and apparatus for reading memory cells of a resistive cross point array

[0002] The present invention relates to data storage devices. More specifically, the present invention relates to a data storage device including a resistive cross point array of memory cells and a method and apparatus for sensing resistance states of the memory cells in the array.

[0003] Magnetic Random Access Memory (“MRAM”) is a non-volatile thin-film memory that is being considered for data storage. A typical MRAM device includes an array of memory cells. Word lines extend along rows of the memory cells, and bit lines extend along columns of the memory cells. Each memory cell is located at a cross point of a word line and a bit line.

[0004] The MRAM memory cells may be based on spin dependent tunneling (“SDT”) junctions. A typical SDT junction has a pinned ferromagnetic layer, a sense ferromagnetic layer and an insulating tunnel barrier sandwiched between the ferromagnetic layers. A logic value may be written to an SDT junction by applying a magnetic field that sets the SDT junction's magnetization orientation to either parallel (logic ‘0’) or anti-parallel (logic ‘1’). Relative orientation and magnitude of spin polarization of the ferromagnetic layers determine the resistance state (R or R+ΔR) of the SDT junction.

[0005] Polymer memory is another non-volatile thin-film memory that is being considered for data storage. A polymer memory device also includes an array of memory cells, with word lines extending along rows of the memory cells, and bit lines extending along columns of the memory cells. The polymer memory cell includes a memory element that is based on polar conductive polymer molecules. Data is stored as a “permanent polarization” in a polymer molecule (in contrast to an SDT junction, where data is stored as a “permanent magnetic moment”). Polymer memory elements may be written by applying electric fields. Resistance state (R or R+ΔR) of a polymer memory element is dependant upon the orientation of polarization of the polymer molecules.

[0006] The logic value stored in the thin-film memory element may be read by sensing the resistance state of the memory element. During a read operation on a selected memory cell, an operating potential may be applied to the bit line crossing the selected memory cell, and a ground potential may be applied to the word line crossing the selected memory cell. Consequently, a sense current flows through the memory element of the selected memory cell. This sense current indicates the resistance state of the memory element.

[0007] However, the memory cells in the array are coupled together through many parallel paths. The resistance seen at one cross point equals the resistance of the memory cell at that cross point in parallel with resistances of memory cells in the other rows and columns. In this regard, the array of memory cells may be characterized as a cross point resistor network.

[0008] To prevent sneak path currents from obscuring the sense current, an equal operating potential is applied to a subset of unselected lines (e.g., the unselected bit lines). This “equipotential method” allows the sense current to be read reliably without the use of diodes or switches for blocking the sneak path currents. The “equipotential” method is disclosed in assignee's U.S. Ser. No. 09/564,308 filed Mar. 3, 2000, issued as U.S. Pat. No. 6,259,644, and incorporated herein by reference.

[0009] It is an objective of the present invention to reduce the amount of time for sensing the resistance states of the memory cells.

[0010] According to one aspect of the present invention, a sense amplifier is used to perform a read operation on a selected memory cell in a resistive cross point array of memory cells. An input of the sense amplifier is forced to a known, consistent condition; and then the sense amplifier is used to sense a resistance state of the memory cell.

[0011] Other aspects and advantages of the present invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the present invention.

[0012] FIG. 1 is an illustration of an information storage device according to the present invention;

[0013] FIGS. 2aand 2bare illustrations of a method of reading a memory cell in the device of FIG. 1;

[0014] FIG. 3 is an illustration of an exemplary sense amplifier for the device of FIG. 1;

[0015] FIG. 4 is an illustration of signals generated during a read operation by the hardware implementation of FIG. 3;

[0016] FIG. 5 is an illustration of capacitor voltage and sense amplifier input voltage during a series of read operations; and

[0017] FIGS. 6aand 6bare illustrations of sense and sneak path currents flowing through an electrical equivalent of a resistive cross point array of the device shown in FIG. 1.

[0018] As shown in the drawings for purposes of illustration, the present invention is embodied in an information storage device including an array of memory cells and at least one sense amplifier for reliably sensing resistance states of selected memory cells. During a read operation on a selected memory cell, a sense amplifier applies an operating potential to a selected bit line and an equal potential to a subset of unselected word and bit lines. Before a resistance state of the selected memory cell is sensed, an input of the sense amplifier is forced to a known, consistent condition. Applying the equal potential to the subset of unselected lines can prevent parasitic currents from interfering with the read operation on the selected memory cell. Forcing the sense amplifier input to the known, consistent condition reduces the time for sensing the resistance state of the selected memory cell.

[0019] Reference is made to FIG. 1, which illustrates an information storage device 8 including a resistive cross point array 10 of memory cells 12. The memory cells 12 are arranged in rows and columns, with the rows extending along an x-direction and the columns extending along a y-direction. Only a relatively small number of memory cells 12 are shown to simplify the explanation of the device 8. In practice, arrays of any size may be used.

[0020] Traces functioning as word lines 14 extend along the x-direction in a plane on one side of the memory cell array 10. Traces functioning as bit lines 16 extend along the y-direction in a plane on an opposite side of the memory cell array 10. There may be one word line 14 for each row of the array 10 and one bit line 16 for each column of the array 10. Each memory cell 12 is located at a cross point of a corresponding word line 14 and bit line 16.

[0021] The memory cells 12 may include thin-film memory elements. For example, data may be stored in a memory element as a “permanent magnetic moment” (in the case of MRAM technology) or a “permanent polarization” (in the case of polymer memory technology). Magnetic memory elements may be written by applying magnetic fields via the word and bit lines 14 and 16, whereas polymer memory elements may be written by applying electric fields via the word and bit lines 14 and 16. Resistance (R or R+ΔR) of an MRAM memory element is dependant upon the orientation of magnetization of a free layer, whereas resistance (R or R+ΔR) of a polymer memory element is dependant upon the orientation of polarization of polymer molecules.

[0022] The device 8 also includes a row decode circuit 18. During read operations, the row decode circuit 18 may apply either a constant array voltage (Vs) or a ground potential to the word lines 14. The constant array voltage (Vs) may be provided by an external circuit.

[0023] The device 8 further includes a read circuit for sensing the resistance states of selected memory cells 12 during read operations and a write circuit for orienting the magnetization of selected memory cells 12 during write operations. The read circuit is indicated generally at 20. The write circuit is not shown in order to simplify the explanation of the device 8.

[0024] The read circuit 20 includes a plurality of steering circuits 22 and sense amplifiers 24. Multiple bit lines 16 are connected to each steering circuit 22. Each steering circuit 22 includes a set of switches that may connect each bit line 16 to a source of operating potential or a sense amplifier 24. An output of the sense amplifier 24 is supplied to a data register 26, which, in turn, is coupled to an I/O pad 28 of the device 8.

[0025] The read circuit 20 further includes a plurality of pull-up transistors 30. During a read operation on a selected memory cell 12, a pull-up transistor 30 pulls up an input voltage (Vin) of the sense amplifier 24. The input voltage (Vin) is pulled up to the array voltage (Vs). Then the sense amplifier 24 senses a resistance state of the selected memory cell 12. By pulling up the sense amplifier input to the array voltage (Vs), the pull-up transistor 30 forces the sense amplifier input to a known, consistent condition. As will be explained below in connection with FIGS. 2ato 5, forcing the sense amplifier input to the known, consistent condition reduces the time for performing the read operations.

[0026] The device 8 also includes a control circuit 32 for generating an address strobe signal (STR), an integrator control signal (INT) that controls “settle” and “integration” phases of the read operations, a signal (SA) that controls the reset, preset, arm and store of the sense amplifiers 24, and a signal (PU) that controls the sequencing of the pull-up transistors 30 relative to the operation of the sense amplifiers 24. The control circuit 32 generates other signals for controlling the read and write operations. The control circuit 32 may be implemented as a state machine close to the memory cell array 10.

[0027] In the alternative, an external memory controller may generate the control signals.

[0028] FIG. 3 shows an exemplary sense amplifier 24, which includes a direct injection charge amplifier 52 and an integration capacitor 54. A steering circuit switch 56 coupling the charge amplifier 52 and capacitor 54 to the selected bit line will be referred to as the first switch 56. A second switch 58, which is part of the sense amplifier 24, couples the capacitor 54 to a source providing a V_DDvoltage.

[0029] The first switch 56 is closed to connect the selected bit line to the sense amplifier 24 and the second switch 58 is closed to charge the capacitor 54 to the V_DDvoltage. When the pull-up transistor 30 is pulsed, the sense amplifier input is charged to the array voltage (Vs).

[0030] Additional reference is made to FIGS. 2aand 2b, which illustrate a method of using the direct injection charge amplifier 52 and integration capacitor 54 to apply an equal potential to the array 10 during a read operation on a selected memory cell. At the beginning of a read operation, an address is selected (block 100) by connecting a selected word line 14 to the ground potential (the address select strobe signal STR sets the word line address), a selected bit line 16 to an input of the direct injection charge amplifier 52 and a subset of unselected lines to the array voltage (Vs). The voltage (Vs) applied to the unselected lines has the same magnitude as the voltage applied to the selected bit line. Thus, sneak path currents do not interfere with the sense current.

[0031] Next, the settle phase is initiated by connecting an output of the direct injection charge amplifier 52 to the V_DDvoltage (block 102). Shortly after the settle phase is initiated, the pull-up transistor 30 is pulsed by the control signal PU (block 104). Because the pull-up transistor 30 has low impedance, the selected bit line 16 and the input voltage (Vin) of the direct injection charge amplifier 52 are charged up quickly to the array voltage (Vs). Consequently, a known initial condition is applied to the selected bit line 16.

[0032] When the pull-up transistor 30 is turned off, the selected bit line voltage decays to an operation voltage that depends upon offset parameters of the direct injection charge amplifier. The direct injection charge amplifier 52 applies a regulated voltage (Vs) to the selected bit line 16.

[0033] A wait time (W1) is imposed to allow all voltage and current transients in the sense amplifier 24 to settle down to very low levels (block 106). If the direct injection charge amplifier 52 is ideal and does not have an offset, the sense current becomes stable immediately and the current may be sensed immediately. In practice, however, the direct injection charge amplifier 52 has an offset. The offset causes transients in the sense current. These transients should be allowed to settle before sensing the sense current.

[0034] Once the transients have settled, an integration phase begins. Just before the integration phase begins, however, the sense amplifier 24 is reset, preset and armed by the control signal SA.

[0035] Additional reference is now made to FIG. 4. The integration phase begins by discharging the integration capacitor 54 with the sense current (block 108). The voltage (Vcap) on the integration capacitor 54 decays at a rate that is dependent upon the resistance of the selected memory cell 12. The capacitor voltage (Vcap) will fall slower if the selected memory cell 12 has a higher resistance (R+ΔR) and the capacitor voltage (Vcap) will fall faster if the selected memory cell 12 has a lower resistance (R).

[0036] The time for the capacitor voltage (Vcap) to decay to a reference voltage (Vt) is measured (block 110), and the measured time is compared to a threshold (block 112). A first comparator 60 compares the capacitor voltage (Vcap) to a threshold voltage (Vt). The resistance state of the selected memory cell 12 and, therefore, logic value of the selected memory cell 12 can then be determined according to the time for reaching the threshold voltage (Vt).

[0037] For example, a second comparator 62 may compare an output of the first comparator 60 to a clock pulse (CP), which transitions from high to low (or vice versa) at a specific time. An output of the second comparator 62 provides a data signal (DAT) to the data register 32. If the capacitor voltage (Vcap) drops below the threshold voltage (Vt) before the clock pulse CP transitions, the data signal (DAT) indicates a logic value (indicated by the solid line) corresponding to the low cell resistance (R). If the capacitor voltage (Vcap) drops below the threshold (Vt) after the clock transitions, the data signal (DAT) provides a logic value (indicated by the dashed line) corresponding to the high cell resistance (R+ΔR).

[0038] The threshold voltage (Vt) may be a dc voltage that is less than the V_DDvoltage but greater than the array voltage (Vs). That is, Vs<Vt<V_DD. The transition of the clock pulse (CP) may occur at a time (T0) between a first switching threshold time (T1) of the high resistance state and a second switching threshold time (T2) of the low resistance state. Both the threshold voltage (Vt) and the clock pulse (CP) may be generated by an external reference circuit.

[0039] FIG. 5 shows the capacitor voltage (Vcap) and sense amplifier input voltage (Vin) over four read operations. During each read operation, the pull-up transistor 30 is pulsed (by control signal PU) before the sense current is integrated. Although the pull-up transistor 30 is pulsed for a finite duration, that finite duration is shorter than the time for the transients to settle out. For example, the finite duration may be 10% of the settle time.

[0040] The first read operation is performed on a selected memory cell having a high resistance state, the second read operation is performed on a selected memory cell having a low resistance state, the third read operation is performed for a short integration time, and the fourth read operation is performed for a long integration time. For each read operation, the sense amplifier input starts at the same voltage.

[0041] Without the pull-up transistor 30, the initial condition at the beginning of the “settle” phase dictates the duration of the “settle” phase. Short integration times and sensing high resistance values would normally lead to the charge amplifier 52 operating in a linear mode and voltages in the charge amplifier 52 being above saturation levels. Resulting would be a shorter “settle” phase. Long integration times and sensing low resistance values would lead to an initial condition of the charge amplifier operating in saturation. Resulting would be a longer “settle” phase.

[0042] With the pull-up transistor 30, however, all four read operations begin at the same voltage on the sense amplifier input. As a result, each of the four read operations has a short ‘settle’ phase.

[0043] FIGS. 6aand 6bshow how the equipotential method prevents sneak path currents from interfering with the read operations. FIG. 6ashows an electrical equivalent of the memory cell array 10. A selected memory cell is represented by a first resistor 12a, and unselected memory cells are represented by second, third and fourth resistors 12b, 12cand 12d. The second resistor 12brepresents the unselected memory cells along the selected bit line, the third resistor 12crepresents the unselected memory cells along the selected word line, and the fourth resistor 12drepresents the remaining unselected memory cells. If, for example, all of the memory cells 12 have a nominal resistance of about R and if the array 10 has n rows and m columns, then the second resistor 12bwill have a resistance of about R/(n−1), the third resistor 12cwill have a resistance of about R/(m−1), and the fourth resistor 12dwill have a resistance of about R/[(n−1)(m−1)].

[0044] The first resistor 12amay be selected by applying the array voltage (Vs) to the crossing bit line and a ground potential to the crossing word line. Consequently, a sense current (I_s) flows through the first resistor 12a. However, the second, third and fourth resistors 12b, 12cand 12dare also coupled between the array voltage (Vs) and the ground potential.

[0045] To mitigate the effects of sneak path currents during read operations, the same operating potential Vb=Vs is applied to the unselected bit line. If Vb=Vs, sneak path currents will be blocked from flowing through the second and fourth resistors 12band 12d, and a sneak path current S3 flowing through the third resistor 12cwill be directed to the ground potential and, therefore, will not interfere with the sense current (I_s).

[0046] In the alternative, the effects of the sneak path currents may be mitigated by applying the same operating potential Vb=Vs to the unselected word line, as shown in FIG. 6b. A sneak path current will be blocked from flowing through the second resistor 12b. Sneak path currents S3 and S4 flowing through the third and fourth resistors 12cand 12dwill be directed to the ground potential and, therefore, will not interfere with the sense current (I_s).

[0047] Thus, applying an equal potential to the unselected bit or word lines of the array 10 can eliminate or reduce the obscuration of the sense current (I_s). Consequently, the sense current (I_s) and, therefore, the resistance state of the selected memory cell are determined reliably.

[0048] Thus disclosed is an information storage device in which resistance states of memory cells can be sensed reliably and quickly during read operations. Sneak path currents are blocked or re-directed so as not obscure sense currents during read operations. The pull-up transistors force the read operations to begin at the same initial condition for every read. The initial condition is achieved, quickly and independently of the resistance state of the memory cell. Quickly pulling up the sense amplifier input and consistently starting at the same initial voltage reduces the time to wait for the transients to settle and reduces the time for performing the read operations.

[0049] The sense amplifier is not limited to any particular type. However, the sense amplifier of FIG. 3 is preferred.

[0050] The reference voltages and other reference signals (e.g., thresholds) may be generated in any number of ways. For example, a reference voltage may be established by a simple resistive network of dummy memory cells. Other examples of generating reference voltages are provided in the assignee's U.S. Ser. No. 09/598,671 filed Jun. 20, 2000.

[0051] The memory cells of the resistive cross point array are not limited to any particular type of memory element. For instance, MRAM elements could include giant magnetoresistance (“GMR”) memory elements.

[0052] The present invention is not limited to the specific embodiments described and illustrated above. Instead, the invention is construed according to the claims that follow.