Semiconductor device with multilayer interconnection having HSQ film with implanted fluorine and fluorine preventing liner

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor device with multilevel interconnection structure and a manufacturing method thereof, and more particularly, it relates to a semiconductor device with a multilevel interconnection whose wiring capacitance is reduced and a manufacturing method thereof.

[0004] 2. Description of the Related Arts

[0005] There is observed an effective wherein as the wiring pitch becomes smaller, and the distance between adjacent wires becomes shorter, the wiring capacitance increases as a semiconductor device becomes more minute. When the wiring capacitance increases, the operational speed of a circuit becomes slower, the electric power consumed becomes larger. Therefore, for reducing wiring capacitance, it is required to use a low dielectric constant film as an interlayer insulating film.

[0006] An inorganic SOG (Spin-on-glass) such as HSQ (hydrogen silsesquioxane) has a comparatively low dielectric constant of approximately 3.0, and further, it has a thermal resistance of approximately 400° C., and therefore, it is a very useful material. However, the dielectric constant of HSQ is still high when compared with that of an organic film, and it is desired to further lower this dielectric constant of HSQ. As a method to reduce the dielectric constant of an inorganic SOG film, for example, there is a method shown in “Study of Porous Interlayer Insulating Film Material” Aoi, et al. (Proceedings of the 52th symposium on Semiconductor and Integrated Circuits Technology, pp. 62-67 (1997), in which silylation is performed by adding a silylation agent to an SOG solution, coupled with, amine processing the resulting dielectric constant is lowered to approximately 2.3, the diameter of a pore is made fine, and humidity resistance is improved.

[0007] However, in the above conventional semiconductor device with multilayer structure, solution processing is troublesome, and there is also a problem in stability of wiring capacitance.

[0008] In Japanese Patent Laid-Open Publication No. 8-250490, a method is disclosed, where a thin film of a modified HSQ thin film precursor is coated on a semiconductor substrate with a conductor. This HSQ thin film precursor comprises a hydrogen silsesquioxane resin, and preferably a modifier selected from among the group consisting of alkylalkoxysilane, alkylalkoxysilane fluoride, and a combination thereof. However, the prior art described in this publication also has a weak point because solution processing is troublesome and the stability of wiring capacitance is low.

[0009] It is an object of the present invention to provide a semiconductor device with a multilevel interconnection in which the dielectric constant of HSQ is low and wiring capacitance can be reduced, and a manufacturing method thereof.

[0010] A semiconductor device with a multilevel interconnection according to the present invention comprises a hydrogen silsesquioxane film made porous by etching with hydrogen fluoride and used as an interlayer insulating film for filling the space between wires.

[0011] Another semiconductor device with a multilevel interconnection according to the present invention comprises hydrogen silsesquioxane film made porous by ion-implantation of impurities containing fluorine used as an interlayer insulating film for filling the space between wires.

[0012] In this semiconductor device with a multilevel interconnection, it is preferable to perform said ion-implantation of impurities containing fluorine under the condition of 10 to 30 keV and 1×10¹⁴to 3×10¹⁵cm⁻².

[0013] A manufacturing method of a semiconductor device with a multilevel interconnection according to the present invention comprises the steps of disposing a hydrogen silsesquioxane film so as to fill the space between wires, baking the hydrogen silsesquioxane film, and implanting impurities containing fluorine by ion-implantation.

[0014] In this manufacturing method of a semiconductor device with a multilevel interconnection, it is preferable to perform said ion-implantation of impurities containing fluorine under the condition of 10 to 30 keV and 1×10¹⁴to 3×10¹⁵cm⁻².

[0015] According to the present invention, the dielectric constant of an HSQ film is low, and wiring capacitance can remarkably be reduced. Furthermore, according to the present invention, HSQ is made porous by etching of hydrogen fluoride or ion-implantation of impurities containing fluorine, and therefore the processing is extremely easy.

[0016] FIG. 1 is a cross sectional view showing a semiconductor device with a multilevel interconnection according to a first embodiment of the present invention;

[0017] FIG. 2 is a cross sectional view showing 1 step of a manufacturing method;

[0018] FIG. 3 is a cross sectional view showing the next step;

[0019] FIG. 4 is a cross sectional view showing the next step;

[0020] FIG. 5 is a cross sectional view showing the next step;

[0021] FIG. 6 is a figure showing an advantageous effect of the present invention; and

[0022] FIG. 7 is a cross sectional view showing a semiconductor device with a multilevel interconnection according to a second embodiment of the present invention.

[0023] Preferred embodiments of the present invention will concretely be described below by referring to accompanying drawings. FIG. 1 is a cross sectional view showing a semiconductor device according to an embodiment of the present invention. On the surface of a semiconductor substrate 1, element separating areas 2 are formed, and between these element separating areas 2, a diffusion layer area 3 is provided. Then, on the substrate 1, a first interlayer insulating film 4 is formed, and on this first interlayer insulating film 4, a first layer wiring 7 comprising aluminum is patterned through a barrier metal layer 6. On the first layer wiring 7, a high fusing point metal layer 8 is formed, and to cover the first layer wiring 7 and the high fusing point metal layer 8, a plasma oxide film 9 is formed. Then, to fill the space between these wires, a porous hydrogen silsesquioxane film (hereafter, referred to simply as an HSQ film) 10 is formed. This HSQ film 10 is made porous by etching action of hydrogen fluoride or by ion-implantation of impurities containing fluorine. Then, on this HSQ film 10, a plasma SiON layer 11 and a plasma oxide film 12 are formed, and the upper surface of the plasma oxide film 12 is made flat. Accordingly, under the porous HSQ film 10, a liner film (film thickness: approximately 50 nm) comprising the plasma oxide film 9 exists, and on the porous HSQ film 10, the plasma SiON layer 11 (film thickness: approximately 50 nm) exists, and on that, a plasma oxide film 12 exists.

[0024] A second layer wiring layer with the same structure is formed on the first layer wiring layer. That is, on a plasma oxide film 12, a high fusing point metal layer 17, a second layer wiring 16 comprising aluminum, a high fusing point metal layer 19, a plasma oxide film 20, a porous HSQ film 21, a plasma SiON layer 22, and a plasma oxide film 23 are formed, and the surface of this plasma oxide film 23 is made flat.

[0025] Moreover, on the second layer wiring layer, a third layer wiring layer is formed. That is, on a plasma oxide film 23, a high fusing point metal layer 28 is formed, and on this high fusing point metal layer 28, a third layer wiring 27 comprising aluminum is patterned. Then, on this third layer wiring 27, a high fusing point metal layer 30 is formed, and a cover film 31 is formed so as to cover each space between wires.

[0026] As mentioned above, the present embodiment has 3 layer wiring structure, and an interlayer insulating film between the second layer wiring 16 and the third layer wiring 27 also has the same structure as the interlayer insulating film between the first layer wiring 7 and the second layer wiring 16.

[0027] Then, the first layer wiring 7 and the second layer wiring 16 are connected by a via hole 13, and the peripheral surface of this via hole 13 is covered by the high fusing point metal layer 17, and further, the interior of the via hole 13 is filled up by a tungsten area 15, and this tungsten area 15 electrically connects the first layer wiring 7 and the second layer wiring 16. Similarly, the second layer wiring 16 and the third layer wiring 27 are connected by a via hole 24, the high fusing point metal layer 28, and the tungsten area 26.

[0028] In a semiconductor device composed like this, HSQ films 10, 21 as interlayer insulating films existing between the first layer wiring 7 and the second layer wiring 16 and between the second layer wiring 16 and the third layer wiring 27 are formed with porous HSQ, and therefore, the dielectric constant is extremely low, and the wiring capacitance can remarkably be reduced. Consequently, the acting speed of a circuit using a multilayer wiring becomes fast. On the other hand, since this porosity of HSQ is made by etching action of HF, the manufacturing process of a semiconductor is uncomplicated, and the stability of the manufacturing process is also high.

[0029] Next, a manufacturing method of this semiconductor device with a multilevel interconnection will be described. FIG. 2 to FIG. 5 are cross sectional views showing the manufacturing method of a semiconductor device according to an embodiment of the present invention in the order of steps. First, as shown in FIG. 2, on a semiconductor substrate 1 where an element separating area 2 and a diffusion layer area 3 are formed, a first interlayer insulating film 4 is formed, and on that, a first layer wiring 5 is formed. The first layer wiring 5 comprises, for example, titanium (film thickness: 30 nm), a barrier metal layer 6 including titanium nitride (film thickness: 50 nm), aluminum, and a high fusing point metal layer 8 including titanium such as titanium nitride in this order from the bottom. A liner film (film thickness: approximately 50 nm) comprising a plasma oxide film 9 is formed, and an HSQ film 41 (film thickness: approximately: 0.4 microns at the flat portion) is coated, and baking (approximately 400° C.) is performed.

[0030] Next, as shown in FIG. 3, ion-implantation of fluorine 42 is performed (10 to 30 keV and 1×10¹⁴to 3×10¹⁵cm⁻²). This ion-implantation is performed under the condition that the peak comes at a depth of approximately half of the film thickness of the HSQ film 41.

[0031] Next, as shown in FIG. 4, a plasma SiON 11 (film thickness: approximately 50 nm) is formed, and a plasma oxide film 12 is formed to have a film thickness of approximately 1.4 μm, and it is made flat by a chemical and mechanical polishing (CMP).

[0032] Next, as shown in FIG. 5, a via hole 13 is selectively opened, and the interior of a high fusing point metal 17 containing titanium such as titanium nitride (film thickness: approximately 500 Å) is filled up by a conductor (tungsten 15), and a second layer wiring 16 is formed. By repeating the same process, it is also possible to form wiring of more multiple layers.

[0033] In the present embodiment, by performing ion-implantation of fluorine to the HSQ film 10, Si—H connection in the HSQ film is broken, and fluorine and hydrogen are connected to be hydrogen fluoride (HF). When this is formed in the HSQ film, the HSQ film becomes porous, and the dielectric constant lowers. Then, since the HSQ film is buried in a space between adjacent wires in large amounts, the wiring capacitance is largely reduced.

[0034] By the way, it is also possible to make the HSQ film porous by etching action of hydrogen fluoride instead of ion-implantation of impurities containing fluorine.

[0035] FIG. 6 is a figure of a graph showing a difference in wiring capacitance between the present embodiment (first embodiment) and a conventional semiconductor device by comparing them, taking wiring capacitance in the vertical axis. A width and a space of wires are respectively 0.3 μm and 0.3 μm, and a film thickness of wires is approximately 0.6μm. In the first embodiment, reduction of capacity of approximately 5% is achieved when compared with the case of a conventional HSQ.

[0036] Next, another embodiment of the present invention will be described by referring to FIG. 7. In FIG. 7, the same numerals are given to the components identical with those in FIG. 1, and the detailed description thereof will be omitted. The present embodiment is different from the first embodiment shown in FIG. 1 in that plasma SiON layers 43, 44 are formed instead of plasma oxide films 9, 20 of the first layer wiring layer and the second layer wiring layer of the first embodiment. In the present embodiment, an HSQ film 10 made porous by etching action of hydrogen fluoride also exists between wires of the first layer wiring 7 and on the first layer wiring 7. Under this porous HSQ film 10, there is a liner film (film thickness: approximately 50 nm) 43 comprising a plasma SiON layer. Furthermore, on the porous HSQ film 10, there is a plasma SiON layer (film thickness: approximately 50 nm) 11, and on that, there is a plasma oxide film 12. The upper surface of this plasma oxide film 12 is made flat. Furthermore, a plasma SiON layer 44 is also used for a liner film under the porous HSQ film 21 buried between wires of the second layer wiring 16.

[0037] In this embodiment, a plasma SiON layer 43 is used as a liner film under the porous HSQ film, and therefore, there is such an effect that it is possible to prevent HF generated in the HSQ film from diffusing in the wiring direction, and that it is possible to prevent corrosion of wiring.

[0038] Moreover, it is sufficient that impurities implanted into the HSQ layer by ion-implantation contain fluorine, and for example, BF₂is also possible. In this case, it is necessary to perform implantation with accelerating energy larger than that of B ions.

[0039] In the present invention, the wiring capacitance is also remarkably reduced as shown in the second embodiment of FIG. 6.