US 6,316,810 B1Grant
Display switch with double layered gate insulation and resinous interlayer dielectric
Issue Date:2001-11-13
•50 Claims
•11 Drawing Sheets
Abstract
Concentration of metal element which promotes crystallization of silicon and which exists within a crystal silicon film obtained by utilizing the metal element is reduced. A first heat treatment for crystallization is implemented after introducing nickel element to an amorphous silicon film 103. Then, after obtaining the crystal silicon film, another heat treatment is implemented within an oxidizing atmosphere at a temperature higher than that of the previous heat treatment. At this time, HCl or the like is added to the atmosphere. A thermal oxide film 106is formed in this step. At this time, gettering of the nickel element into the thermal oxide film 106takes place. Next, the thermal oxide film 106is removed. Thereby, a crystal silicon film 107having low concentration of the metal element and a high crystalinity can be obtained.
Metadata
Assignee
- Semiconductor Energy Laboratory Co., Ltd.
Inventors
- Shunpei Yamazaki
- Satoshi Teramoto
- Jun Koyama
- Yasushi Ogata
- Masahiko Hayakawa
- Mitsuaki Osame
Application Information
Application Number:US 09/350,176
Filing Date:1999-07-09
Priority Date:1996-01-19
Art Unit:7
Classifications
IPC:
H01L 2900
Field of Search:
257 72257408257410257411257353
Patent Drawings (11 sheets)
Description
[0002] This application is a Division of application Ser. No. 08/783,866, filed Jan. 16, 1997. U.S. Pat. No. 5,985,740.
Detailed Description of the Invention
[0003] 1. Field of the Invention
[0004] The present invention relates to a semiconductor device typified by a thin film transistor and to a fabrication method thereof. Specifically, the present invention relates to a semiconductor device using a crystal silicon thin film formed on a glass substrate or a quartz substrate and to a fabrication method thereof.
[0005] 2. Description of Related Art
[0006] Hitherto, there has been known a thin film transistor using a silicon film, i.e. a technology for forming the thin film transistor by using the silicon film formed on a glass substrate or quartz substrate.
[0007] The glass substrate or quartz substrate is used because the thin film transistor is used for an active matrix type liquid crystal display. While a thin film transistor has been formed by using an amorphous silicon film in the past; it is being tried to fabricate the thin film transistor by utilizing a silicon film having a crystalinity (referred to as “crystal silicon film” hereinbelow) in order to enhance its performance.
[0008] The thin film transistor using the crystal silicon film allows to operate at high speed by more than two digits as compared to one using the amorphous silicon film. Therefore, while peripheral driving circuits of an active matrix liquid crystal display have been composed of external IC circuits, they may be built on the glass substrate or quartz substrate similarly to the active matrix circuit.
[0009] Such structure is very advantageous in miniaturizing the whole apparatus and in simplifying the fabrication process, thus leading to the reduction of the fabrication cost.
[0010] In general, a crystal silicon film has been obtained by forming an amorphous silicon film by means of plasma CVD or reduced pressure thermal CVD and then by crystallizing it by implementing a heat treatment or by irradiating laser light.
[0011] However, it has been the fact that it is difficult to obtain a required crystalinity across the wide area through the heat treatment because it may cause nonuniformity in the crystallization.
[0012] Further, although it is possible to obtain the high crystalinity partly by irradiating laser light, it is difficult to obtain a good annealing effect across the wide area. In particular, the irradiation of the laser light is apt to become unstable under the condition for obtaining the good crystalinity.
[0013] Meanwhile, a technology described in Japanese Patent Laid-Open No. Hei. 6-232059 has been known. This is a technology which allows to obtain a crystal silicon film through a heat treatment at a lower temperature than that of the prior art by introducing a metal element (e.g. nickel) which promotes the crystallization of silicon to the amorphous silicon film.
[0014] According to studies conducted by the inventors et. al. it has been found that the crystal silicon film obtained by this method has crystalinity which is good for practical use across the wide area.
[0015] However, it has been also found that because the metal element is contained within the film and the amount thereof to be introduced has to be controlled very carefully, there is a problem in its reproducibility and stability (electrical stability of a device obtained).
[0016] Further, there is a problem that an elapsed change of the characteristics of a semiconductor device to be obtained is large or an OFF value, in case of a thin film transistor, is large, for example due to the influence of the remaining metal element.
[0017] That is, although the metal element which promotes the crystallization of silicon plays the useful role in obtaining the crystal silicon film, its existence becomes a minus factor which causes various problems after obtaining the crystal silicon film once.
Problems to Be Solved by the Invention
[0018] It is an object of the invention disclosed in the present specification to provide a technology for reducing concentration of metal element within a crystal silicon film obtained by utilizing the metal element which promotes crystallization of silicon.
[0019] It is another object of the present invention to provide a technology which can enhance characteristics and reliability of a semiconductor device thus obtained.
Means for Solving the Problems
[0020] One of the invention disclosed in the present specification is characterized in that it comprises steps of intentionally introducing metal element which promotes crystallization of silicon to an amorphous silicon film and crystallizing the amorphous silicon film by a first heat treatment to obtain a crystal silicon film; eliminating or reducing the metal element existing within the crystal silicon film by implementing a second heat treatment within an oxidizing atmosphere containing a halogen element; eliminating a thermal oxide film formed in the previous step; and forming another thermal oxide film on the surface of the domain from which the thermal oxide film has been eliminated by implementing another thermal oxidation.
[0021] An arrangement of another invention is characterized in that it comprises steps of intentionally introducing metal element which promotes crystallization of silicon to an amorphous silicon film and crystallizing the amorphous silicon film by a first heat treatment to obtain a crystal silicon film; eliminating or reducing the metal element existing within the crystal silicon film by implementing a second heat treatment within an oxidizing atmosphere containing a halogen element to form a thermal oxide film on the surface of the crystal silicon film and by causing the thermal oxide film to getter the metal element; eliminating the thermal oxide film formed in the previous step; and forming another thermal oxide film on the surface of the domain from which the thermal oxide film has been eliminated by implementing another thermal oxidation.
[0022] An arrangement of another invention is characterized in that it comprises steps of intentionally introducing a metal element which promotes crystallization of silicon to an amorphous silicon film and crystallizing the amorphous silicon film by a first heat treatment to obtain a crystal silicon film; eliminating or reducing the metal element existing within the crystal silicon film by implementing a second heat treatment within an oxidizing atmosphere containing a halogen element; eliminating a thermal oxide film formed in the previous step; forming an active layer of a thin film transistor by implementing patterning; and forming another thermal oxide film which composes at least a part of a gate insulating film on the surface of the active layer by means of thermal oxidation.
[0023] An arrangement of another invention is characterized in that it comprises steps of selectively introducing a metal element which promotes crystallization of silicon to an amorphous silicon film; growing crystal by a first heat treatment in a direction parallel to the film from the domain to which the metal element has been selectively introduced; forming a thermal oxide film on the surface of the domain where the crystal has been grown by implementing a second heat treatment within an oxidizing atmosphere containing a halogen element; eliminating the thermal oxide film; and forming an active layer of the semiconductor device by using the domain from which the thermal oxide film has been eliminated.
[0024] In the invention disclosed in the present specification, one or a plurality elements selected from Fe, Co, Ni, Ru, Rh, Pd, Os, Ir, Pt, Cu and Au may be used as the metal element which promotes the crystallization of silicon.
[0025] Further, as the oxidizing atmosphere containing the halogen element, an atmosphere to which one or a plurality of gases selected from HCl, HF, HBr, Cl2, F2or Br2is added into the O2atmosphere or an atmosphere containing O2may be used.
[0026] An arrangement of another invention is characterized in that a semiconductor device has a crystal silicon film interposed between a first and second oxide films; the crystal silicon film contains hydrogen and a halogen element as well as a metal element which promotes crystallization of silicon; and the metal element is distributed in high concentration near the interfaces with the first/second oxide film within the crystal silicon film.
[0027] The above-mentioned arrangement is characterized in that the halogen element is distributed in high concentration within the first oxide film or near the interface between the first oxide film and the crystal silicon film.
[0028] Further, the above-mentioned arrangement is characterized in that the halogen element is distributed in high concentration within the crystal silicon film near the interface with the second oxide film.
[0029] The above-mentioned arrangement is also characterized in that the first oxide film is a silicon oxide film or a silicon oxide nitride film formed on a glass substrate or a quartz substrate, the crystal silicon film constitutes an active layer of a thin film transistor and the second oxide film is a silicon oxide film or a silicon oxide nitride film constituting a gate insulating film.
[0030] An arrangement of another invention is characterized in that a semiconductor device comprises an underlying layer made of an oxide film; a crystal silicon film formed on the underlying layer; and a thermal oxide film formed on the crystal silicon film; wherein the crystal silicon film contains a metal element which promotes crystallization of silicon, hydrogen and a halogen element; the metal element which promotes the crystallization of silicon is distributed in high concentration near the interface with the underlying layer/the thermal oxide film; the halogen element is distributed in high concentration near the interface with the underlying layer/the thermal oxide film; and the thermal oxide film composes at least part of a gate insulating film of a thin film transistor.
[0031] The concentration of impurity in the present specification is defined as the minimum value of measured values measured by the SIMS (secondary ion mass spectrometry).
Mode for Carrying Out the Invention
[0032] According to a preferred mode for carrying out the invention disclosed in the present specification, an amorphous silicon film is formed at first. Then, the amorphous silicon film is crystallized by an action of metal element typified by nickel which promotes crystallization of silicon to obtain a crystal silicon film. The crystallization is carried out by heat treatment.
[0033] The metal element is contained in the crystal silicon film in this state. Then, another heat treatment is implemented within an oxidizing atmosphere to which HCl is added to form a thermal oxide film on the surface of the crystal silicon film.
[0034] At this time, the metal element is gettered to the thermal oxide film by the action of chlorine and the concentration of the metal element within the crystal silicon film drops. Further, the nickel element is gasified and removed to the outside by the action of chlorine.
[0035] Then, the crystal silicon film having the high crystalinity, and having low concentration of the metal element may be obtained by eliminating the thermal oxide film to which the element has been gettered.
Description of Preferred Embodiments
[0036] First Embodiment
[0037] An arrangement for obtaining a crystal silicon film on a glass substrate by utilizing nickel element will be explained in the present embodiment.
[0038] At first, the crystal silicon film having a high crystalinity is obtained by an action of nickel element in. the present embodiment.
[0039] Next, a thermal oxide film containing halogen element is formed on the crystal silicon film by thermal oxidation. At this time, the nickel element remaining in the crystal silicon film thus obtained is gettered to the thermal oxide film by the action of the halogen element.
[0040] Then, the thermal oxide film containing the nickel element in high concentration as a result of the gettering is eliminated. Thereby, the crystal silicon film having nickel element in low concentration while having the high crystalinity is obtained on the glass substrate.
[0041] A fabrication process of the present embodiment will be explained by using FIG. 1 below. At first, a silicon oxide nitride film 102 is formed as an underlying film in a thickness of 3000 angstrom on the glass substrate 101 of Coning 1737 (distortion point: 667° C.).
[0042] The silicon oxide nitride film is formed by using plasma CVD using sillane, N2O gas and oxygen as original gases. Or, it may be formed by using plasma CVD using TEOS gas and N2O gas.
[0043] The silicon oxide nitride film has a function of suppressing the diffusion of impurities from the glass substrate in. the later steps (seeing from the level of fabrication of a semiconductor, a glass substrate contains a large amount of impurities).
[0044] It is noted that although the silicon nitride film is most suitable to maximize the function of suppressing the diffusion of the impurities, the silicon nitride film is not practical because it is peeled off from the glass substrate due to the influence of stress. A silicon oxide film may be also used as the underlying film instead of the silicon oxide nitride film.
[0045] It is also important to increase the hardness of the underlying film 102 as much as possible. It is concluded from the fact that the harder the hardness of the underlying film (i.e. the smaller the etching rate thereof), the higher the reliability is in an endurance test of the thin film transistor obtained in the end. It is assumed to be caused by the effect of blocking the impurities from the glass substrate in the fabrication process of the thin film transistor.
[0046] It is also effective to include a small amount of halogen element typified by chlorine in the underlying film 102. Thereby, the metal element which promotes crystallization of silicon and which exists within the semiconductor layer may be gettered by the halogen element in the later step.
[0047] It is also effective to add a hydrogen plasma treatment after forming the underlying film. It is also effective to implement a plasma treatment in an atmosphere in which oxygen and hydrogen are mixed. These treatments are effective in eliminating carbon component which is adsorbed on the surface of the underlying film and in enhancing the characteristic of interface with a semiconductor film formed later.
[0048] Next, an amorphous silicon film 103, which turns out to be a crystal silicon film later, is formed in a thickness of 500 angstrom by the reduced pressure thermal CVD. The reason why the reduced pressure thermal CVD is used is because thereby, the quality of the crystal silicon film obtained later is better, i.e. the film quality is denser in concrete. Beside the reduced pressure thermal CVD, the plasma CVD may be used.
[0049] The amorphous silicon film fabricated here is desirable to have 5×1017cm−3to 2×1019cm−3of concentration of oxygen within the film. It is because oxygen plays an important role in the later step of gettering the metal element which promotes crystallization of silicon.
[0050] However, it must be careful here because the crystallization of the amorphous silicon film is hampered if the oxygen concentration is higher than the above-mentioned range of concentration.
[0051] The concentration of other impurities such as those of nitrogen and carbon is preferred to be low to the utmost. In concrete, the concentration must be below 2×1019cm−3.
[0052] The thickness of the amorphous silicon film 103 is 1600 angstrom. The thickness of the amorphous silicon film must be thicker than a thickness required in the end as described later.
[0053] When the amorphous silicon film 103 is crystallized by means of only heating, the thickness of the starting film (amorphous silicon film) 103 is set at 800 angstrom to 5000 μm or preferably, 1500 to 3000 angstrom. It is uneconomical from the aspect of production cost if the thickness is thicker than the above-mentioned thickness range because it takes more time in forming the film. When the thickness is thinner than the above-mentioned thickness range on the other hand, the crystal may be grown non-uniformly or the reproducibility of the process may become bad.
[0054] Thus, the state shown in FIGS. 1A-1E is obtained.
[0055] Next, nickel element is introduced to the amorphous silicon film 103 to crystallize it. Here, the nickel element is introduced by applying nickel acetate solution containing 10 ppm (reduced to weight) of nickel on the surface of the amorphous silicon film 103.
[0056] Beside the method of using the above-mentioned solution, sputtering, CVD, plasma treatment or adsorption may be used as the method for introducing the nickel element.
[0057] The method of using the solution is useful in that it is simple and that the concentration of the metal element may be readily adjusted.
[0058] The nickel acetate solution is applied as described above to form a water film (liquid film) 104 as shown in FIG. 1B. In this state, extra solution is blown out by using a spin coater not shown. Thus, the nickel element is held in contact on the surface of the amorphous silicon film 103.
[0059] It is noted that it is preferable to use nickel sulfate solution for example, instead of using the nickel acetate, if the remained impurities in the later heating process is taken into consideration. It is because the nickel acetate contains carbon and it might be carbonized in the later heating process, thus remaining within the film.
[0060] An amount of the nickel element to be introduced may be controlled by adjusting the concentration of nickel element within the solution.
[0061] Next, a heat treatment is implemented in the temperature range from 450° C. to 650° C. in the state shown in FIG. 1C to crystallize the amorphous silicon film 103 and to obtain a crystal silicon film 105. This heat treatment is implemented in a reducing atmosphere.
[0062] Here, the heat treatment is implemented for four hours at 620° C. within a nitrogen atmosphere containing 3% of hydrogen.
[0063] The reason why the reducing atmosphere is adopted in the crystallization step in a way of the heat treatment is to prevent oxides from being created in the step of the heat treatment and more concretely, to suppress nickel from reacting with oxygen and NiOx from being created on the surface of the film or within the film.
[0064] Oxygen couples with nickel and contributes a lot in gettering nickel in the later gettering step. However, it has been found that if oxygen couples with nickel in the above-mentioned stage of the crystallization, it hampers the crystallization. Accordingly, it is important to suppress the oxides from being created to the utmost in the crystallization step in a way of heating.
[0065] The concentration of oxygen within the atmosphere for implementing the heat treatment for the crystallization has to be in an order of ppm, or preferably, less than 1 ppm.
[0066] Inert gases such as argon, beside nitrogen, or their mixed gas may be used as the gas which occupies the most of the atmosphere for implementing the heat treatment for the. crystallization.
[0067] The lower limit of the heating temperature for the crystallization is preferred to be 450° C. or more from the aspects of its effectiveness and reproducibility. On the other hand, the upper limit thereof is preferred to be less than the distortion point of the used glass substrate. Because the Coning 1737 glass substrate whose distortion point is 667° C. is used here, its upper limit is set at 650° C., leaving some margin.
[0068] In this regard, the heating temperature may be increased up to around 900° C. if a quartz substrate is used as the substrate. In this case, a crystal silicon film having a higher crystalinity may be obtained in a shorter time.
[0069] Thus, the crystal silicon film 105 is obtained as shown in FIG. 1C.
[0070] Another heat treatment is implemented after obtaining the crystal silicon film 105 to form a thermal oxide film containing halogen element. Then, this heat treatment is implemented within an atmosphere containing halogen element (FIG. 1D).
[0071] This step is carried out to eliminate the nickel element which has been introduced intentionally for the crystallization in the initial stage from the crystal silicon film 105. This heat treatment is implemented at a temperature higher than that of the heat treatment implemented for the crystallization described above. It is an important condition for effectively implementing the gettering of nickel element.
[0072] This heat treatment is implemented in the temperature range from 550° C. to 1050° C. or preferably from 600° C. to 980° C. upon meeting the above-mentioned condition.
[0073] It is because no effect is obtained if the temperature is below 600° C., and a fixture formed by quartz distorts or a burden is placed upon equipments if it exceeds 1050° C. (in this sense, it is preferable to be less than 980° C.
[0074] Further, the upper limit of the heating temperature is limited by the distortion point of the glass substrate to be used. It must be careful not to implement the heat treatment in a temperature above the distortion point of the glass substrate to be used because, otherwise, it is deformed.
[0075] Because the Coning 1737 glass substrate whose distortion point is 667° C. is used here, the heating temperature is set at 650° C. The second heat treatment is implemented in an atmosphere in which 5 volume % of HCl is included in oxygen.
[0076] It is preferable to mix HCl with a ratio of 0.5% to 10% (volume %) to oxygen. It must be careful not to mix above this concentration because, otherwise, the surface of the film becomes rough with the same or more degree of irregularity with the thickness of the film.
[0077] A thermal oxide film 106 containing chlorine as shown in FIG. 1D is formed by implementing the heat treatment under such condition. Here, the thermal oxide film 106 is formed in a thickness of 200 angstrom by implementing the heat treatment for 12 hours.
[0078] Because the thermal oxide film 106 is formed, the thickness of the crystal silicon film 106 reaches to about 1500 angstrom.
[0079] When the heating temperature is 600° C. to 750° C. in this heat treatment, the treatment time (heating time) is set at 10 hours to 48 hours or typically at 24 hours.
[0080] It is noted that if the heating temperature is 750° C. to 900° C., the treatment time is set at 5 hours to 24 hours or typically at 12 hours.
[0081] Further, when the heating temperature is 900° C. to 1050° C., the treatment time is set at 1 hour to 12 hours or typically at 6 hours.
[0082] These treatment times are set adequately depending on the thickness of the oxide film to be obtained as a matter of course.
[0083] In this step, nickel element is gettered out of the silicon film by the action of the halogen element. Here, the nickel element is gettered to the thermal oxide film 106 thus formed by the action of chlorine.
[0084] In the gettering, oxygen existing within the crystal silicon film plays an important role. That is, the gettering of nickel element proceeds effectively because the gettering effect caused by chlorine acts on nickel oxide formed when oxygen couples with nickel.
[0085] If the concentration of oxygen is too much, it becomes the factor of hampering the crystallization of the amorphous silicon film 103 in the crystallization step shown in FIG. 1C as described above. However, the existence thereof plays an important role in the process of gettering nickel as described above. Accordingly, it is important to control the concentration of oxygen existing within the amorphous silicon film, the starting film.
[0086] Here, Cl has been selected as the halogen element and the case of using HCl has been shown as a method for introducing it. Beside HCl, one type or a plurality of types of mixed gas selected from HF, HBr, Cl2, F2, Br2may be used. Beside them, halogen hydroxide may be used in general.
[0087] It is preferable to set the content (volume content) of those gases within the atmosphere to 0.25 to 5% if it is RF, 1 to 15% if it is HBr, 0.25 to 5% if it is Cl2, 0.125 to 2.5% if it is F2and 0.5 to 10% if it is Br2.
[0088] If the concentration is below the above-mentioned range, no significant effect is obtained. Further, if the concentration exceeds the upper limit of the above-mentioned range, the surface of the crystal silicon film is roughened.
[0089] Through this step, the concentration of nickel element may be reduced to less than 1/10 in maximum from the initial stage. It means that the nickel element may be reduced to 1/10 as compared to the case when no gettering is conducted by the halogen element. This effect may be obtained in the same manner even when another metal element is used.
[0090] Because the nickel element is gettered to the oxide film to be formed in the above-mentioned step, naturally the nickel concentration within the oxide film becomes high as compared to other domains.
[0091] Further, it has been observed that the concentration of nickel element is apt to be high near the interface of the crystal silicon film 105 with the oxide film 106. It is considered to happen because the domain where the gettering mainly takes place is on the side of the oxide film near the interface between the silicon film and the oxide film. The gettering proceeding near the interface is considered to be caused by the existence of stress and defects near the interface.
[0092] Then, the thermal oxide film 106 containing nickel in high concentration. is eliminated. The thermal oxide film 106 may be eliminated by means of wet etching or dry etching using buffer hydrofluoric acid (or other hydrofluorite etchant).
[0093] Thus, a crystal silicon film 107 in which the concentration of nickel has been reduced is obtained as shown in FIG. 1E.
[0094] Because nickel element is contained near the surface of the obtained crystal silicon film 107 relatively in high concentration, it is effective to advance the above-mentioned etching to over-etch, more or less, the surface of the crystal silicon film 107.
[0095] Second Embodiment
[0096] The present embodiment relates to a case when laser light is irradiated after obtaining the crystal silicon film by the heat treatment shown in FIG. 1B in the arrangement shown in the first embodiment to promote the crystallization thereof.
[0097] When the temperature of the heat treatment shown in FIG. 1B is low or when the treatment time is short, i.e. when the heating temperature or the heating time is restricted by the reason of the fabrication process, there is a possibility that the required crystalinity cannot not be obtained. In such a case, the required high crystalinity may be obtained by implementing annealing by irradiating laser light.
[0098] The width of the permissible laser irradiation condition of the irradiation of laser this time is wide as compared to the case when the amorphous silicon film is directly crystallized. Further, its high reproduciblity may be enhanced.
[0099] The irradiation of laser light is implemented after the step shown in FIG. 1C. It is also important to form the amorphous silicon film 103 which is formed in FIG. 1A as the starting film in a thickness of 200 to 2000 angstrom. It is because the annealing effect exerted by the irradiation of laser light becomes high when the thickness of the amorphous silicon film is thin.
[0100] It is preferable to use excimer laser in the ultraviolet region as the laser light to be used. In concrete, KrF excimer laser (wavelength: 248 nm), XeCl excimer laser (wavelength: 308 nm) and the like may be used. Beside laser light, the annealing may be implemented by irradiating intense light by using an ultraviolet lamp.
[0101] Third Embodiment
[0102] The present embodiment relates to a case when an infrared lamp is used instead of the laser light in the second embodiment. The use of infrared ray allows the silicon film to be heated selectively without heating the glass substrate so much. Accordingly, an effective heat treatment may be implemented without giving thermal damage to the glass substrate.
[0103] Fourth Embodiment
[0104] The present embodiment relates to a case when Cu is used as the metal element which promotes the crystallization of silicon in the arrangement shown in the first embodiment. In this case, cupric acetate [Cu(CH3COO)2] or cupricchloride (CuCl22H2O) may be used as the solution for introducing Cu.
[0105] Fifth Embodiment
[0106] The present embodiment relates to a case when a quartz substrate is used as the substrate 101 in the arrangement shown in the first embodiment. In the present embodiment, the amorphous silicon film 103, i.e. the starting film, is formed in a thickness of 2000 angstrom. Further, the heating temperature in forming the thermal oxide film in the heat treatment shown in FIG. 1C is set at 950° C.
[0107] In this case, the oxide film is formed quickly and the gettering effect cannot be fully obtained, so that the concentration of oxygen within the atmosphere is lowered. In concrete, the oxygen concentration within the nitrogen atmosphere is set at 10%. Further, the heat treatment is implemented in the atmosphere in which the concentration of HCl (volume concentration) to oxygen is set at 3%.
[0108] In this case, the treatment time is set at 300 minutes. Under such conditions, the thermal oxide film having about 500 angstrom of thickness may be obtained. In the same time, the time necessary for gettering may be earned.
[0109] It is noted that if the heat treatment is implemented at 950° C. within the atmosphere of 97% of oxygen and 3% of HCl, a thermal oxide film having a thickness of 500 angstrom is obtained in about 30 minutes. In this case, nickel cannot be fully gettered, so that nickel element remains relatively in high concentration within the crystal silicon film 107.
[0110] Accordingly, it is preferable to form the thermal oxide film by adjusting the oxygen concentration as described in the present embodiment to earn an enough time to obtain the gettering effect.
[0111] The utilization of this method allows the time necessary for the gettering to be set by adjusting the oxygen concentration in the atmosphere when the thickness and forming temperature of the thermal oxide film are changed.
[0112] Sixth Embodiment
[0113] The present embodiment relates to a case of growing crystal in the form different from that in the first embodiment. That is, the present embodiment relates to a method of growing the crystal in a direction parallel to the substrate, i.e. a method called lateral growth, by utilizing the metal element which promotes crystallization of silicon.
[0114] FIG. 2 shows the fabrication process according to the present embodiment. At first, a silicon oxide nitride film is formed as an underlying film 202 in a thickness of 3000 angstrom on the Coning 1737 glass substrate (or a quartz substrate) 201.
[0115] Next, an amorphous silicon film 203 which is the starting film of a crystal silicon film is formed in a thickness of 2000 angstrom by reduced pressure thermal CVD. The thickness of the amorphous silicon film is preferable to be less than 2000 angstrom as described before.
[0116] It is noted that plasma CVD may be used instead of the reduced pressure thermal CVD.
[0117] Next, a silicon oxide film not shown is formed in a thickness of 1500 angstrom and is patterned to form a mask 204. An opening is created on the mask in a domain 205. The amorphous silicon film 203 is exposed at the domain where the opening 205 is created.
[0118] The opening 205 has a thin and long rectangular shape in the longitudinal direction from the depth to the front side of the figure. Preferably, the width of the opening 203 is 20 μm or more. The length thereof in the longitudinal direction may be determined arbitrarily.
[0119] Then, the nickel acetate aqueous solution containing 10 ppm of nickel element in terms of weight is applied in the same manner with the first embodiment and the extra solution is removed by implementing spin drying by using a spinner not shown.
[0120] Thus, the solution is held in contact on the exposed surface of the amorphous silicon film 203 as indicated by a dot line 206 in FIG. 2A.
[0121] Next, a heat treatment is implemented at 640° C. for four hours in a nitrogen atmosphere containing 3% of hydrogen and in which oxygen is minimized. Then, crystal grows in the direction parallel to the substrate as indicated by the reference numeral 207 in FIG. 2B. This crystal growth advances from the domain of the opening 205 to which nickel element has been introduced to the surrounding part. This crystal growth in the direction parallel to the substrate will be referred to as lateral growth.
[0122] It is possible to advance this lateral growth across more than 100 μm under the conditions shown in the present embodiment. Then, a crystal silicon film 208 having the domain in which the crystal has thus grown laterally is obtained. It is noted that crystal growth in the vertical direction called vertical growth advances from the surface of the silicon film to the underlying interface in the domain where the opening 205 is formed.
[0123] Then, the mask 204 made of the silicon oxide film for selectively introducing nickel element is eliminated. Thus, the state shown in FIG. 2C is obtained. In this state, the vertically grown domain, the laterally grown domain and a domain in which no crystal has grown (having amorphous state) exist within the silicon film 208.
[0124] In this state, a heat treatment is implemented at 650° C. for 12 hours within an oxygen atmosphere containing 3% of HCl. In this step, an oxide film 209 containing nickel element in high concentration is formed. In the same time, the concentration of nickel element within the silicon film 208 may be reduced relatively.
[0125] Here, the thermal oxide film 209 is formed in a thickness of 200 angstrom. The thermal oxide film contains the nickel element gettered by the action of chlorine in high concentration. Further, because the thermal oxide film 209 is formed, the thickness of the crystal silicon film 208 is reduced to about 1900 angstrom.
[0126] Next, the thermal oxide film 209 containing nickel element in high concentration is eliminated.
[0127] In the crystal silicon film of this state, the nickel element has a distribution of concentration such that it exists in high concentration toward the surface of the crystal silicon film.
[0128] Accordingly, it is useful to etch the surface of the crystal silicon film to eliminate the domain in which the nickel element exists in high concentration after eliminating the thermal oxide film 209. That is, the crystal silicon film in which the nickel element concentration is reduced further may be obtained by etching the surface of the crystal silicon film in which the nickel element exists in high concentration.
[0129] Next, patterning is implemented to form a pattern 210 formed of the laterally grown domain. Here, it is important to form the pattern 210 such that no vertically grown domain, amorphous domain nor an edge portion of the laterally grown domain is included there.
[0130] It is because the concentration of nickel element is relatively high in the edge portion of the vertically and laterally grown domains and the amorphous domain has inferior electrical characteristics.
[0131] The concentration of nickel element which remains within the pattern 210 made of the laterally grown domain thus obtained may be reduced further as compared to the case shown in the first embodiment.
[0132] This is caused by the fact that the concentration of the metal element contained within the laterally grown domain is low originally. In concrete, the concentration of nickel element within the pattern 209 made of the laterally grown domain may be readily reduced to the order of 1017cm−3or less.
[0133] When a thin film transistor is formed by utilizing the laterally grown domain, a semiconductor device having a higher mobility may be obtained as compared to the case when the vertically grown domain as shown in the first embodiment (crystal grows vertically on the whole surface in the case of the first embodiment) is utilized.
[0134] It is noted that it is useful to implement the etching process further after forming the pattern shown in FIG. 2E to eliminate the nickel element existing on the surface of the pattern.
[0135] However, it is not useful to implement thermal oxidation within the oxidizing atmosphere containing halogen element after patterning the crystal silicon film in a shape of island and then to eliminate the thermal oxide film.
[0136] It is because in this arrangement, the etching advances so as to scoop out even the under side of the crystal silicon film formed in an island shape because the etching of the underlying film advances when the thermal oxide film is eliminated, though the gettering effect is certainly obtained by the thermal oxide film. Such condition may cause breaking of wires and defective operation of elements later.
[0137] Then, a thermal oxide film 210 is formed after thus forming the pattern 210. This thermal oxide film becomes a part of a gate insulating film later when a thin film transistor is constructed.
[0138] Seventh Embodiment
[0139] The present embodiment relates to a case of fabricating a thin film transistor disposed in a pixel domain of an active matrix type liquid crystal display or an active matrix type EL display by utilizing the invention disclosed in the present specification.
[0140] FIG. 3 shows the fabrication process according to the present embodiment. At first, the crystal silicon film is formed on the glass substrate through the process shown in the first or the sixth embodiment. When the crystal silicon film is obtained by the arrangement shown in the first embodiment, it is patterned to obtain the state shown in FIG. 3A.
[0141] In FIG. 3A, the reference numeral 301 denotes a glass substrate, 302 an underlying film, and 303 an active layer formed of the crystal silicon film. After obtaining the state shown in FIG. 3A, a plasma treatment is implemented within a reduced pressure atmosphere in which oxygen and hydrogen are mixed. The plasma is generated by high-frequency discharge.
[0142] Organic substances existing on the surface of the exposed active layer 105 may be removed by the above-mentioned plasma treatment. Specifically, the organic substances adsorbing on the surface of the active layer are oxidized by oxygen plasma and the oxidized organic substances are reduced and vaporized further by hydrogen plasma. Thus the organic substances existing on the surface of the exposed active layer 303 are removed.
[0143] The removal of the organic substances is very effective in suppressing fixed charge from existing on the surface of the active layer 303. Because the fixed charge caused by the existence of organic substances hampers the operation of the device and renders the characteristics thereof instable, it is very useful to reduce it.
[0144] After removing the organic substances, thermal oxidation is implemented within an oxygen atmosphere at 640° C. to form a thermal oxide film 300 of 100 angstrom thick. This thermal oxide film has a high interfacial characteristic with a semiconductor layer and composes a part of a gate insulating film later. Thus, the state shown in FIG. 3A is obtained.
[0145] After obtaining the state shown in FIG. 3A, a silicon oxide nitride film 304 which composes the gate insulating film is formed in a thickness of 1000 angstrom. The film may be formed by using plasma CVD using mixed gas of sillane and N2O or plasma CVD using mixed gas of TEOS and N2O.
[0146] The silicon oxide nitride film 304 functions as the gate insulating film. together with the thermal oxide film 300.
[0147] It is also effective to contain halogen element within the silicon oxide nitride film. That is, it is possible to prevent the function of the gate insulating film as an insulating film from dropping by the influence of the nickel element (or another metal element which promotes crystallization of silicon) existing within the active layer by fixing the nickel element by the action of the halogen element.
[0148] It is significant to use the silicon oxide nitride film in that metal element hardly infiltrates to the gate insulating film from its dense film quality. If metal element infiltrates into the gate insulating film, its function as an insulating film drops, thus causing instability and dispersion of characteristics of the thin film transistor.
[0149] It is noted that a silicon oxide film which is normally used may be also used for the gate insulating film.
[0150] After forming the silicon oxide nitride film 304 which functions as the gate insulating film, an aluminum film not shown which functions as a gate electrode later is formed by sputtering. 0.2 weight % of scandium is included within the aluminum film.
[0151] Scandium is included in the aluminum film to suppress hillock and whisker from being produced in the later process. The hillock and whisker mean that abnormal growth of aluminum occurs by heating, thus forming needle or prickle-like projections.
[0152] After forming the aluminum film, a dense anodic oxide film not shown is formed. The anodic oxide film is formed by using ethylene glycol solution containing 3 weight % of tartaric acid as electrolyte. That is, the anodic oxide film having the dense film quality is formed on the surface of the aluminum film by setting the aluminum film as the anode and platinum as the cathode and by anodizing within this electrolyte.
[0153] The thickness of the anodic oxide film not shown having the dense film quality is around 100 angstrom. This anodic oxide film plays a role of enhancing the adhesiveness with a resist mask to be formed later.
[0154] It is noted that the thickness of the anodic oxide film may be controlled by adjusting voltage applied during the anodization.
[0155] Next, the resist mask 306 is formed and the aluminum film is patterned so as to have a pattern 305. The state shown in FIG. 3B is thus obtained.
[0156] Here, another anodization is implemented. In this case, 3 weight % of oxalate aqueous solution is used as electrolyte. A porous anodic oxide film 308 is formed by anodizing within this electrolyte by setting the aluminum pattern 305 as the anode.
[0157] In this step, the anodic oxide film 308 is formed selectively on the sides of the aluminum pattern because the resist mask 306 having the high adhesiveness exists thereabove.
[0158] The anodic oxide film may be grown up to several μm thick. The thickness is 6000 angstrom here. It is noted that the range of the growth may be controlled by adjusting an anodizing time.
[0159] Next, the resist mask 306 is removed. Then, a dense anodic oxide film is formed again. That is, the anodization is implemented again by using the ethylene glycol solution containing 3% of tartaric acid as electrolyte. Then, an anodic oxide film 309 having a dense film quality is formed because the electrolyte infiltrates into the porous anodic oxide film 308.
[0160] This dense anodic oxide film 309 is 1000 angstrom thick. The thickness is controlled by adjusting applied voltage.
[0161] Here, the exposed silicon oxide nitride film 304 and the thermal oxide film 300 are etched by utilizing dry etching. Then, the porous anodic oxide film 308 is eliminated by using mixed acid in which acetic acid, nitric acid and phosphoric acid are mixed. Thus, the state shown in FIG. 3D is obtained.
[0162] After obtaining the state shown in FIG. 3D, impurity ions are injected. Here, P (phosphorus) ions are injected by plasma doping in order to fabricate an N-channel type thin film transistor.
[0163] In this step, heavily doped domains 311 and 315 and lightly doped domains 312 and 314 are formed because part of the remaining silicon oxide film 310 functions as a semi-permeable mask, thus blocking part of the injected ions.
[0164] Then, laser light or intense light is irradiated to activate the domains into which the impurity ions have been injected. Thus, a source domain 311, a channel forming domain 313, a drain domain 315 and low concentrate impurity domains 312 and 314 are formed in a manner of self-adjustment.
[0165] The one designated by the reference numeral 314 here is the domain called the LDD (lightly doped domain) (FIG. 3D).
[0166] It is noted that when the dense anodic oxide film 309 is formed as thick as 2000 angstrom or more, an offset gate domain may be formed on the outside of the channel forming domain 313 by its thickness.
[0167] Although the offset gate domain is formed also in the present embodiment, it is not shown in the figures because its size is small, its contribution due to the existence thereof is small and the figures might otherwise become complicated.
[0168] Next, a silicon oxide film or a silicon nitride film or their laminated film is formed as an interlayer insulating film 316. The interlayer insulating film may be constructed by forming a layer made of a resin material on the silicon oxide film or the silicon nitride film.
[0169] Then, contact holes are created to form a source electrode 317 and a drain electrode 318. Thus, the thin film transistor shown in FIG. 3E is completed.
[0170] Eighth Embodiment
[0171] The present embodiment is related to a method for forming the gate insulating film 304 in the arrangement shown in the seventh embodiment. Thermal oxidation may be used as a method for forming the gate insulating film when a quartz substrate or a glass substrate having a high heat resistance is used as the substrate.
[0172] The thermal oxidation allows the film quality to be densified and is useful in obtaining a thin film transistor having stable characteristics.
[0173] That is, because an oxide film formed by the thermal oxidation is dense as an insulating film and movable electric charge existing therein can be reduced, it is one of the most suitable films as a gate insulating film.
[0174] A heat treatment is implemented for example in an oxidizing atmosphere at 950° C. in forming the thermal oxide film.
[0175] At this time, it is effective to mix HCl or the like into the oxidizing atmosphere because, thereby, metal element existing in the active layer may be fixed in the same time with the formation of the thermal oxide film.
[0176] It is also effective to mix N2O gas into the oxidizing atmosphere to form a thermal oxide film containing nitrogen component. Here, it is also possible to obtain a silicon oxide nitride film by the thermal oxidation if the mixed ratio of N2O gas is optimized.
[0177] It is noted that the thermal oxide film 300 needs not be formed in the present embodiment.
[0178] Eighth Embodiment
[0179] The present embodiment relates to a case of fabricating a thin film transistor through a process different from that shown in FIG. 3.
[0180] FIG. 4 shows the fabrication process according to the present embodiment. At first, the crystal silicon film is formed on the glass substrate through the process shown in the first or second embodiment. It is then patterned, thus obtaining the state shown in FIG. 4A.
[0181] After obtaining the state shown in FIG. 4A, a plasma treatment is implemented within a reduced pressure atmosphere in which oxygen and hydrogen are mixed.
[0182] In the state shown in FIG. 4A, the reference numeral 401 denotes a glass substrate, 402 an underlying film, 403 an active layer formed of the crystal silicon film and 400 a thermal oxide film formed again after eliminating the thermal oxide film for gettering.
[0183] After obtaining the state shown in FIG. 4A, a silicon oxide nitride film 404 which composes a gate insulating film is formed in a thickness of 1000 angstrom. The film may be formed by using plasma CVD using mixed gas of oxygen, sillane and N2O or plasma CVD using mixed gas of TEOS and N2O.
[0184] The silicon oxide nitride film 404 composes the gate insulating film together with the thermal oxide film 400. It is noted that a silicon oxide film may be used beside the silicon oxide nitride film.
[0185] After forming the silicon oxide nitride film 404 which functions as the gate insulating film, an aluminum film not shown which functions as a gate electrode later is formed by sputtering. 0.2 weight % of scandium is included within the aluminum film.
[0186] After forming the aluminum film, a dense anodic oxide film not shown is formed. The anodic oxide film is formed by using ethylene glycol solution containing 3% of tartaric acid as electrolyte. That is, the anodic oxide film having the dense film quality is formed on the surface of the aluminum film by setting the aluminum film as the anode and platinum as the cathode and by anodizing within this electrolyte.
[0187] The thickness of the anodic oxide film not shown having the dense film quality is around 100 angstrom. This anodic oxide film plays a role of enhancing the adhesiveness with a resist mask to be formed later.
[0188] It is noted that the thickness of the anodic oxide film may be controlled by adjusting voltage applied during the anodization.
[0189] Next, the resist mask 405 is formed and the aluminum film is patterned so as to have a pattern 406.
[0190] Here, another anodization is implemented. In this case, 3% of oxalate aqueous solution is used as electrolyte. A porous anodic oxide film 407 is formed by anodizing within this electrolyte by setting the aluminum pattern 406 as the anode.
[0191] In this step, the anodic oxide film 407 is formed selectively on the sides of the aluminum pattern because the resist mask 405 having the high adhesiveness exists thereabove.
[0192] The anodic oxide film may be grown up to several μm thick. The thickness is 6000 angstrom here. It is noted that the range of the growth may be controlled by adjusting an anodizing time.
[0193] Then, after removing the resist mask 405, another dense anodic oxide film is formed. That is, the anodization is implemented again by using the ethylene glycol solution containing 3% of tartaric acid as electrolyte. Then, an anodic oxide film 408 having a dense film quality is formed because the electrolyte infiltrates into the porous anodic oxide film 407.
[0194] Here, the initial injection of impurity ions is implemented. It is noted that this step may be implemented after removing the resist mask 405.
[0195] A source domain 409 and a drain domain 411 are formed by injecting the impurity ions. No impurity ion is injected to a domain 410.
[0196] Then, the porous anodic oxide film 307 is eliminated by using mixed acid in which acetic acid, nitric acid and phosphoric acid are mixed. Thus, the state shown in FIG. 4D is obtained.
[0197] After obtaining the state shown in FIG. 4D, impurity ions are injected again. The impurity ions are injected under the doping condition lighter than that of the first injection.
[0198] In this step, lightly doped domains 412 and 413 are formed and a domain 414 turns out to be a channel forming domain (FIG. 4D).
[0199] Then, laser light or intense light is irradiated to activate the domains into which the impurity ions have been injected. Thus, the source domain 409, the channel forming domain 414, the drain domain 411 and low concentrate impurity domains 412 and 413 are formed in a manner of self-adjustment.
[0200] Here, the one designated by the reference numeral 413 is the domain called the LDD (lightly doped domain) (FIG. 4D).
[0201] Next, a silicon oxide film or a silicon nitride film or their laminated film is formed as an interlayer insulating film 414. The interlayer insulating film may be constructed by forming a layer made from a resin material on the silicon oxide film or the silicon nitride film.
[0202] After that, contact holes are created to form a source electrode 416 and a drain electrode 417. Thus, the thin film transistor shown in FIG. 4E is completed.
[0203] Ninth Embodiment
[0204] The present embodiment relates to a case when an N-channel type thin film transistor and a P-channel type thin film transistor are formed in a complementary manner.
[0205] The arrangement shown in the present embodiment may be utilized for various thin film integrated circuits integrated on an insulated surface as well as for peripheral driving circuits of an active matrix type liquid crystal display for example.
[0206] At first, a silicon oxide film or a silicon oxide nitride film is formed as an underlying film 502 on a glass substrate 501 as shown in FIG. 5A. It is preferable to use the silicon oxide nitride film.
[0207] Next, an amorphous silicon film not shown is formed by the plasma CVD or reduced pressure thermal CVD. Then; the amorphous silicon film is transformed into a crystal silicon film by the same method as shown in the first embodiment.
[0208] Next, a plasma treatment is implemented within an atmosphere in which oxygen and hydrogen are mixed. Then, the obtained crystal silicon film is patterned to obtain active layers 503 and 504. Thus, the state shown in FIG. 5A is obtained.
[0209] It is noted that a heat treatment is implemented at 650° C. for 10 hours within a nitrogen atmosphere containing 3% of HCl in the state shown in FIG. 5A in order to suppress the influence of carriers moving the sides of the active layers.
[0210] Because an OFF current characteristic becomes bad if a trap level exists due to the existence of metal element on the sides of the active layers, it is effective to implement the above-mentioned treatment to lower the level on the sides of the active layers.
[0211] Further, a thermal oxide film 500 and a silicon oxide nitride film 505 which compose a gate insulating film are formed. When quartz is used as the substrate here, it is desirable to compose the gate insulating film only by the thermal oxide film formed by using the above-mentioned thermal oxidation.
[0212] Next, an aluminum film not shown which composes a gate electrode later is formed in a thickness of 4000 angstrom. Beside the aluminum film, a metal which can be anodized (e.g. tantalum) may be used.
[0213] After forming the aluminum film, a very thin and dense anodic oxide film is formed on the surface thereof by the method described before.
[0214] Next, a resist mask not shown is placed on the aluminum film to pattern the aluminum film. Then, anodization is implemented by setting the obtained aluminum pattern as the anode to form porous anodic oxide films 508 and 509. The thickness of the porous anodic oxide films is 5000 angstrom for example.
[0215] Then, another anodization is implemented under the condition of forming dense anodic oxide films to form dense anodic films 510 and 511. The thickness of the dense anodic oxide films 510 and 511 is 800 angstrom. Thus, the state shown in FIG. 5B is obtained.
[0216] Then, the exposed silicon oxide film 505 and the thermal oxide film 500 are eliminated by dry etching, thus obtaining the state shown in FIG. 5C.
[0217] After obtaining the state shown in FIG. 5C, the porous anodic oxide films 508 and 509 are eliminated by using mixed acid in which acetic acid, nitric acid and phosphoric acid are mixed. Thus, the state shown in FIG. 5D is obtained.
[0218] Here, resist masks are disposed alternately to inject P (phosphorus) ions to the thin film transistor on the left side and B (boron) ions to the thin film transistor on the right side.
[0219] By injecting those impurity ions, a source domain 514 and a drain domain 517 having N-type in high concentration are formed in a manner of self-adjustment.
[0220] Further, a domain 515 to which P ions are doped in low concentration, thus having weak N-type, as well as a channel forming domain 516 are formed in the same time.
[0221] The reason why the domain 515 having the weak N-type is formed is because the remaining gate insulating film 512 exists. That is, part of P ions transmitting through the gate insulating film 512 is blocked by the gate insulating film 512.
[0222] By the same principle, a source domain 521 and a drain domain 518 having strong P-type are formed in a manner of self-adjustment and a low concentrate impurity domain 520 is formed in the same time. Further, a channel forming domain 519 is formed in the same time.
[0223] It is noted that when the thickness of the dense anodic oxide films 510 and 511 is as thick as 2000 angstrom, an offset gate domain may be formed in contact with the channel forming domain by that thickness.
[0224] Its existence may be ignored in the case of the present embodiment because the dense anodic oxide films 510 and 511 are so thin as less than 1000 angstrom.
[0225] Then, laser light or intense light is irradiated to anneal the domain into which the impurity ions have been injected.
[0226] Then, a silicon nitride film 522 and a silicon oxide film 523 are formed as interlayer insulating films as shown in FIG. 5E. Their thickness is 1000 angstrom, respectively. It is noted that the silicon oxide film 523 needs not be formed.
[0227] Here, the thin film transistor is covered by the silicon nitride film. The reliability of the thin film transistor may be enhanced by arranging as described above because the silicon nitride film is dense and has a favorite interfacial characteristic.
[0228] Further, an interlayer insulating film 524 made of a resin material is formed by means of spin coating. Here, the thickness of the interlayer insulating film 524 is 1 μm FIG. 5E).
[0229] Then, contact holes are created to form a source electrode 525 and a drain electrode 526 of the N-channel type thin film transistor on the left side. In the same time, a source electrode 527 and the drain electrode 526 of the thin film transistor on the right side are formed. Here, the electrode 526 is disposed in common.
[0230] Thus, the thin film transistor circuit having a CMOS structure constructed in a complementary manner may be formed.
[0231] According to the arrangement shown in the present embodiment, the thin film transistor is covered by the nitride film as well as the resin material. This arrangement allows to enhance the durability of the thin film transistor to which movable ions nor moisture hardly infiltrate.
[0232] Further, it allows to prevent capacitance from being generated between the thin film transistor and wires when a multi-layered wire is formed.
[0233] Tenth Embodiment
[0234] The present embodiment relates to a case of forming a mono-crystal domain or a domain which can be substantially considered as a mono-crystal domain by irradiating laser light to the crystal silicon film obtained in the first or second embodiment.
[0235] At first, the crystal silicon film is obtained by utilizing the action of nickel element as shown in the first embodiment. Next, excimer laser (e.g. KrF excimer laser) is irradiated to the film to promote crystallization thereof further. At this time, the mono-crystal domain or the domain which can be substantially considered as a mono-crystal domain may be formed by using a heat treatment in the temperature range of more than 450° C., and by optimizing the condition for irradiating the laser light.
[0236] The film whose crystallization has been greatly promoted by such method has a domain which can be considered as a mono-crystal in which an electron spin density measured by ESR is less than 3×1017cm−3and the concentration of nickel element as the minimum value measured by SIMS is less than 3×1017cm−3.
[0237] Substantially no grain boundary exists in this domain and high electrical characteristics equivalent to a mono-crystal silicon wafer can be obtained.
[0238] Further, the domain which can be considered as a mono-crystal contains hydrogen by less than 5 atom % to 1×1015cm−3. This value is clarified by the measurement carried out by the SIMS (secondary ion mass spectrometry).
[0239] By fabricating a thin film transistor by utilizing such mono-crystal or the domain which can be substantially considered as a mono-crystal, a semiconductor device which is equivalent to a MOS type transistor fabricated by using a mono-crystal wafer may be obtained.
[0240] Eleventh Embodiment
[0241] The present embodiment relates to a case when nickel element is introduced directly to the surface of the underlying film in the process shown in the first embodiment. In this case, the nickel element is held in contact with the lower surface of the amorphous silicon film.
[0242] In this case, nickel element is introduced after forming the underlying film such that the nickel element (metal element) is held in contact with the surface of the underlying film. Beside the method of using the solution, sputtering, CVD or adsorption may be used as the method for introducing nickel element.
[0243] Twelfth Embodiment
[0244] In the present embodiment, the effect of gettering nickel, by the action of chlorine, from the crystal silicon film which has been crystallized by the action of nickel based on experimental data.
[0245] FIG. 6 shows a measured result of the distribution of concentration of nickel element in a direction of section of the crystal silicon film obtained by utilizing nickel. The measurements were obtained by SIMS (secondary ion mass spectrometry).
[0246] It is noted that the measured data around the surface is not significant because it is influenced by the irregularity and adsorbed substances on the surface. The data around the interface also contains errors more or less by the same reason.
[0247] Steps for fabricating the sample from which these measured values have been obtained will be explained below briefly. An silicon oxide film is formed as an underlying film in a thickness of 4000 angstrom on a quartz substrate and then an amorphous silicon film is formed in a thickness of 500 angstrom by reduced pressure thermal CVD.
[0248] Next, nickel element is introduced to the amorphous silicon film by the method using nickel acetate aqueous solution as shown in the first embodiment. Further, the amorphous silicon film is crystallized by a heat treatment at 650° C. for four hours to obtain a crystal silicon film.
[0249] Then, another heat treatment is implemented within an oxidizing atmosphere at 950° C. to form a thermal oxide film 500 angstrom thick.
[0250] As it is apparent from FIG. 6, the nickel element exists within the crystal silicon film (poly-Si film) in high concentration (as compared to other domains). It is noted that the reason why the concentration of nickel element is high on the surface of the thermal oxide film is considered to be measurement errors caused by the state of the surface, so that it is not significant.
[0251] Next, FIG. 7 shows measured data of a sample of another method for forming the thermal oxide film implemented within an oxygen atmosphere containing 3% of HCl at 950° C.
[0252] As it is apparent from FIG. 7, the concentration of nickel within the crystal silicon film (poly-Si) is reduced and instead of that, the concentration of nickel within the thermal oxide film is increased. This means that the nickel element has been suctioned out (i.e. gettered) to the thermal oxide film.
[0253] The difference between FIG. 6 and FIG. 7 is only whether HCl has been contained within the atmosphere in forming the thermal oxide film. Accordingly, it can be concluded that the above-mentioned effect of gettering is brought about by HCl. Further, because no gettering effect is confirmed by H, it can be concluded that, more accurately, the gettering effect as indicated by the difference between FIG. 6 and FIG. 7 can be obtained by the action of Cl (chlorine).
[0254] Further, it can be seen that the crystal silicon film in which the nickel concentration has been reduced can be obtained by eliminating the thermal oxide film which has gettered the nickel element.
[0255] FIG. 8 shows the distribution of concentration of Cl element in a sample fabricated under the same condition with that of the sample from which the data in FIG. 7 has been obtained. As it is apparent from FIG. 8, the Cl element is concentrated near the interface between the crystal silicon film and the thermal oxide film.
[0256] Thirteenth Embodiment
[0257] The present embodiment is related to a case when an amorphous silicon film formed by plasma CVD is utilized as the starting film of the crystal silicon film from which the data described in the twelfth embodiment has been obtained. Because the quality of the amorphous silicon film formed by the plasma CVD is different from that of the amorphous silicon film formed by the reduced pressure thermal CVD, the action of gettering is also different as described later.
[0258] FIG. 9 shows data for comparison. FIG. 9 shows measured data of a sample when the thermal oxide film has been formed in an oxygen atmosphere at 950° C. As it is apparent from FIG. 9, the nickel element exists relatively in high concentration within the crystal silicon film (poly-Si).
[0259] It is noted that although the condition for introducing nickel is the same, the nickel concentration is high within the crystal silicon film (poly-Si) as compared to that in FIG. 6. It is assumed to have happened because the nickel element can readily diffuse within the film because the quality of the amorphous silicon film formed by the plasma CVD is not dense and has many defects.
[0260] The above-mentioned fact may be seen from another point of view as follows. That is, while a very thin oxide film has been formed on the surface of the amorphous silicon film by means of UV oxidation before applying the nickel acetate aqueous solution, there is a possibility that the thickness of the oxide film have become different by receiving an influence of difference of the quality of the underlying amorphous silicon film. It can be understood that because the amount-of nickel element which diffuses within the silicon film is different depending on the difference of the thickness in this case, its effect has appeared as the difference between FIG. 6 and FIG. 9.
[0261] FIG. 10 shows data when 1% of HCl is contained in oxygen as the atmosphere in forming the thermal oxide film. As it is apparent from FIG. 10, the nickel concentration within the crystal silicon film (Poly-Si) drops further as compared to the data shown in FIG. 9. In contrary to that, the nickel concentration within the thermal oxide film has increased.
[0262] This fact means that the nickel element has been gettered to the thermal oxide film by the action of chlorine. Thus, the nickel element existing within the silicon film may be gettered effectively to the thermal oxide film by forming the thermal oxide film within the oxidizing atmosphere containing chlorine.
[0263] Accordingly, the crystal silicon film in which the nickel concentration is reduced may be obtained by eliminating the thermal oxide film which has gettered the nickel element.
[0264] FIG. 11 shows a result obtained by studying the concentration of chlorine within a sample obtained under the same fabrication condition with that of the sample from which the data shown in FIG. 10 has been obtained. As it is apparent from FIG. 11, chlorine exists in high concentration near the interfaces between the underlying film and the crystal silicon film and between the crystal silicon film and the thermal oxide film.
[0265] While FIG. 11 corresponds to FIG. 8, the reason why the chlorine concentration is distributed as shown in FIG. 11 is considered to happen because the amorphous silicon film which is the starting film has been formed by the plasma CVD and the quality thereof is not dense.
[0266] As it is also apparent from FIG. 10, the nickel concentration is apt to be high also near the interface between the underlying film and the crystal silicon film. It is understood to happen as a result that nickel has been gettered to the underlying film by the action of chlorine existing near the interface with the underlying film (or within the underlying film).
[0267] Such phenomenon is considered to be obtained also when a halogen element is added to the underlying film.
Effects of the Invention
[0268] The use of the invention disclosed in the present specification allows to provide the technology for reducing the concentration of metal element within the crystal silicon film which has been obtained by utilizing the metal element which promotes the crystallization of silicon.
[0269] The use of this technology also allows a more reliable and higher performance thin film semiconductor device to be obtained.
Brief Description of Drawings
[0270] FIG. 1 is a diagram showing steps for obtaining a crystal silicon film;
[0271] FIG. 2 is a diagram showing steps for obtaining a crystal silicon film;
[0272] FIG. 3 is a diagram showing steps for fabricating a thin film transistor;
[0273] FIG. 4 is a diagram showing steps for fabricating a thin film transistor;
[0274] FIG. 5 is a diagram showing steps for fabricating a thin film transistor;
[0275] FIG. 6 is a graph showing distribution of concentration of nickel element;
[0276] FIG. 7 is a graph showing a distribution of concentration of nickel element;
[0277] FIG. 8 is a graph showing a distribution of concentration of chlorine element;
[0278] FIG. 9 is a graph showing a distribution of concentration of nickel element;
[0279] FIG. 10 is a graph showing a distribution of concentration of nickel element;
[0280] FIG. 11 is a graph showing a distribution of concentration of chlorine element.
Brief Description of Reference Numerals
[0281] 101: Glass Substrate or Quartz Substrate
[0282] 102: Underlying Layer (Silicon Oxide Film or Silicon Oxide Nitride Film)
[0283] 103: Amorphous Silicon Film
[0284] 104: Aqueous Film of Solution Containing Nickel
[0285] 105: Crystal Silicon Film
[0286] 106: Thermal Oxide Film
[0287] 107: Crystal Silicon Film in Which Concentration of Nickel Element Has Been Reduced
[0288] 201: Glass Substrate or Quartz Substrate
[0289] 202: Underlying Layer (Silicon Oxide Film or Silicon Oxide Nitride Film)
[0290] 203: Amorphous Silicon Film
[0291] 204: Mask Made of Silicon Oxide Film
[0292] 205: Aperture
[0293] 206: Nickel Held in Contact
[0294] 207: Direction of Crystal Growth In parallel to Substrate
[0295] 208: Silicon Film
[0296] 209: Thermal Oxide Film
[0297] 210: Patterned Silicon Film
Claims
What is claimed is:
1. An active matrix type EL display device comprising:
a substrate having an insulating surface;
at least one thin film transistor formed on said insulating surface, said thin film transistor having a crystalline semiconductor layer comprising at least source, drain, and channel regions, first and second gate insulating films, and a gate electrode;
an interlayer insulating film comprising inorganic material over said thin film transistor;
a layer comprising resin material over said thin film transistor with said interlayer insulating film interposed therebetween; and
at least one electrode electrically connected to said drain region of the thin film transistor through a contact hole provided in at least said layer comprising said resin material.
2. A device according to claim 1, wherein said insulating surface has a function of suppressing diffusion of impurities from said substrate.
3. A device according to claim 1, wherein said thin film transistor is a top gate type.
4. A device according to claim 1, wherein said crystalline semiconductor layer further comprises a pair of LDD regions.
5. A device according to claim 1, wherein said crystalline semiconductor layer including a metal element for promoting crystallization of said semiconductor at a concentration of 3×1017cm−3or less.
6. A device according to claim 1, wherein an electron spin density measured by ESR of said crystalline semiconductor layer is less than 3×1017cm−3.
7. An active matrix type EL display device comprising:
a substrate having an insulating surface;
a crystalline semiconductor layer comprising at least source, drain, and channel regions over said substrate;
first and second gate insulating films adjacent to said crystalline semiconductor layer, said first gate insulating film comprising a thermal oxide film of said semiconductor layer;
at least one gate electrode adjacent to said channel region with said first and second gate insulating films interposed therebetween;
an interlayer insulating film comprising inorganic material over said crystalline semiconductor layer and said gate electrode;
a layer comprising resin material over said crystalline semiconductor layer and said gate electrode with said interlayer insulating film interposed therebetween; and
at least one electrode electrically connected to said drain region through a contact hole provided in at least said layer comprising said resin material.
8. A device according to claim 7, wherein said insulating surface has a function of suppressing diffusion of impurities from said substrate.
9. A device according to claim 7, wherein said second gate insulating film includes at least one halogen element.
10. A device according to claim 7, wherein said gate electrode is located over said crystalline semiconductor layer.
11. A device according to claim 7, wherein said second gate insulating film is selected from the group consisting of a silicon oxynitride film and a silicon oxide film.
12. A device according to claim 7, wherein said crystalline semiconductor layer further comprises a pair of LDD regions.
13. A device according to claim 7, wherein said crystalline semiconductor layer including a metal element for promoting crystallization of said semiconductor at a concentration of 3×1017cm−3or less.
14. A device according to claim 7, wherein an electron spin density of said crystalline semiconductor measured by ESR is less than 3×1017cm−3.
15. An active matrix type EL display device comprising:
a substrate having an insulating surface;
at least one thin film transistor formed on said insulating surface, said thin film transistor having a crystalline semiconductor layer comprising at least source, drain, and channel regions, first and second gate insulating films, and a gate electrode;
an interlayer insulating film over said thin film transistor, said interlayer insulating film being selected from the group consisting of a silicon oxide film, a silicon nitride film, and a lamination film thereof;
a layer comprising resin material over said thin film transistor with said interlayer insulating film interposed therebetween; and
at least one electrode electrically connected to the drain region of the thin film transistor through a contact hole provided in at least said layer comprising said resin material.
16. A device according to claim 15, wherein said insulating surface has a function of suppressing diffusion of impurities from said substrate.
17. A device according to claim 15, wherein said thin film transistor is a top gate type.
18. A device according to claim 15, wherein said crystalline semiconductor layer further comprises a pair of LDD regions.
19. A device according to claim 15, wherein said crystalline semiconductor layer including a metal element for promoting crystallization of said semiconductor at a concentration of 3×1017cm−3or less.
20. A device according to claim 15, wherein an electron spin density measured by ESR of said crystalline semiconductor layer is less than 3×1017cm−3.
21. An active matrix type EL display device comprising:
a substrate having an insulating surface;
a crystalline semiconductor layer comprising at least source, drain, and channel regions over said substrate;
first and second gate insulating films adjacent to said crystalline semiconductor layer, said first gate insulating film comprising a thermal oxide film of said semiconductor layer;
at least one gate electrode adjacent to said channel region with said first and second gate insulating films interposed therebetween;
an interlayer insulating film over said crystalline semiconductor layer and said gate electrode, said interlayer insulating film being selected from the group consisting of a silicon oxide film, a silicon nitride film, and a lamination film thereof;
a layer comprising resin material over said crystalline semiconductor layer and said gate electrode with said interlayer insulating film interposed therebetween; and
at least one electrode electrically connected to said drain region through a contact hole provided in at least said layer comprising said resin material.
22. A device according to claim 21, wherein said insulating surface has a function of suppressing diffusion of impurities from said substrate.
23. A device according to claim 21, wherein said second gate insulating film includes at least one halogen element.
24. A device according to claim 21, wherein said gate electrode is located over said crystalline semiconductor layer.
25. A device according to claim 21, wherein said second gate insulating film is selected from the group consisting of a silicon oxynitride film and a silicon oxide film.
26. A device according to claim 21, wherein said crystalline semiconductor layer further comprises a pair of LDD regions.
27. A device according to claim 21, wherein said crystalline semiconductor layer including a metal element for promoting crystallization of said semiconductor at a concentration of 3×1017cm−3or less.
28. A device according to claim 21, wherein an electron spin density of said crystalline semiconductor measured by ESR is less than 3×1017cm−3.
29. An active matrix type EL display device comprising:
a substrate having an underlayer insulating film;
at least one thin film transistor formed on said underlayer insulating film, said thin film transistor having a crystalline semiconductor layer comprising at least source, drain, and channel regions, first and second gate insulating films, and a gate electrode;
an interlayer insulating film comprising inorganic material over said thin film transistor;
a layer comprising resin material over said thin film transistor with said interlayer insulating film interposed therebetween; and
at least one electrode electrically connected to said drain region of the thin film transistor through a contact hole provided in at least said layer comprising said resin material,
wherein said underlayer insulating film has a function of suppressing diffusion of impurities from said substrate.
30. A device according to claim 29, wherein said underlayer insulating film is selected from the group consisting of a silicon oxynitride film and a silicon oxide film.
31. A device according to claim 29 wherein said thin film transistor is a top gate type.
32. A device according to claim 29 wherein said crystalline semiconductor layer further comprises a pair of LDD regions.
33. A device according to claim 29, wherein said interlayer insulating film is selected from the group consisting of a silicon oxide film, a silicon nitride film, and a lamination film thereof.
34. A device according to claim 29, wherein said crystalline semiconductor layer including a metal element for promoting crystallization of said semiconductor at a concentration of 3×1017cm−3or less.
35. A device according to claim 29, wherein an electron spin density measured by ESR of said crystalline semiconductor layer is less than 3×1017cm−3.
36. An active matrix type EL display device comprising an active matrix region over a substrate having an insulating surface, said active matrix region comprising:
at least one first thin film transistor formed on said insulating surface, said first thin film transistor having a crystalline semiconductor layer comprising at least source, drain, and channel regions, at least one LDD region, first and second gate insulating films, and a gate electrode;
an interlayer insulating film comprising inorganic material over said first thin film transistor;
a layer comprising resin material over said first thin film transistor with said interlayer insulating film interposed therebetween; and
at least one electrode electrically connected to said drain region of the thin film transistor through a contact hole provided in at least said layer comprising said resin material.
37. A display according to claim 36, wherein said first gate insulating film is a thermal oxide film of said semiconductor layer and said second gate insulating film is a deposit film.
38. A display according to claim 36, wherein said interlayer insulating film comprises at least silicon and nitrogen.
39. An active matrix type EL display device comprising an active matrix region over a substrate having an insulating surface, said active matrix region comprising:
a first crystalline semiconductor layer comprising at least source, drain, and channel regions, and at least one LDD region over said substrate;
first and second gate insulating films adjacent to said first crystalline semiconductor layer, said first gate insulating film comprising a thermal oxide film of said semiconductor layer;
at least one first gate electrode adjacent to said channel region of said first crystalline semiconductor layer with said first and second gate insulating films interposed therebetween;
an interlayer insulating film comprising inorganic material over said first crystalline semiconductor layer and said first gate electrode;
a layer comprising resin material over said first crystalline semiconductor layer and said first gate electrode with said interlayer insulating film interposed therebetween; and
at least one electrode electrically connected to said drain region of said first crystalline semiconductor layer through a contact hole provided in at least said layer comprising said resin material.
40. A device according to claim 39, wherein said second gate insulating film is selected from the group consisting of a silicon oxynitride film and a silicon oxide film.
41. A device according to claim 39, wherein said interlayer insulating film comprises at least silicon and nitrogen.
42. An active matrix type EL display device comprising an active matrix region over a substrate having an insulating surface, said active matrix region comprising:
at least one first thin film transistor formed on said insulating surface, said first thin film transistor having a crystalline semiconductor layer comprising at least source, drain, and channel regions, at least one LDD region, first and second gate insulating films, and a gate electrode;
an interlayer insulating film over said first thin film transistor, said interlayer insulating film being selected from the group consisting of a silicon oxide film, a silicon nitride film, and a lamination film thereof;
a layer comprising resin material over said first thin film transistor with said interlayer insulating film interposed therebetween; and
at least one electrode electrically connected to the drain region of the first thin film transistor through a contact hole provided in at least said layer comprising said resin material.
43. A display according to claim 42, wherein said first gate insulating film is a thermal oxide film of said semiconductor layer and said second gate insulating film is a deposit film.
44. A display according to claim 42, wherein said gate electrode is located over said crystalline semiconductor layer.
45. An active matrix type EL display device comprising an active matrix region over a substrate having an insulating surface, said active matrix region comprising:
a first crystalline semiconductor layer comprising at least source, drain, and channel regions, and at least one LDD region over said insulating surface;
first and second gate insulating films adjacent to said first crystalline semiconductor layer, said first gate insulating film comprising a thermal oxide film of said semiconductor layer;
at least one first gate electrode adjacent to said channel region of said first crystalline semiconductor layer with said first and second gate insulating films interposed therebetween;
an interlayer insulating film over said first crystalline semiconductor layer and said first gate electrode, said interlayer insulating film being selected from the group consisting of a silicon oxide film, a silicon nitride film, and a lamination film thereof;
a layer comprising resin material over said first crystalline semiconductor layer and said first gate electrode with said interlayer insulating film interposed therebetween; and
at least one electrode electrically connected to said drain region of said first crystalline semiconductor layer through a contact hole provided in at least said layer comprising said resin material.
46. A device according to claim 45, wherein said second gate insulating film is selected from the group consisting of a silicon oxynitride film and a silicon oxide film.
47. A device according to claim 45, wherein said gate electrode is located over said crystalline semiconductor layer.
48. An active matrix type EL display device comprising an active matrix region over a substrate having an underlayer insulating film, said active matrix region comprising:
at least one first thin film transistor formed on said underlayer insulating film, said first thin film transistor having a crystalline semiconductor layer comprising at least source, drain, and channel regions, at least one LDD region, first and second gate insulating films, and a gate electrode;
an interlayer insulating film comprising inorganic material over said first thin film transistor;
a layer comprising resin material over said first thin film transistor with said interlayer insulating film interposed therebetween; and
at least one electrode electrically connected to said drain region of the first thin film transistor through a contact hole provided in at least said layer comprising said resin material,
wherein said underlayer insulating film has a function of suppressing diffusion of impurities from said substrate.
49. A display according to claim 48, wherein said first gate insulating film is a thermal oxide film of said semiconductor layer and said second gate insulating film is a deposit film.
50. A display according to claim 48, wherein said interlayer insulating film comprises at least silicon and nitrogen.
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