Interconnect for testing semiconductor components and method of fabrication

[0002] This application is a division of application Ser. No. 09/234,725, filed Jan. 21, 1999, now U.S. Pat. No. 6,242,935.

[0003] This invention relates generally to semiconductor manufacture and specifically to an interconnect for testing semiconductors components such as wafers containing semiconductor dice, and substrates containing semiconductor packages.

[0004] Semiconductor components can be manufactured using wafer level fabrication processes in which multiple components are contained on a single substrate. Semiconductor dice, for example, are typically fabricated on substrates in the form of silicon wafers. Following the fabrication process, the dice can be singulated into individual units.

[0005] Semiconductor packages, such as BGA packages, can also be manufactured using wafer level fabrication processes. A BGA package includes an array of external ball contacts, such as solder balls, that permit the package to be surface mounted to a printed circuit board (PCB) or other electronic component. Some BGA packages have a foot print that is about the size of the die contained in the package. These BGA packages are also known as chip scale packages.

[0006] Multiple BGA packages can be fabricated on a single substrate formed of an electrically insulating material. Sometimes the substrate comprises a reinforced polymer laminate, such as bismaleimide triazine (BT), or an epoxy resin (e.g., FR-4). BGA packages can also be fabricated using ceramic or silicon substrates. The substrate can be in the form of a wafer, or in the form of a panel of material.

[0007] During, or following, the fabrication process it is usually necessary to perform test procedures on the components to evaluate various electrical characteristics of the components. For example, wafer probe testing can be used to evaluate the gross functionality of dice contained on a wafer.

[0008] In order to perform the test procedures it is necessary to make temporary electrical connections with contacts on the components. Semiconductor dice typically include contacts in the form of planar aluminum bond pads, or bond pads bumped with solder bumps. Semiconductor packages typically include contacts in the form of solder balls arranged in a dense area array. For making these temporary electrical connections an interconnect is employed. A wafer probe card is one type of interconnect, and includes probe needles that electrically engage the bond pads on the wafer.

[0009] As semiconductor components become smaller, and the contacts on the components become more dense, the temporary electrical connections with the contacts become more difficult to make. Variations in the size and location of the contacts also make the temporary electrical connections difficult to make. In particular, the z-direction location and planarity of contacts can vary between different components on a substrate, and can vary between contacts on the same component. This makes it difficult to make reliable electrical connections with the contacts.

[0010] In addition, the contacts can be damaged by the interconnect. Solder balls are particularly susceptible to deformation and loosening of the solder joints that hold the balls on the components. Also, native oxide layers are usually present on the component contacts, and these oxide layers must be penetrated by the contacts on the interconnect. This requires application of forces for scrubbing or penetrating the contacts on the components.

[0011] The present invention is directed to an interconnect that can be used to test multiple components contained on a substrate. The interconnect includes contacts that are configured to accommodate dimensional variations, and to accommodate different z-axis locations of the contacts on the components.

[0012] In accordance with the present invention, an interconnect for testing semiconductor components, a test system employing the interconnect, and a method for fabricating the interconnect, are provided. The interconnect is configured to test multiple components contained on a substrate, such as semiconductor dice contained on a wafer, or chip scale packages contained on a panel. In addition, the interconnect can be configured to test semiconductor components having planar contacts, such as bond pads, or to test semiconductor components having ball contacts, such as solder bumps on bumped dice, or solder balls on chip scale packages.

[0013] The interconnect, broadly stated, comprises: a substrate; a polymer layer formed on a face of the substrate; a pattern of contacts formed on the polymer layer; and conductive members in the substrate for providing electrical paths from the contacts to external contact pads on a back side of the substrate.

[0014] The interconnect substrate comprises an electrically insulating material such as glass reinforced resin, or ceramic, or alternately a semiconducting material, such as silicon. The polymer layer comprises a resilient or compliant material such as polyimide, or a photosensitive polyimide which simplifies the fabrication process. The polymer layer provides a resilient or compliant support structure for the interconnect contacts such that movement in the z-direction is possible. This allows the interconnect contacts to move during a test procedure to accommodate differences in the z-axis location, or planarity, of the contacts on the components.

[0015] For testing components with planar contacts, the interconnect contacts comprise bumps deposited on conductive layers formed in recesses in the polymer layer. For testing components with ball contacts, the interconnect contacts comprise recesses in the polymer layer covered with conductive layers. In either embodiment the interconnect contacts are in electrical communication with conductive members, which can comprise openings in the interconnect substrate at least partially filled with a conductive material.

[0016] The conductive members provide straight line electrical paths from the interconnect contacts to the external contact pads on the back side of the interconnect. The contact pads are configured for electrical engagement by spring loaded electrical connectors (e.g.,“POGO PINS”) in electrical communication with test circuitry. In addition to performing an electrical function the spring loaded electrical connectors can also perform a force applying function for biasing the interconnect against the components.

[0017] A system constructed in accordance with the invention comprises: a tester having a test head in electrical communication with test circuitry; a probe card mounted to the test head; an interconnect mounted to the probe card; a force applying mechanism having spring loaded electrical connectors in electrical communication with the test circuitry and adapted to press the interconnect against the components; and a wafer chuck for supporting and aligning the components to the interconnect.

[0018] FIG. 1A is a schematic plan view of a prior art substrate in the form of a semiconductor wafer containing multiple semiconductor dice;

[0019] FIG. 1B is an enlarged cross sectional view taken along section line 1B—1B of FIG. 1A illustrating a semiconductor die on the wafer;

[0020] FIG. 1C is an enlarged cross sectional view taken along section line 1C—1C of FIG. 1B illustrating a bumped bond pad on the die;

[0021] FIG. 2A is a schematic plan view of a prior art substrate in the form of a panel containing multiple semiconductor packages;

[0022] FIG. 2B is an enlarged cross sectional view taken along section line 2B—2B of FIG. 2A illustrating a semiconductor package on the panel;

[0023] FIG. 3 is an enlarged cross sectional view equivalent to FIG. 1C illustrating a planar bond pad on the die;

[0024] FIG. 4 is a schematic plan view of an interconnect constructed in accordance with the invention configured for testing semiconductor components having ball contacts;

[0025] FIG. 4A is an enlarged portion of FIG. 4 taken along section line 4A illustrating a pattern of contacts on the interconnect;

[0026] FIG. 4B is a cross sectional view of a portion of the interconnect taken along section line 4B—4B of FIG. 4A;

[0027] FIG. 4C is an enlarged cross sectional view taken along section line 4C—4C of FIG. 4A illustrating a contact on the interconnect;

[0028] FIG. 4D is an enlarged cross sectional view equivalent to FIG. 4C but illustrating the contact of FIG. 4C electrically engaging a ball contact on a semiconductor component;

[0029] FIG. 5 is a schematic plan view of an alternate embodiment interconnect constructed in accordance with the invention configured for testing semiconductor components having planar contacts;

[0030] FIG. 5A is an enlarged portion of FIG. 5 taken along section line 5A illustrating a pattern of contacts on the interconnect;

[0031] FIG. 5B is a cross sectional view of a portion of the alternate embodiment interconnect taken along section line 5B—5B of FIG. 5A;

[0032] FIG. 5C is an enlarged cross sectional view taken along section line 5C—5C of FIG. 5A illustrating a contact on the alternate embodiment interconnect;

[0033] FIG. 5D is an enlarged cross sectional view equivalent to FIG. 5C but illustrating the contact of FIG. 5C electrically engaging a planar contact on a semiconductor component;

[0034] FIG. 6A is a schematic cross sectional view of a wafer level test system employing an interconnect constructed in accordance with the invention;

[0035] FIG. 6B is an enlarged schematic portion of FIG. 6A taken along section line 6B and illustrating a portion of the interconnect of FIG. 4;

[0036] FIG. 6C is an enlarged schematic portion of FIG. 6A taken along section line 6C and illustrating a portion of the interconnect of FIG. 5; and

[0037] FIGS. 7A-7F are schematic cross sectional views illustrating process steps for fabricating the interconnect of FIGS. 4-4C or FIGS. 5-5D.

[0038] Referring to FIGS. 1A-1D, 2A-2B, and 3, various prior art substrates containing semiconductor components are illustrated. As will be further explained, an interconnect can be constructed in accordance with the invention for electrically contacting each of the substrates, as well as other types of substrates containing semiconductor components.

[0039] In FIG. 1A, a substrate comprises a semiconductor wafer 10W containing a plurality of components in the form of semiconductor dice 12D. Typically, the semiconductor wafer 10W comprises a semiconducting material such as silicon or gallium arsenide. FIG. 1B illustrates a die 12D that has been separated from the wafer 10W. Each die 12D includes an array of ball contacts 14D, such as solder bumps, formed on a face thereof. The ball contacts 14D are formed in a pattern P1, such as a dense grid array.

[0040] As shown in FIG. 1C, the ball contacts 14D are bonded to planar bond pads 16D on the die 12D in electrical communication with the integrated circuits contained on the die 12D. The bond pads 16D are embedded in a die passivation layer 20D formed on the face of the die 12D. As also shown in FIG. 1C, solder fillets 18D attach the ball contacts 14D to the bond pads 16D.

[0041] Alternately, as shown in FIG. 3, the ball contacts 14D are omitted on some types of dice, such that the bond pads 16D provide planar contacts for the die 12D. In either case, dimensional variations, such as the size or location of the ball contacts 14D, can cause differences in the z-axis location, or planarity, of the ball contacts 14D, or the bond pads 16D on the die 12D. In FIG. 1C this z-axis difference is indicated by the dotted lines which represent a larger ball contact 14D, and the delta z which represents the size difference of the larger ball contact 14D. In general, these z-direction variations can occur among ball contacts 14D on the same die 12D, or on different dice 12D contained on the same wafer 10W.

[0042] Referring to FIG. 2A, a substrate comprises a panel 10P containing a plurality of semiconductor components in the form of chip scale packages 12CSP. Typically, the panel 10P comprises an electrically insulating material such as ceramic, a reinforced polymer laminate, such as bismaleimide triazine (BT), or an epoxy resin (e.g., FR-4).

[0043] As shown in FIG. 2B, each chip scale package 12CSP includes a substrate 10CSP. The substrate 10CSP comprises a segment of the panel 10P which has been cut, sheared, punched or otherwise separated from a remainder of the panel 10P. In addition, each chip scale package 12CSP includes a semiconductor die 22CSP wire bonded to the substrate 10CSP, and an adhesive layer 26CSP which attaches the die 22CSP to the substrate 10CSP. Each chip scale package 12CSP also includes an array of ball contacts 14CSP in electrical communication with the integrated circuits contained on the die 22CSP.

[0044] The ball contacts 14CSP are attached to the substrate 10CSP in a dense grid array, such as a ball grid array (BGA). By way of example, a representative diameter D1 for the ball contacts 14CSP can be about 0.005-in (0.127 mm) to 0.050-in (1.270 mm) or greater. A representative pitch P (center to center spacing) of the ball contacts 14CSP can be from about 0.008-in (0.228 mm) to about 0.060-in (1.524 mm) or greater. Due to differences in the diameters and locations of the ball contacts 14CSP, the z-axis location, or planarity, of the ball contacts 14CSP in the array can vary. This dimensional variation is indicated by delta z in FIG. 2B. In addition, the variation can occur between ball contacts 14CSP on the same component or between ball contacts 14CSP on different components on the panel 10P.

[0045] Referring to FIGS. 4-4C, an interconnect 40 constructed in accordance with the invention is illustrated. The interconnect 40 comprises: a substrate 42; a polymer layer 44 formed on a face 70 of the substrate 42; a plurality of patterns P2 of contacts 46 formed on the polymer layer 44 and adapted to make temporary electrical connections with ball contacts 14CSP (FIG. 4D) on semiconductor components 12CSP (FIG. 2A) contained on panel 10P (FIG. 2A); and a plurality of external contact pads 60 formed on a back side 58 of the substrate 42 in electrical communication with the contacts 46.

[0046] In the illustrative embodiment the interconnect 40 has a generally square peripheral outline which corresponds to the square panel 10P (FIG. 2A). However, this outline is merely exemplary. Alternately other outlines, such as an outline that corresponds to that of a semiconductor wafer can be employed (e.g., generally circular with a major flat). In addition, as will be more fully hereinafter explained, the interconnect 40 includes a stepped surface 126 for mounting purposes.

[0047] The substrate 42 can comprise an electrically insulating material such as ceramic, or a reinforced polymer laminate, such as bismaleimide triazine (BT), or an epoxy resin (e.g., FR-4). The substrate 42 can also comprise a semiconducting material such as silicon, silicon-on-glass, or gallium arsenide, in which case additional insulating layers can be formed on the substrate 42 as will be hereinafter described.

[0048] The polymer layer 44 comprises an electrically insulating material having a natural resiliency, or compliancy, that permits the contacts 46 to move in the z-direction during a test procedure using the interconnect 40. The permits the contacts 46 to make reliable electrical connections even with z-direction variations among the contact balls 14CSP (e.g., delta z in FIG. 2B).

[0049] Suitable materials for the polymer layer 44 include polyimide, photoimageable polyimide, polyester, epoxy, urethane, polystyrene, silicone and polycarbonate. These materials can be cast in place to a desired thickness using known processes such as spin on, or dispensing through a nozzle. Alternately, these materials can be in the form of a tape, such as “KAPTON” tape, which can be applied to the substrate 42 using an adhesive layer. A representative thickness “t” (FIG. 4C) for the polymer layer 44 can be from 0.5 μm to 150 μm.

[0050] As shown in FIG. 4C, the polymer layer 44 includes recesses 48 wherein the contacts 46 are formed. The recesses 48 can be etched by forming a mask (not shown) on the polymer layer 44, such as a photopatterned resist mask, and then etching the polymer layer 44 through openings in the mask, using an etchant. With the polymer layer 44 comprising polyimide, a suitable etchant for performing the etch process comprises a solution of TMAH (tetramethylammonium hydroxide). If the polymer layer 44 comprises a photoimageable polyimide, an etch mask is not required, as the photoimageable material can be patterned by exposure to UV and then developed using a suitable developing solution.

[0051] A size and shape of the recesses 48 will be determined by the openings in the etch mask used to etch the polymer layer 44, or alternately by the exposure mask used to pattern a photoimageable polymer layer 44. The recesses 48 are sized and shaped to retain and electrically engage the ball contacts 14CSP (FIG. 4D). A representative diameter, or width, of the recesses 48 can be from 2 mils to 50 mils or more. This diameter can be less than a diameter of the ball contacts 14CSP so that only portions of the ball contacts 14CSP will be contacted. A depth of the recesses 48 can be equal to a thickness “t” of the polymer layer 44, or can be less than the thickness “t”. A pitch or spacing of the recesses 48 will exactly match a pitch or spacing of the ball contacts 14CSP (FIG. 4D). A pattern P2 of the contacts 46 thus exactly matches a pattern of the ball contacts 14 (e.g., pattern P1—FIG. 1B).

[0052] As shown in FIG. 4C, in addition to the recesses 48, the contacts 46 include conductive layers 50 formed within the recesses 48. Peripheral edges 52 of the conductive layers 50 are adapted to penetrate native oxide layers on the ball contacts 14CSP (FIG. 4D) to contact the underlying metal. The conductive layers 50 can be formed as a layer of a highly conductive metal such as aluminum, titanium, nickel, iridium, copper, gold, tungsten, silver, platinum, palladium, tantalum, molybdenum or alloys of these metals.

[0053] As also shown in FIG. 4C, the contacts 46 include conductive members 54 formed within through openings 56 in the substrate 42. The openings 56 for the conductive members 54 can be formed by etching, punching, or laser machining the substrate 42. U.S. patent application Ser. No. 08/993,965, filed Dec. 10, 1997, now U.S. Pat. No. 6,107,109, entitled “Semiconductor Interconnect Having Laser Machined Contacts”, which is incorporated herein by reference, describes a method for laser machining the openings 56.

[0054] As will be more fully explained the conductive members 54 can comprise a metal, such as the previously described metals for the conductive layers 50, or can comprise a conductive polymer.

[0055] Still referring to FIG. 4C, the conductive members 54 are formed within the openings in electrical contact with the conductive layers 50. The conductive members 54 provide straight line electrical paths from the contacts 46 on the face 70 of the substrate 42 to the external contact pads 60 on the back side 58 of the substrate 42. The external contact pads 60 are adapted for making electrical connections to the outside, such as test circuitry for performing test procedures. As will be further explained, the pads 60 are adapted for physical and electrical contact by a mating electrical connector (e.g., “POGO PIN”) of a test system, or other electrical assembly, that will employ the completed interconnect 40.

[0056] Referring to FIGS. 5-5D, an alternate embodiment interconnect 40A is illustrated. The interconnect 40A is adapted to make electrical connections with planar bond pads 16D (FIG. 5D) on semiconductor dice 12D (FIG. 1A) contained on a wafer 10W (FIG. 1A). As, such the interconnect has a peripheral shape corresponding to the semiconductor wafer 10W (FIG. 1A).

[0057] The interconnect 40 comprises: a substrate 42A; a polymer layer 44A formed on a face 70A of the substrate 42A; a plurality of patterns P2 of contacts 46A formed on the polymer layer 44A adapted to make temporary electrical connections with the bond pads 16D (FIG. 5D); and a plurality of external contacts pads 60A in electrical communication with the contacts 46A. These elements function substantially the same as the substrate 42, polymer layer 44 and contacts 46 previously described and shown in FIGS. 4-4D.

[0058] However, in the alternate embodiment interconnect 40A, the substrate 42A comprises silicon, such that additional insulating layers 64A must be formed to electrically insulate the bulk of the substrate 42A and openings 56A for the conductive members 54A. In addition, the conductive members 54A are offset from the contacts 46A, and are in electrical communication with conductors 66A formed on the substrate 42A. Still further, the conductive members 54A include bumps 62A formed on the conductive layers 50A for electrically engaging the bond pads 16D (FIG. 5D).

[0059] The insulating layers 64A can comprise a grown or deposited dielectric material such as SiO₂, Si₃N₄or a deposited polymer, such as polyimide. The conductors 66A can comprise a highly conductive metal such as those previously described for conductive layers 50 (FIG. 4C). In addition, the conductors 66A can be formed using a subtractive process as previously described (e.g., blanket deposition, photopatterning and etching of a metal layer), or can be formed using an additive process (e.g., deposition of a metal through openings in a mask). The conductors 66A allow the external contact pads 60A to be formed in a pattern that is different than the pattern P2 of the contacts 46A.

[0060] The bumps 62A can be formed on the conductive layers 50A using a suitable deposition process, such as electrolytic, or electroless plating of a metal. Suitable metals for the bumps 62A include copper, nickel, gold and palladium. For some metals such as copper a non-oxidizing layer 68A can be formed on the bumps 62A out of a non-oxidizing metal such as gold. The bumps 62A can also comprise a conductive polymer material such as a silver filled epoxy or isotropic adhesive as previously described for conductive members 54 (FIG. 4C). In this case the conductive polymer material can be deposited on the conductive layers 50A using a process such as screen printing and then cured as required. Still further, the bumps 62A can comprise a solder material deposited by screen printing or by evaporation through a mask.

[0061] These and other processes for forming the bumps 62A are described in parent application U.S. Pat. No. 5,808,360 entitled “Microbump Interconnect For Bare Semiconductor Dice”; and in U.S. Pat. No. 5,789,271 entitled “Method For Fabricating Microbump Interconnect For Bare Semiconductor Dice”, both of which are incorporated herein by reference.

[0062] Referring to FIGS. 6A-6C, a wafer test system 80 constructed in accordance with the invention is shown. The test system 80 is configured to test semiconductor dice 12D contained on the semiconductor wafer 10W, or alternately to test chip scale packages 12CSP contained on the panel 10P. The test system 80 includes a probe card 82 which includes the interconnect 40 or 40A. Depending on its configuration, the interconnect 40 or 40A makes temporary electrical connections with ball contacts 14D (FIG. 1C), ball contacts 14CSP (FIG. 2B), or bond pads 16D (FIG. 3) on the components under test. The test system 80 also includes a wafer handler 84, and a tester 86 having test circuitry 88 for applying and analyzing test signals.

[0063] The wafer handler 84 interfaces with a test head 90 wherein the probe card 82 is mounted. In addition, the wafer handler 84 includes a wafer chuck 92 configured to move in X and Y directions to align the wafer 10W or the panel 10P, with the probe card 82, and in the Z direction to move the wafer 10W or the panel 10P into contact with the interconnect 40 or 40A. The wafer handler 84 can also include an optical or mechanical alignment system (not shown) for aligning the wafer 10W or the panel 10P, to the interconnect 40 or 40A. One suitable wafer handler 84 is manufactured by Electroglass and is designated a Model 4080.

[0064] The test system 80 also includes a prober interface board 94 for routing test signals from the tester 86 to the test head 90, and then to the probe card 82. The prober interface board 94 can be mounted to the test head 90. In addition, the prober interface board 94 can be in electrical communication with tester pin electronics 96 in the test head 90. Separate electrical paths 98 are provided from the test circuitry 88 in the tester 86 to the tester pin electronics 96, and to the prober interface board 94. The prober interface board 94 includes separate electrical paths 98 to the probe card 82.

[0065] The probe card 82, generally stated, comprises: a probe card substrate 100; the interconnect 40 or 40A; and a force applying mechanism 102. The probe card substrate 100 can comprise an electrically insulating material, such as a glass filled resin (e.g., FR-4), a ceramic, or plastic. The probe card substrate 100 includes an opening 104 wherein the force applying mechanism 102 is mounted. Viewed from above, the opening 104 is generally rectangular shaped to accommodate a mating rectangular shape of the force applying mechanism 102. However, as is apparent, a rectangular shape is merely exemplary.

[0066] The probe card substrate 100 can be attached to a probe card fixture 106 mounted within the test head 90. Threaded fasteners 108 can be used to removably attach the probe card substrate 100 to the probe card fixture 106. If desired, the probe card substrate 100 can be a conventional probe card having the middle portion removed to form the opening 104. The probe card fixture 106 can also be a conventional component. Conventional probe cards and probe card fixtures are available from Packard Hughes Interconnect, Los Angeles, Calif., and Wentworth Laboratories, Sunnyvale, Calif.

[0067] The force applying mechanism 102 includes a base 110 which attaches to the probe card substrate 100. In addition, the force applying mechanism 102 includes a plurality of spring loaded electrical connectors 112 mounted to a pin mounting plate 114 attached to the base 110. The electrical connectors 112 physically and electrically engage the external contact pads 60 (FIG. 6B) or 60A (FIG. 6C). The electrical connectors 112 can be commercially available spring loaded electrical connectors, such as “POGO PINS” manufactured by Pogo Industries of Kansas City, Kans. Other suitable spring loaded electrical connectors include “DURASEAL” connectors manufactured by IDI, Kansas City, Kans.

[0068] The interconnect 40 or 40A is slidably mounted to a two piece interconnect support plate 116 that attaches to the probe card substrate 100 with threaded fasteners 108. In addition, spring biased threaded fasteners 120 allow a planarity of the interconnect support plate 116 to be adjusted.

[0069] As shown in FIGS. 6A-6C, the interconnect support plate 116 includes an opening 122 formed with a peripheral lip 124 for supporting the interconnect 40 or 40A. The interconnect 40 or 40A includes a stepped surface 126 (FIG. 6B) or 126A (FIG. 6C) that engages the lip 124 and allows the interconnect contacts 46 (FIG. 6B) or 46A (FIG. 6C) to project from the interconnect support plate 116. The stepped surface 126 or 126A of the interconnect 40 or 40A can be formed by an etching or a machining process during fabrication of the interconnect 40 or 40A.

[0070] The peripheral lip 124 of the interconnect support plate 116 prevents the interconnect 40 or 40A from separating from the interconnect support plate 116. However, the interconnect 40 or 40A is movable within the opening 122 in the z-direction towards the electrical connectors 112. The opening 122 can be sized to prevent excessive movement of the interconnect 40 or 40A in the X and Y directions. If desired, dots of a resilient polymer material such as silicone can be placed in a gap between the interconnect 40 or 40A and opening 122. The dots of resilient material can be used to retain the interconnect 40 or 40A while allowing some Z-direction movement of the interconnect 40 or 40A.

[0071] The interconnect 40 or 40A is maintained in a stationary position within the opening 122 by spring pressure exerted by the electrical connectors 112. However, during a test procedure, the wafer 10W or the panel 10P, can be overdriven in the z-direction with respect to the interconnect 40 or 40A, to move the interconnect 40 or 40A in the z-direction towards the electrical connectors 112. With the z-direction overdrive, a contact force with which the interconnect contacts 46 (FIG. 6B) or 46A (FIG. 6C) press into the contacts 14D (FIG. 1C) or 16D (FIG. 3) or 14CSP (FIG. 2B) on the components under test is generated by compression of the spring components of the electrical connectors 112. In addition, the polymer layer 44 (FIG. 6B) under contacts 46 (FIG. 6B), or the polymer layer 44A (FIG. 6C) under contacts 46A (FIG. 6C) allows individual contacts 46 or 46A to move in the z-direction to accommodate difference in the z-direction location and planarity of the contacts 14D (FIG. 1C) or 16D (FIG. 3) or 14CSP (FIG. 2B).

[0072] The force exerted by the electrical connectors 112 will be dependent on a spring constant, and amount of compression, of the spring components of the electrical connectors 112. A representative value for the force F can be from 0.10 oz to 1.5 oz per electrical connector 112. As used herein, the term z-direction overdrive refers to movement of the wafer 10W or panel 10P, or of the probe card 82, towards one another past the initial point of contact between the interconnect contacts 46 or 46A and the external contacts 16D or 14CSP. The z-direction overdrive determines the amount of compression in the spring components of the electrical connectors 112 and thus the magnitude of the force. A representative amount of z-direction overdrive can be from 0.25 mils to 8 mils.

[0073] Referring to FIGS. 7A-7F, steps in a method for fabricating the interconnect 40 (FIG. 4A) are illustrated. As shown in FIG. 7A, the substrate 42 can be provided. Preferably, the substrate 42 comprises a wafer of material on which multiple interconnects will be fabricated using semiconductor circuit fabrication techniques, and then singulated by cutting the wafer. Such a process is referred to as a wafer level fabrication process.

[0074] In the embodiment illustrated in FIGS. 7A-7F, the substrate 42 comprises an electrically insulating material such as a ceramic material, or reinforced polymer laminate, such as bismaleimide triazine (BT), or an epoxy resin (e.g., FR-4).

[0075] The substrate 40 includes the face 70 and the opposing back side 58. The face 70 and back side 58 of the substrate 40 are planar surfaces generally parallel to one another. A representative thickness of the substrate 10 can be from about 12 mils to 38 mils.

[0076] As shown in FIG. 7A the polymer layer 44 is initially deposited on the face 70 of the substrate 40. Suitable materials for the polymer layer 44 include polyimide, photoimageable polyimide, polyester, epoxy, urethane, polystyrene, silicone and polycarbonate. In the illustrative embodiment, the polymer layer 44 comprises a photoimageable polyimide which can be patterned using UV and then developed using a developer solution. Photosensitive polyimide compositions are commercially available, and are described in U.S. Pat. Nos. 5,589,319; and 5,616,448.

[0077] The polymer layer 44 can be blanket deposited to a desired thickness using spin coating or other suitable process. A representative thickness can be from 0.5 μm to 150 μm. Following blanket deposition the polymer layer 44 can be soft baked (e.g., 100° C. for several minutes) and then subjected to UV exposure energy at a suitable intensity (e.g., I-line at 230-330 mJ/cm²). The exposed polymer layer 44 can then be cleaned and cured by heating in an inert ambient for several hours (e.g., 350° C. for 2-3 hours).

[0078] As shown in FIG. 7B, following curing the polymer layer 44 can be developed with the recesses 48 for the contacts 46. Depending on the formula of the polymer layer different developing solutions can be employed to form the recesses 48. One suitable developing solution comprises an aqueous solution of tetramethylammonium hydroxide (TMAH). The recesses 48 have a size and pattern that corresponds to the size and pattern of the ball contacts 14 (FIG. 4D) on the component 12 (FIG. 4D). In the illustrative embodiment the recesses 48 extend completely through the polymer layer 44 and end point at the face 70 of the substrate 42. Alternately the exposure and developing steps can be controlled such that the recesses 48 end point within the polymer layer 44.

[0079] If the polymer layer 44 does not comprise a photosensitive material, the recesses 48 can be etched by formed a photomask and etching through openings in the mask. The recesses 48 can also be formed using a laser, or using a machining process.

[0080] As shown in FIG. 7C, following formation of the recesses 48, the conductive layers 50 are formed within the recesses 48. Peripheral edges 52 of the conductive layers 50 are adapted to penetrate native oxide layers on the ball contacts 14CSP (FIG. 4D) to contact the underlying metal. The conductive layers 50 can be formed as a layer of a highly conductive metal such as aluminum, titanium, nickel, iridium, copper, gold, tungsten, silver, platinum, palladium, tantalum, molybdenum or alloys of these metals. Rather than being a single layer of metal, the conductive layers 50 can be formed as multi-layered stacks of metals (e.g., bonding layer/barrier layer). Rather than being a single layer of metal, the conductive layers 50 can be formed as multi-layered stacks of metals (e.g., bonding layer/barrier layer). Also, the conductive layers 50 can comprise an alloy such as TiN, TiW, TiC or NiB.

[0081] The conductive layers 50 can be formed using a metallization process (e.g., deposition, photopatterning, etching). An exemplary metallization process is disclosed in U.S. Pat. No. 5,607,818, incorporated herein by reference. The conductive layers 50 can also be formed using a plating process, such as electrolytic deposition, or electroless deposition. A representative thickness of the conductive layers 50 is from 600 Å to 20000 Å.

[0082] As shown in FIG. 7D, following formation of the conductive layers 50, openings 56 can be formed through the conductive layers 50, and through the substrate 42 to the back side 58 thereof. One method for forming the openings 56 is with a laser machining process.

[0083] A suitable laser machining apparatus is manufactured by General Scanning of Sommerville, Mass. and is designated a model no. 670-W. A representative diameter of the openings 56 is from 10 μm to 2 mils or greater. A representative laser fluence for forming the openings 56 is from 2 to 10 watts/per opening at a pulse duration of 20-25 ns and at a repetition rate of up to several thousand per second. The wavelength of the laser beam can be a standard infrared or green wavelength (e.g., 1064 nm-532 nm).

[0084] In FIG. 7D, the openings 56 are generally perpendicular to the face 70 and back side 58 of the substrate 52. In addition, the openings 56 are located along a longitudinal axis 128 which will be the center line of the completed contacts 46 (FIG. 7E). Alternately, the openings 56 can be offset from the center line of the contacts 46 or outside of the contacts 46.

[0085] As shown in FIG. 7E, following formation of the openings 56, the conductive members 54 can be formed within the openings 56. The conductive members 34 can comprise a metal, such as the previously described metals for the conductive layers 50. The metal can be deposited within the openings 56 using a deposition process, such as CVD, electrolytic deposition or electroless deposition. A solder metal can be screen printed in the openings 56, as well as with capillary action, or with a vacuum system using a hot solder wave. In addition, the conductive members 54 can be plugs that completely fill the openings 56, or alternately can be layers that cover just the inside surfaces or sidewalls of the openings 56.

[0086] Rather than being a metal, the conductive members 54 can comprise a conductive polymer, such as a metal filled silicone, or an isotropic epoxy. Suitable conductive polymers are sold by A.I. Technology, Trenton, N.J.; Sheldahl, Northfield, Minn.; and 3M, St. Paul, Minn. A conductive polymer can be deposited within the openings 56, as a viscous material, and then cured as required. A suitable deposition process, such as screen printing, or stenciling, can be used to deposit the conductive polymer into the openings 56.

[0087] As also shown in FIG. 7E, the conductive members 54 can include the contact pads 60 formed along the back side 58 of the substrate 42. The pads 60 can have a circular, square, rectangular or other peripheral configuration. As also shown in FIG. 7E, the pads 60 can be formed along a center line coincident to the axis 128 or can be offset from the axis 128.

[0088] The pads 60 can be formed during formation of the conductive members 54 using a suitable mask (not shown), such as a hard mask, or a stencil mask. For example, a metal can be blanket deposited on the back side 58 of the substrate 42 and into the openings 56 and then etched to form the pads 60. Alternately the pads 60 can comprise a different material than the conductive members 54, and can be formed using a separate deposition process.

[0089] FIG. 7E illustrates the completed contacts 46 which are adapted to electrically contact ball contacts 14CSP (FIG. 4D). Optionally as shown in FIG. 7F bumps 62 can be formed on the conductive layer 50 for contacting planar bond pads 16D (FIG. 5D). The bumps 62 can comprise a metal or a conductive polymer deposited as previously described.

[0090] The interconnect 40A (FIG. 5A) can be formed using substantially the same process steps outlined in FIGS. 7A-7F. However, with the substrate 42A comprising a semiconducting material, such as silicon, additional insulating layers 64A can be formed substantially as previously described. In addition, the conductive members 54A (FIG. 5C) can be offset from the contacts 46A by forming the conductors 66A (FIG. 5C) in a required pattern substantially as previously described.

[0091] Thus the invention provides an interconnect for testing semiconductor components contained on a substrate. Also provided are a test system employing the interconnect, and a method for fabricating the interconnect. Although the invention has been described with reference to certain preferred embodiments, as will be apparent to those skilled in the art, certain changes and modifications can be made without departing from the scope of the invention as defined by the following claims.