Phase comparator operable at half frequency of input signal

[0002] 1. Field of the Invention

[0003] The present invention relates to a phase comparator for use in a digital phase locked loop (PLL) circuit.

[0004] 2. Description of the Related Art

[0005] In a serial communication system, in order to surely receive a serial input signal, synchronization between the serial input signal and a clock signal has to be established in a receiver circuit.

[0006] Generally, a digital serial input signal such as a Non Return to Zero (NRZ) signal latently includes a clock signal component which is produced when transmitting the digital serial signal. Therefore, the above-mentioned clock signal is recovered by a PLL circuit using the serial input signal.

[0007] A PLL circuit is usually constructed by a phase comparator for comparing the phase of an input signal with the phase of a clock signal, a loop filter for generating a control voltage in accordance with the output signal of the phase comparator, and a voltage controlled oscillator for controlling the frequency of the clock signal in accordance with the control voltage.

[0008] In a first prior art PLL circuit for recovery of a clock signal from a serial signal, the frequency of a clock signal is about the same as that of the NRZ signal (see: Charles R. {dot over (H)}odge, Jr., “A Self Correcting Clock Recovery Circuit”, IEEE Transactions on Elecron Devices, Vol. ED-32, No. 12, pp. 2704-2706, December 1985). This will be explained later in detail.

[0009] In the above-described first prior art PLL circuit, in order to increase the amount of transmitted data in a serial communication system, the transmission speed of data needs to be increased, which also increases the frequency of the clock signal. However, if the frequency of the clock signal is increased, the performance of a semiconductor device for transmitter/receiver circuits, particularly, the PLL circuit thereof has to be improved. This increases the manufacturing cost.

[0010] In a second prior art PLL circuit for recovery of a clock signal from a serial signal, multiple phased clock signals each having a smaller frequency than that of the serial signal are adopted. Therefore, the speed of transmitted data can be increased without the necessity of improving the semiconductor device for the PLL circuit (see: Chik.Kong Ken Yang et al., “A 0.8μm CMOS 2.5 Gb/s Oversampling Receiver and Transmitter for Serial Links”, IEEE Journal of Solid-State Circuits, Vol. 31, No. 12, December 1996).

[0011] In the above-mentioned prior art PLL circuit, however, if the number of the multiple phased clock signals is increased, it is difficult to accurately control the multiple phased clock signals, and also, a circuit configuration for the multiple phased clock signals is increased in size, which further increases the power dissipation.

[0012] It is an object of the present invention to provide a PILL circuit, particularly, a phase comparator thereof capable of decreasing the size and the power dissipation thereof without the necessity of improving the performance of a semiconductor device therefor.

[0013] According to the present invention, in a phase comparator, a first data fetching circuit fetches an input signal in response to a transition timing of a clock signal having a frequency about half that of the input signal, and a second data fetching circuit fetches the output signal of the first data fetching circuit in response to a transition timing of an inverted signal of the clock signal. A first exclusive OR performs an exclusive OR operation upon the input signal and the output signal of the first data fetching circuit, and a second exclusive OR circuit performs an exclusive OR operation upon the output signals of the first and second data fetching circuits. An inverter inverts the output signal of the first exclusive OR circuit. A first AND circuit performs an AND operation upon the output signal of the second data fetching circuit and the output of the exclusive OR circuit, a second AND circuit performs an AND operation upon the output signal of the first exclusive OR circuit and the output of the first AND circuit to generate a leading signal, and a third AND circuit performs an AND operation upon the output signal of the inverter and the output of the first AND circuit to generate a lagging signal.

[0014] Thus, since the frequency of the clock signal is decreased, it is unnecessary to improve the performance of a semiconductor device for a PILL circuit.

[0015] The present invention will be more clearly understood from the description as set below, as compared with the prior art, with reference to the accompanying drawings, wherein:

[0016] FIG. 1 is a block circuit diagram illustrating a prior art PLL circuit;

[0017] FIG. 2 is a detailed circuit diagram of the phase comparator of FIG. 1;

[0018] FIGS. 3A through 3G are timing diagrams for explaining the operation of the comparator of FIG. 2;

[0019] FIG. 4 is a circuit diagram illustrating an embodiment of the phase comparator according to the present invention;

[0020] FIGS. 5A through 5K are timing diagrams showing the operation of the phase comparator of FIG. 4;

[0021] FIG. 6 is a circuit diagram of a 1 bit to 2 bit converter to which the phase comparator of FIG. 4 is applied; and

[0022] FIGS. 7A through 7E are timing diagrams showing the operation of the 1 bit to 2 bit converter of FIG. 6;

[0023] Before the description of the preferred embodiment, a prior art PLL circuit will be explained with reference to FIGS. 1, 2 and 3A through 3G.

[0024] In FIG. 1, which illustrates a prior art PLL circuit, a PLL circuit is constructed by a phase comparator 1, a loop filter 2, and a voltage controlled oscillator 3.

[0025] The phase comparator 1 compares the phase of an input signal IN with that of a clock signal CLK output from the voltage controlled oscillator 3 to generate a leading signal UP and a lagging signal DOWN.

[0026] The loop filter 2 is formed by a charge pump circuit 21 and a capacitor 22 charged and discharged by the charge pump circuit 21. The charge pump circuit 21 includes a current source 211, a switch 212 turned ON by the leading signal UP, a switch 213 turned ON by the lagging signal DOWN, and a current source 214. That is, when the switch 212 is turned ON, the capacitor 22 is charged by the current source 211 to increase a control voltage V_c. On the other hand, when the switch 213 is turned ON, the capacitor 22 is discharged by the current source 214 to decrease the control voltage V_c.

[0027] The oscillation frequency of the voltage controlled oscillator 3 is controlled by the control voltage V_c.

[0028] In FIG. 2, which is a detailed circuit diagram of the phase comparator 1 of FIG. 1 (see: Charles R. Hodge, Jr., “A Self Correcting Clock Recovery Circuit,” IEEE Transactions on Electron Devices, Vol. ED-32, No. 12, pp. 2704-2706, December 1985), if an input signal IN is an NRZ signal as shown in FIG. 3C, a clock signal CLK has about the same frequency as that of the NRZ signal. A D-type flip-flop 11 fetches the input signal IN in response to a rising edge of the clock signal CLK as shown in FIG. 3A, and a D-type flip-flop 12 fetches the output signal S₁of the D-type flip-flop 11 in response to a falling edge of the clock signal CLK, i.e., a rising edge of an inverted signal of the clock signal CLK as shown in FIG. 3B. The input signal IN and the output signal SI of the D-type flip-flop 11 are supplied to an exclusive OR circuit 13 that generates a leading signal UP as shown in FIG. 3F. Also, the output signal S₁of the D-type flip flop 11 and the output signal S₂of the D-type flip-flop 12 are supplied to an exclusive OR circuit 14 that generates a lagging signal DOWN as shown in FIG. 3G. Note that the output signal S₂of the D-type flip-flop 12 serves as an output data OUT.

[0029] In FIG. 2, note that, a portion indicated by X forms a rising and falling transition detection circuit, and the exclusive OR circuit 13 forms a phase difference determination circuit.

[0030] As shown in FIGS. 3F and 3G, the width of pulses of the leading signal UP is variable, while the width of pulses of the lagging signal DOWN is fixed. The larger the width of pulses of the leading signal UP with respect to the width of pulses of the lagging signal DOWN, the higher the control voltage V_c. On the other hand, the smaller the width of pulses of the leading signal UP with respect to the width of pulses of the lagging signal DOWN, the lower the control voltage V_c.

[0031] In a serial data communication system, in order to increase the amount of transmitted data, the transmission speed needs to be increased, which also increases the frequency of the clock signal CLX. However, if the clock signal CLX is increased, the performance of an integrated semiconductor circuit device for transmitter/receiver circuits, particularly, for a PILL circuit has to be improved, which increases the manufacturing cost.

[0032] In FIG. 4, which illustrates an embodiment of the present invention, in a phase comparator 1′, an inverter 15, and AND circuits 16-18 forming a phase difference determination circuit Y2 is added to the circuit of FIG. 2 forming a falling transition detection circuit. Note that the phase comparator 1′ of FIG. 4 is used instead of the phase comparator 1 in FIG. 1.

[0033] That is, the inverter 15 inverts the output signal S₃of the exclusive OR circuit 13 to generate an output signal S₃. The AND circuit 16 performs an AND operation upon the output signal S₂of the D-type flip-flop 12 and the output signal S₄of the exclusive OR circuit 14 to generate an output signal S₆. The AND circuit 17 performs an AND operation upon the output signal S₃of the exclusive OR circuit 13 and the output signal S₆of the and circuit 16 to generate a leading signal UP. The AND circuit 18 performs an AND operation upon the output signal S₅of the inverter 15 and the output S₆of the AND circuit 16 to generate a lagging signal DOWN.

[0034] In FIG. 4, note that the clock signal CLK of the voltage controlled oscillator 3 (see FIG. 1) has about half of the frequency of the input signal IN.

[0035] The operation of the phase comparator 1′ of FIG. 4 is explained next with reference to FIGS. 5A through 5K.

[0036] The D-type flip-flop 11 fetches the input signal IN as shown in FIG. 5C in response to rising edges of the clock signal CLK as shown in FIG. 5A. In this case, the output signal S₁of the D-type flip-flop 11 is not an NRZ signal, since the frequency of the clock signal CLK is about half of that of the input signal IN.

[0037] The D-type flip-flop 12 fetches the output signal S₁of the D-type flip-flop 11 as shown in FIG. 5D in response to rising edges of an inverted signal of the clock signal CLK as shown in FIG. 5B. That is, as shown in FIGS. 5D and 5E, the output signal S₂of the D-type flip-flop 12 is delayed By half of one period T/2 of the clock signal CLK from the output signal S₁of the D-type flip-flop 11. Note that the output signal S₂of the D-type flip-flop 12 is output as an output signal OUT.

[0038] As shown in FIGS. 5A. 5C and 5F, the output signal S₃of the exclusive OR circuit 13 includes information on phase error between the input signal IN and the clock signal CLK.

[0039] As shown in FIGS. 5D and 5H, the output signal S₄of the exclusive OR circuit 14 shows rising and falling transitions of the output signal S₁of the D-type flip-flop 11.

[0040] As shown in FIGS. 5D and 5I, the output signal S₆of the AND circuit 16 shows falling transitions of the output signal S₁of the D-type flip-flop 11.

[0041] As shown in FIGS. 5F, 5I and 5J, the AND circuit 17 performs an AND operation upon the output signal S₃of the exclusive OR circuit 13 with the output signal S₆of the AND circuit 16, to generate the leading signal UP. That is, only a phase error component is taken out of the output signal S₃of the exclusive OR circuit 13.

[0042] As shown in FIGS. 5G, 5I and 5K, the AND circuit 18 performs an AND operation upon the output signal S₅of the inverter 15 with the output signal S₆of the AND circuit 16, to generate the lagging signal DOWN. In more detail, a period “a” of the signal S₁in FIG. 5D consists of an input signal component as indicated by “b” and a phase error component as indicated by “c” in FIG. 5F. Note that this phase error component “c” exists only in falling transition periods of the output signal S₁of the D-type flip-flop 11. Therefore, such falling transitions are generated by the output signal S₆of the AND circuit 16 of FIG. 5I.

[0043] Also, as indicated by “1” and “2” in FIGS. 5J and 5K, the pulse width of the leading signal UP is different from that of the lagging signal DOWN. In this case, if jitter occurs in the clock signal CLK, correct data is hardly fetched.

[0044] On the other hand, as indicated by “3” in FIGS. 5J and 5K, the pulse width of the leading signal UP is the same as that of the lagging signal DON. In this case, even if jitter occurs in the clock signal CLX, correct data can be fetched, because the input signal IN synchronizes with the clock signal CLK, so that the clock signal CLK transits at centers of NRZ data. Therefore, the NRZ signal can be surely recognized.

[0045] Thus, in the phase comparator 1′ of FIG. 4, even when one of the input signals is an NRZ signal and the other is a clock signal having about half the frequency of the NRZ signal, a phase comparison therebetween is possible. Therefore, if a PILL circuit of FIG. 1 is constructed by using the phase comparator 1′ of FIG. 4, a clock signal in synchronization with an input signal can be extracted from the PLL circuit.

[0046] FIG. 6 illustrates a 1 bit to 2 bit converter to which the phase comparator of FIG. 4 is applied. That is, a D-tipe flip-flop 11ais added to the elements of FIG. 4. Note that a phase comparator 1″ of FIG. 6 is used instead of the phase comparator 1 in FIG. 1.

[0047] In FIG. 6, the D-type flip-flop lha fetches the input signal IN (which is a serial data signal) in response to falling edges of the clock signal CLK as shown in FIG. 7A, i.e., rising edges of an inverted signal of the clock signal CLK as show in FIG. 7B. That is, the clock timing of the D-type flip-flop 11 is shifted from that of the D-type flip-flop 11aby a half period (T/2) of the clock signal CLK. The output signal of the D-type flip-flop 12 and the output signal of the D-type flip-flop 11aconstitute two parallel data bits D₁and D₂, respectively.

[0048] The D-type flip-flops 11, 12 and 11aform a data retention circuit. A plurality of data retention circuits, each of which comprises the D-type flip-flops 11, 12 and 11a, have different phases relative to each other.

[0049] Thus, the serial input signal In as shown in FIG. 7C is converted into the two parallel output signals D₁and D₂as shown in FIGS. 7D and 7E, respectively.

[0050] As explained hereinabove, a phase comparator according to the present invention can surely compare an input signal with a clock signal whose frequency is about half that of the input signal. Therefore, it is unnecessary to improve the performance of a semiconductor device for a PLL circuit including the phase comparator, which also decreases the size and power dissipation thereof.