Fabrication method of semiconductor memory device with impurity regions surrounding recess

[0002] This application is a Divisional of application Ser. No. 08/773,510 filed Dec. 23, 1996, now U.S. Pat. No. 5,990,529.

[0003] 1. Field of the Invention

[0004] The present invention relates to a semiconductor memory device and a fabrication method thereof, and in particular, to an improved semiconductor memory device and a fabrication method thereof which is capable of achieving a lightly doped drain (LDD) construction and reducing a parasitic capacitance generated between an impurity area and a word line by forming a trench in a portion of a semiconductor substrate and forming an impurity area around the trench.

[0005] 2. Description of the Prior Art

[0006] FIG. 1 is a plan view of a layout of a semiconductor memory device according to the conventional art, and FIG. 2 is a longitudinal cross-sectional view of the semiconductor memory device in FIG. 1. As shown in these drawings, a semiconductor substrate 1 is formed having a plurality of (N+) impurity areas (2s, 2d) on the upper portion thereof 1, and on the plurality of impurity areas (N+) (2s, 2d), a gate oxide film 3 is formed. On the gate oxide film 3, a plurality of polysilicon lines 4 are sequentially formed. The polysilicon lines 4 which serve as word lines are formed to cross the plurality of (N+) impurity areas (2s, 2d). And, a polysilicide layer 5 is formed on the polysilicons 4.

[0007] In the above-described semiconductor memory device according to the conventional art, since as many capacitors as the (N+) impurity areas (2s,2d) (which are parasitic capacitors) are formed between the (N+) impurity areas (2s,2d) and the polysilicon lines 4 formed on the semiconductor substrate 1, the delay time of the word lines is disadvantageously increased due to the parasitic capacitors, and it is difficult to reduce the size of a cell due to a lateral diffusion of the (N+) impurity areas (2s,2d). Furthermore, since the (N+) impurity areas (2s,2d) serve as the source and drain of a transistor, a semiconductor memory device having the LDD construction is impossible to fabricate.

[0008] Accordingly, it is an object of the present invention to provide an improved semiconductor memory device and a fabrication method thereof which is capable of lessening the parasitic capacitance formed due to polysilicon and (N+) impurity areas.

[0009] It is another object of the present invention to provide an improved semiconductor memory device and a fabrication method thereof which is capable of fabricating a semiconductor memory device having an LDD construction.

[0010] It is still another object of the present invention to provide an improved semiconductor memory device and a fabrication method thereof which is capable of reducing the size of a memory cell of a semiconductor device by preventing a lateral diffusion of an impurity area on a semiconductor substrate.

[0011] To achieve the above object, there is provided an improved semiconductor memory device which includes a semiconductor substrate, a plurality of trenches formed in the semiconductor substrate, first impurity areas formed along the outer surfaces of each of the plurality of trenches, second impurity areas formed under a bottom surfaces of each first impurity area along the outer surfaces of the trenches, an insulating film filled in each trench, a gate insulating film formed at a regular interval on the substrate having the insulating film filled in the trench, and a gate electrode formed on the gate insulating film.

[0012] To achieve the above object, there is provided an improved fabrication method for a semiconductor memory device which includes the steps of forming a plurality of trenches in a semiconductor substrate, forming a first impurity area around each trench, forming a second impurity area beneath each first impurity area, filling the trenches with an insulating film, forming a gate insulating film at a regular interval on the substrate having the insulating film filled in the trenches, and forming a gate electrode on the gate insulating film.

[0013] The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:

[0014] FIG. 1 is a plan view of a layout of a semiconductor memory device according to the conventional art;

[0015] FIG. 2 is a longitudinal cross-sectional view of the semiconductor memory device in FIG. 1 according to the conventional art;

[0016] FIG. 3 is a plan view of a semiconductor memory device according to the present invention;

[0017] FIG. 4 is a longitudinal cross-sectional view of the semiconductor memory device in FIG. 3 according to the present invention; and

[0018] FIGS. 5A through 5H are views showing a fabrication method for a semiconductor memory device according to the present invention.

[0019] FIG. 3 is a plan view of a semiconductor memory device according to the present invention. As shown in this drawing, bit lines 16 and word lines 22 are formed in the trenches on a semiconductor substrate 11.

[0020] FIG. 4 is a longitudinal cross-sectional view of the semiconductor memory device in FIG. 3. As shown in this drawing, the semiconductor memory device includes a first conductive semiconductor substrate 11, a plurality of trenches 14 formed in the semiconductor substrate 11, first impurity areas 16 formed along the outer surfaces of each of the plurality of trenches 14, second impurity areas 17 formed under the outer bottom surfaces of the first impurity areas 16, a first CVD oxide film 18 formed on the inside walls and the inner lower surface in the trenches 14, an SOG (spin on glass) layer 19 filled in the first oxide film 18 in the trench 14, a second CVD oxide film 20 formed on the SOG layer 19, a gate oxide film 21 formed at a regular interval on the semiconductor substrate 11 having the second oxide film 18, and a conductive layer serving as a gate electrode formed on the gate oxide film.

[0021] The conductive layer is formed by the sequential deposition of a polysilicon 22 and a polysilicide 23.

[0022] FIGS. 5A through 5H show a fabrication method for the semiconductor memory device in FIG. 4, and the fabrication steps will now be described in detail.

[0023] First, as shown in FIGS. 5A and 5B, a relief oxide film 12 which is to serve as an insulating layer is deposited to have a thickness of about 400 Å on the first conductive semiconductor substrate 11, and then a nitride film 13 is deposited to have a thickness of about 1600 Å by a low pressure chemical vapor deposition (LPCVD). Then, by a photolithography process, an insulating layer including the nitride film 13 and the oxide film 12 is patterned to expose a predetermined portion of the semiconductor substrate, and a plurality of trenches 14 are formed by etching the semiconductor substrate 11, using the patterned insulating layer as a mask.

[0024] Next, as shown in FIGS. 5C and SD, after a CVD PSG (phosphorous silicate glass) (n−) 15 is deposited to cover the entire resultant uneven surface formed by the above process, an annealing is performed on the resultant structure at the temperature of about 800˜1000° C. so that phosphorus is diffused into the semiconductor substrate 11 to form the first impurity area (n−) 16 along the outer outline of the trenches 14. Then, after the CVD PSG film 15 is stripped, an (n+) (5×10¹⁵) inpurity is implanted by 0° tilting, using the insulating layer as a mask, so that the second impurity area (n+) 17 is formed beneath the first impurity area (n−) 16.

[0025] Next, as shown in FIGS. 5E and 5F, after the nitride film 13 which serves as an insulating layer is stripped, a first CVD oxide film 18 is deposited to have a thickness of about 1000 Å to cover the entire resultant surface formed by the above process. By coating the resultant surface with an SOG(spin on glass) for a planarization and curing the same at a temperature of 650° C., an SOG layer 19 is formed in such a manner that the entire surface is covered and the trenches 14 are filled, and then the SOG layer 19 is etched back so that the SOG layer 19 remains on the first oxide film 18 inside the trenches 14. A second CVD film 20 is deposited to have a thickness of 2000 Å on the first CVD film 18, including the upper surface of the remaining SOG layer 19.

[0026] Next, as shown in FIGS. 5G and 5H, the first and second CVD oxide films 18,20 are etched back, and then about 100˜150 Å of the gate oxide film 21, about 1000˜2500 Å of the polysilicon layer 22 which serves as a gate electrode and about 1000˜2000 Å of the polysilicide(WSi₂) layer 23 are sequentially deposited.

[0027] As described above, in the semiconductor memory device according to the present invention, by forming the respective impurity areas(n−,n+) in the semiconductor substrate, the fabrication of the semiconductor memory device having an LDD construction can be achieved.

[0028] Therefore, the present invention has the advantages as follows:

[0029] The reduction of the size of the semiconductor memory device can be accomplished since the lateral diffusion of impurities is decreased in comparison with the conventional device.

[0030] A parasitic capacitance and the delay time of the word lines can be reduced since a thick insulating layer is formed between the polysilicon lines(word line) and the impurity areas.

[0031] Although the preferred embodiments of the present invention have been disclosed for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as recited in the accompanying claims.