Method of fabricating a bottom electrode

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor fabrication method. More particularly, the present invention relates to a method of fabricating a bottom electrode.

[0004] 2. Description of the Related Art

[0005] As the integration of the semiconductor devices increases and the linewidth thereof decreases, it becomes desirable to form more semiconductor devices in a limited area. Due to limitations imposed by the fabrication process, it is difficult to achieve a highly integrated circuit. In addition, because difficulties exist in forming a highly integrated device, it is hard to ensure the reliability of the device. Therefore, how to fabricate highly integrated semiconductor devices has became the main topic of the recent research on semiconductor fabrication at the 0.13 micron level.

[0006] FIG. 1 is a schematic, cross-sectional view illustrating a conventional method of forming a bit line and a bottom electrode.

[0007] A metal oxide semiconductor (MOS) is formed on the substrate 100. The MOS includes a gate 102 on the substrate 100, a spacer 104 on the sidewall of the gate 102 and the source/drain region 106 in the substrate 100 beside the gate 102. A dielectric layer 108 is formed over the substrate 100 to cover the MOS. A bit line 110 is formed through the dielectric layer 108 to electrically couple with the source/drain region 106. A dielectric layer 112 is formed over the substrate 100 to cover the bit line 110. A bottom electrode 114 is formed through the dielectric layers 108 and 112 to electrically couple with the source/drain region 106.

[0008] In the conventional method, devices, such as bit line 110 and the bottom electrode 114 are separated from each other. Consequently, the integration of the semiconductor circuit cannot be effectively increased. Thus, there is a need to further increase the integration of semiconductor devices.

[0009] In addition, due to the fabrication limitation for forming semiconductor devices in a limited area, box-shaped capacitors are usually formed. However, the conventional box-shaped capacitor cannot provide sufficient capacitance. Thus, the capacitance of the conventional capacitor is limited.

[0010] The invention provides a method of fabricating a bottom electrode. A first dielectric layer having a first opening is formed over a substrate. The first opening exposes a portion of a conductive layer in the substrate. A first liner layer is formed on a sidewall of the first opening. A conductive plug is formed in the opening. A plurality of bit lines is formed next to the first opening. A second liner layer is formed over the substrate to cover the bit lines, the first liner layer, and the conductive plug. A node contact opening is formed in the second liner layer to expose a portion of the conductive plug. A second dielectric layer is formed over the substrate. A second opening is formed in the second dielectric layer to expose the node contact opening and a portion of the second liner layer. A conformal conductive layer is formed in the opening.

[0011] In contrast with the conventional method, which has devices separated from each other, the devices of the present invention are next and closer to each other. Thus, the integration of the semiconductor devices fabricated by the present invention is effectively increased. In addition, since the first liner layer and the second liner layer are used to isolate the bit lines from the bottom electrode, the reliability of the devices is enhanced.

[0012] In addition, because of the liner layers provide isolation between the bottom electrode and the bit line, the opening for forming the bottom electrode overlaps with the bit line when viewed from the top. Thus, the opening for forming the bottom electrode can be wider than the conductive plug. The surface area of the bottom electrode is thus further increased.

[0013] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

[0014] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,

[0015] FIG. 1 is a schematic, cross-sectional view illustrating a conventional method of forming a bottom electrode and a bit line.

[0016] FIGS. 2A through 2E are schematic, cross-sectional views illustrating a method of fabricating a bottom electrode according to one preferred embodiment of the invention.

[0017] Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0018] FIGS. 2A through 2E are schematic, cross-sectional views illustrating a method of fabricating a bottom electrode according to one preferred embodiment of the invention.

[0019] Referring to FIG. 2A, a substrate 200 having a conductive layer 202 therein is provided. The conductive layer 202 can be, for example, a source/drain region of a MOS or a conductive line. A dielectric layer 204 is formed over the substrate 200 by, for example, chemical vapor deposition. The material for the dielectric layer 204 includes oxide, tetra-ethyl-ortho-silicate (TEOS), borophosphosilicate glass (BPSG), or phosphosilicate glass (PSG). An opening 206 is formed in the dielectric layer 204 to expose a portion of the conductive layer 202. A liner layer 208 is formed on the sidewall of the opening 206. The thickness of the liner layer 208 is preferably about 100 angstroms to about 500 angstroms. A conductive plug 210 is formed in the opening 206. The liner layer 208 and the conductive plug 210 can be formed by the following exemplary steps. A conformal liner layer (not shown) is formed over the substrate 200 by, for example, plasma-enhanced chemical vapor deposition or deposition in a furnace. A photolithographic and etching process is performed to remove the conformal liner layer at the bottom of the opening 206. A conductive layer (not shown), such as polysilicon, is formed over the substrate 200 to fill the opening 206. A removing step, such as a chemical-mechanical polishing, is performed. The conductive layer and the conformal liner layer are removed until the dielectric layer 204 is exposed. The liner layer 208 and the conductive plug 210 as shown in the figure are thus formed.

[0020] Referring to FIG. 2B, the dielectric layer 204 is patterned to form bit line openings 212aand 212bnext to the opening 206. The bit line openings 212aand 212bexposes the liner layer 208. The dielectric layer 204 can be patterned by, for example, a photolithographic and etching process. In the photolithographic and etching process, the etchant has a high etching selectivity between the dielectric layer 204 and the liner layer 208. Specifically, the etching rate of the dielectric layer 204 is higher than the etching rate of the liner layer 208. For example, in the case that the material of the dielectric layer 204 is oxide, the liner layer 208 is a silicon nitride layer.

[0021] Referring to FIG. 2C, a metal material is filled in the bit line openings 212aand 212bto form bit lines 214aand 214b. The bit lines 214aand 214bcan be formed by, for example, depositing a metal material over the substrate 200 to fill the bit line openings 212aand 212bfollowed by performing a chemical-mechanical polishing step to remove the metal material until the dielectric layer 204 is exposed. In this preferred embodiment, there are two bit lines 212aand 212bparallel to each other when viewed from the top. In addition, the metal material filling in the bit line openings 212aand 212bhas a low resistance. Preferably, the metal material is tungsten, although other metal material having a low resistance can be used.

[0022] A liner layer 216 is formed over the substrate 200 to cover the bit lines 214aand 214b, the liner layer 208, and the conductive plug 210. The liner layer 216 preferably has a thickness of about 100 angstroms to about 500 angstroms and is formed by, for example, plasma-enhanced chemical-vapor deposition or deposition in a furnace. A node contact opening 218 is formed in the liner layer 216 to expose a portion of the conductive plug 210. The material of the liner layer 216 can be, for example, silicon nitride.

[0023] Referring to FIG. 2D, a dielectric layer 220 is formed over the substrate 200 by, for example, chemical vapor deposition. The dielectric layer 220 preferably has a thickness of about 8000 angstroms to about 10000 angstroms. The dielectric layer 220 includes an oxide layer, a tetra-ethyl-ortho-silicate (TEOS) layer, a borophosphosilicate glass (BPSG) layer, or a phosphosilicate glass (PSG) layer. An opening 222 is formed in the dielectric layer 220 to align with the conductive plug 210. The opening 222 exposes the node contact opening 218 and a portion of the liner layer 214. The opening 222 can be formed by, for example, a photolithographic and etching process. The etchant of the photolithographic and etching process has a high etching selectivity between the liner layer 216 and the dielectric layer 220. In this manner, the etching step is performed using the liner layer 214 as an etching stop. For example, in the case that the material of the dielectric layer 220 is oxide, the liner layer 214 is a silicon nitride layer.

[0024] Reference is made to FIG. 2E, which shows a formation of a bottom electrode. A conformal conductive layer 224 is formed in the opening 222. The thickness of the conformal conductive layer 224 is about 300 angstroms to about 500 angstroms. In order to further increase the surface area of the bottom electrode, a hemispherical-grained silicon (HSG) layer 226 is preferably formed on the conformal conductive layer 224.

[0025] The present invention increases the integration of the semiconductor circuit by forming the bit lines 214aand 214band the bottom electrode next to each other. Thus, the integration of the semiconductor devices is effectively increased. In addition, since the liner layers 208 and 216 are used to isolate the bit lines 214aand 214bfrom the bottom electrode, the reliability of the devices is enhanced. Moreover, because of the liner layers 208 and 216 provide isolation between the bottom electrode and the bit lines 214aand 214b, the opening 222 for forming the bottom electrode overlaps with the bit lines 214aand 214bwhen viewed from the top. Thus, the opening size can be increased according to the design requirement. The surface area of the bottom electrode thus is further increased.

[0026] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure and the method of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.