Television apparatus, display method of television apparatus and picture plane control apparatus, and method

[0002] This is a continuation of copending International Application PCT/JP98/05140 having an international filing date of Nov. 16, 1998.

[0003] The invention relates to a television apparatus for displaying picture-in-picture or picture-and-picture in which a first picture plane and a second picture plane can be displayed, a display method of such a television apparatus, and picture plane control apparatus and method.

[0004] FIG. 8 shows a block diagram for performing what is called a picture-in-picture (hereinafter, referred to as a PinP) in which a slave picture plane is displayed in a conventional master picture plane. In the block diagram shown in FIG. 8, a scaling and a display position of the slave picture plane are set through a field memory 134. Parameters of a writing range (HAct, VAct) and a reading range (HSize, VSize) are supplied to a divider 131. The writing range (HAct, VAct) is a fixed value. In the divider 131, a ratio of magnification or reduction is set. In a horizontal interpolating circuit 132 and a vertical interpolating circuit 133, when the reduction ratio is supplied from the divider 131, an interpolation in the horizontal and vertical directions is performed to an image inputted on the basis of the ratio.

[0005] The image supplied from the vertical interpolating circuit 133 is written into the field memory 134 on the basis of a control signal which is supplied from a write memory control circuit 137. A horizontal sync signal, a vertical sync signal, and parameters of a write start position (HPhase, VPhase) and the writing range (HAct, VAct) of a fixed value are supplied to the write memory control circuit 137. Those parameters have a relation shown in FIG. 9. An image surrounded by the writing range (HAct, VAct) of the fixed value is written into the field memory 134.

[0006] The written image is read out from the field memory 134 on the basis of a control signal which is supplied from a read memory control circuit 138. The horizontal sync signal, the vertical sync signal, and parameters of a read start position (HPosition, VPosition) and the reading range (HSize, VSize) are supplied to the read memory control circuit 138. Those parameters have a relation shown in FIG. 10. The image written in the field memory 134 is read out so as to be displayed in a range surrounded by the reading range (HSize, VSize).

[0007] In a horizontal interpolating circuit 135 and a vertical interpolating circuit 136, when the magnification ratio is supplied from the divider 131, an interpolation in the horizontal and vertical directions is performed to an image supplied on the basis of such a ratio.

[0008] It is a feature of PinP that the writing range (HAct, VAct) which is set to the field memory 134 is set to a fixed value on the assumption that the operation to magnify or reduce the whole picture plane is performed. A display picture plane size is determined by only the setting of the reading range (HSize, VSize). FIGS. 9 and 10 show relations between the parameters for the write memory control circuit 137, read memory control circuit 138, and divider 131 and the horizontal and vertical sync signals. As shown in FIG. 9, upon writing, only the write start position (HPhase, VPhase) becomes the parameter. Upon reading shown in FIG. 10, the position and size are set by the parameters of the read start position (HPosition, VPosition) and the reading range (HSize, VSize). An actual display picture plane of PinP is shown in FIG. 11. As shown in FIG. 11, in the conventional PinP, a slave picture plane 142 obtained by reducing an almost whole picture plane of a program on a different channel is displayed in the master picture plane 141.

[0009] However, in case of PinP, since almost whole picture plane is reduced and displayed as a slave picture plane, there is a problem such that small characters cannot be discriminated or a small person cannot be recognized. For example, when a relay of a baseball game or a soccer game is displayed on the slave picture plane, a problem such that the score cannot be discriminated occurs.

[0010] Further, in case of what is called a picture-and-picture (hereinafter, referred to as a P&P) in which a picture plane 146 is displayed adjacently to a picture plane 145 shown in FIG. 12, when a letter box signal is displayed, there is a problem such that upper and lower black edges are displayed in a frame of the picture plane 146. This is a problem such that the frame which does not correspond to the inherent aspect ratio is displayed in the picture plane.

[0011] It is, therefore, an object of the invention to provide a television apparatus in which in a display of PinP or P&P, the portion of an image of an arbitrary size at an arbitrary position in an image of a program on a different channel or an image of another input signal is displayed in the second picture plane, a display method of such a television apparatus, and picture plane control apparatus and method.

[0012] According to the invention, there is provided a television apparatus for displaying a first picture plane and a second picture plane onto a same picture plane, characterized in that the apparatus has signal processing means for magnifying or reducing an input signal of a program on a different channel or an input signal other than a signal displayed at present on the first picture plane and the magnified or reduced input signal is displayed in the second picture plane.

[0013] According to the invention, there is provided a display method of a television apparatus for displaying a first picture plane and a second picture plane onto a same picture plane, characterized by comprising the steps of: magnifying or reducing an input signal of a program on a different channel or an input signal other than a signal displayed at present on the first picture plane; and displaying the magnified or reduced input signal onto the second picture plane.

[0014] According to the invention, there is provided a picture plane control apparatus for displaying an inputted signal onto a picture plane, characterized by comprising: dividing means for discriminating a magnification or a reduction of the signal; a memory into/from which the signal can be written and read out; write control means for writing a desired area of the signal into the memory; and read control means for allowing the signal written in the memory to be displayed at a desired position.

[0015] According to the invention, there is provided a picture plane control method of displaying an inputted signal onto a picture plane, characterized by comprising the steps of: discriminating a magnification or a reduction of the signal by dividing means; writing a desired area of the signal into a memory; and allowing the signal written in the memory to be displayed at a desired position on the picture plane.

[0016] When the inputted image is written into a field memory, a writing range (HAct, VAct) can be varied. Thus, in a slave picture plane of PinP, by displaying only necessary information of an arbitrary portion of the image such as small characters, small person, or the like which cannot be discriminated, it can be discriminated. In the first and/or the second picture plane of P&P, the upper and lower black edge portions of a letter box signal are removed and the image can be displayed at an inherent aspect ratio.

[0017] FIG. 1 is a block diagram showing an embodiment of a television receiver to which the invention is applied;

[0018] FIG. 2 is a block diagram of an embodiment of the invention;

[0019] FIG. 3 is a schematic diagram for use in explanation upon writing that is applied to the invention;

[0020] FIG. 4 is a schematic diagram for use in explanation upon reading that is applied to the invention;

[0021] FIG. 5 shows an example of a picture plane of a picture-in-picture to which the invention is applied;

[0022] FIG. 6 shows an example of a picture plane of a picture-and-picture to which the invention is applied;

[0023] FIGS. 7A and 7B are schematic diagrams for explaining a writing range which is applied to the invention;

[0024] FIG. 8 is a block diagram of a conventional picture-in-picture;

[0025] FIG. 9 is a schematic diagram for use in explanation upon writing;

[0026] FIG. 10 is a schematic diagram for use in explanation upon reading;

[0027] FIG. 11 is a schematic diagram of a picture plane of the conventional picture-in-picture; and

[0028] FIG. 12 is a schematic diagram of a picture plane of a conventional picture-and-picture.

[0029] An embodiment of the invention will now be described hereinbelow with reference to the drawings. FIG. 1 shows an example of a television receiver to which the invention is applied. In the television receiver to which the invention is applied, PinP can be set.

[0030] In FIG. 1, reference numerals 1 and 2 denote antennas. Signals from a television broadcasting station are received by the antennas 1 and 2. The reception signal from the antenna 1 is supplied to a terminal 3A of an antenna switch 3 and to a terminal 4A of an antenna switch 4. The reception signal from the antenna 2 is supplied to an input terminal 3B of the antenna switch 3 and to an input terminal 4B of the antenna switch 4. An output of the antenna switch 3 is supplied to a tuner circuit 5. An output of the antenna switch 4 is supplied to a tuner circuit 6.

[0031] The antenna switch 3 switches a signal which is inputted to the tuner circuit 5 between the reception signal from the antenna 1 and the reception signal from the antenna 2. When the antenna switch 3 is set to the terminal 3A side, the reception signal from the antenna 1 is supplied to the tuner circuit 5 via the antenna switch 3. When the antenna switch 3 is set to the terminal 3B side, the reception signal from the antenna 2 is supplied to the tuner circuit 5 via the antenna switch 3.

[0032] The antenna switch 4 switches a signal which is inputted to the tuner circuit 6 between the reception signal from the antenna 1 and the reception signal from the antenna 2. When the antenna switch 4 is set to the terminal 4A side, the reception signal from the antenna 1 is supplied to the tuner circuit 6 via the antenna switch 4. When the antenna switch 4 is set to the terminal 4B side, the reception signal from the antenna 2 is supplied to the tuner circuit 6 via the antenna switch 4.

[0033] The tuner circuit 5 is a main tuner circuit for a master picture plane. A desired reception channel to be displayed on the master picture plane is selected by the tuner circuit 5. The reception signal is converted into an intermediate frequency signal and supplied to an intermediate frequency and video detecting circuit 7.

[0034] The tuner circuit 6 is a sub tuner circuit for a slave picture plane. A desired reception channel to be displayed on the slave picture plane is selected by the tuner circuit 6. The reception signal is converted into an intermediate frequency signal and supplied to an intermediate frequency and video detecting circuit 8.

[0035] A channel setting signal is supplied from a controller 10 to the tuner circuits 5 and 6. By the tuner setting signal, the channels of the tuner circuits 5 and 6 are set. Information regarding the channels has been stored in a memory 49.

[0036] As mentioned above, in the television receiver to which the invention is applied, the two tuner circuits of the main tuner circuit 5 and sub tuner circuit 6 are provided and the different channels can be set for the master picture plane and the slave picture plane by the tuner circuits 5 and 6.

[0037] The intermediate frequency signal from the main tuner circuit 5 for the master picture plane is amplified and a video signal is detected by the intermediate frequency and video detecting circuit 7. Thus, a composite color video signal of, for example, the NTSC system to form the master picture plane is demodulated. The composite color video signal is supplied to a terminal 13A of the switching circuit 13 of the video source change-over switch 12 and supplied to a terminal 14C of the switching circuit 14.

[0038] The intermediate frequency signal from the sub tuner circuit 6 for the slave picture plane is amplified and a video signal is detected by the intermediate frequency and video detecting circuit 8. Thus, a composite color video signal of, for example, the NTSC system to form the slave picture plane is demodulated. The composite color video signal is supplied to a terminal 14A of the switching circuit 14 of the video source change-over switch 12 and supplied to a terminal 13C of the switching circuit 13.

[0039] An audio intermediate frequency signal is extracted from a beat component of, for example, 4.5 MHz by the intermediate frequency and video detecting circuit 7. The audio intermediate frequency signal is supplied to an audio decoder 11. An audio signal is demodulated by the audio decoder 11. The audio signal from the audio decoder 11 is supplied to a terminal 15A of an audio source change-over switch 15.

[0040] The television receiver to which the invention is applied has an external video input terminal 16 and an external audio input terminal 17. A composite color video signal from the outside is supplied to the external video input terminal 16 and an audio signal from the outside is supplied to the external audio input terminal 17.

[0041] The video signal from the external video input terminal 16 is supplied to a terminal 13B of the switching circuit 13 of the video source change-over switch 12 and to a terminal 14B of the switching circuit 14. The audio signal from the external audio input terminal 17 is supplied to a terminal 15B of the audio source change-over switch 15.

[0042] The video source change-over switch 12 switches video sources on the basis of a switch control signal from the controller 10. The video source change-over switch 12 has the switching circuit 13 to select the video signal to be displayed on the master picture plane and the switching circuit 14 to select the video signal to be displayed on the slave picture plane.

[0043] The video signal to be displayed on the master picture plane is outputted from an output terminal 13D of the switching circuit 13 of the video source change-over switch 12. The video signal to be displayed on the slave picture plane is outputted from an output terminal 14D of the switching circuit 14.

[0044] The switching circuit 13 of the video source change-over switch 12 is switched to the terminal 13A side in the case where the picture plane based on the video signal of the channel set by the main tuner circuit 5 is displayed on the master picture plane, switched to the terminal 13B side in the case where the picture plane based on the video signal from the external video input terminal 16 is displayed on the master picture plane, and switched to the terminal 13C side in the case where the picture plane based on the video signal of the channel set by the sub tuner circuit 6 is displayed on the master picture plane.

[0045] The switching circuit 14 of the video source change-over switch 12 is switched to the terminal 14A side in the case where the picture plane based on the video signal of the channel set by the sub tuner circuit 6 is displayed on the slave picture plane, switched to the terminal 14B side in the case where the picture plane based on the video signal from the external video input terminal 16 is displayed on the slave picture plane, and switched to the terminal 14C side in the case where the picture plane based on the video signal of the channel set by the main tuner circuit 5 is displayed on the slave picture plane.

[0046] The audio source change-over switch 15 switches audio sources on the basis of a switch control signal from the controller 10. An output of the audio source change-over switch 15 is supplied to an audio amplifier 18. An output of the audio amplifier 18 is supplied to a speaker 19.

[0047] The audio source change-over switch 15 is switched to the terminal 15A side in case of outputting the audio sound based on the audio signal of the channel set by the main tuner circuit 5 and switched to the terminal 15B side in case of outputting the audio sound based on the audio signal from the external audio input terminal 17.

[0048] The video signal of the master picture plane which is outputted from the output terminal 13D of the switching circuit 13 of the video source change-over switch 12 is supplied to a Y/C separating circuit 21. The video signal of the slave picture plane which is outputted from the output terminal 14D of the switching circuit 14 is supplied to a Y/C separating circuit 22.

[0049] The Y/C separating circuit 21, a luminance signal processing circuit 23, a chroma signal processing circuit 25, an image processing circuit 29, and a matrix circuit 24 generate three primary color signals R, G, and B to be displayed on the master picture plane.

[0050] That is, the video signal of the master picture plane is separated into a luminance signal Y and a chroma signal C by the Y/C separating circuit 21. The luminance signal Y from the Y/C separating circuit 21 is supplied to the luminance signal processing circuit 23. In the luminance signal processing circuit 23, picture quality adjustments such as luminance adjustment, brightness adjustment, and the like are executed.

[0051] The chroma signal C from the Y/C separating circuit 21 is supplied to the chroma signal processing circuit 25. In the chroma signal processing circuit 25, a burst signal is extracted from the reception signal and color difference signals I and Q are demodulated by using the burst signal. In the chroma signal processing circuit 25, an ACC (Automatic Color Control), a frequency characteristics correction, and the like are performed.

[0052] The luminance signal Y from the luminance signal processing circuit 23 and the color difference signals I and Q from the chroma signal processing circuit 25 are supplied to the image processing circuit 29. The image processing circuit 29 is an essence of the invention. As will be explained hereinlater, in the image processing circuit 29, processes are performed to the luminance signal Y and color difference signals I and Q. In the image processing circuit 29, a signal of the master picture plane to be displayed on the master picture plane is formed. The signal of the master picture plane is supplied to the matrix circuit 24. By the matrix circuit 24, three primary color signals R, G, and B for the master picture plane are formed by the luminance signal Y and color difference signals I and Q.

[0053] The Y/C separating circuit 22, a luminance signal processing circuit 26, a chroma signal processing circuit 27, an image processing circuit 28, and a matrix circuit 30 are used to form the slave picture plane and are called a PinP circuit.

[0054] That is, the video signal of the slave picture plane is separated into a luminance signal Y and a chroma signal C by the Y/C separating circuit 22. The luminance signal from the Y/C separating circuit 22 is supplied to the luminance signal processing circuit 26. The chroma signal C is supplied to the chroma signal processing circuit 27. In the chroma signal processing circuit 27, a burst signal is extracted from the reception signal and the color difference signals I and Q are demodulated by using the burst signal.

[0055] The luminance signal Y from the luminance signal processing circuit 26 and the color difference signals I and Q from the chroma signal processing circuit 27 are supplied to the image processing circuit 28. In a manner similar to the foregoing image processing circuit 29, the image processing circuit 28 is an essence of the invention. As will be explained hereinlater, in the image processing circuit 28, processes are performed to the luminance signal Y and color difference signals I and Q. In the image processing circuit 28, a signal of the slave picture plane to be displayed on the slave picture plane is formed. The signal of the slave picture plane is supplied to the matrix circuit 30. By the matrix circuit 30, three primary color signals R, G, and B for the slave picture plane are formed by the luminance signal Y and color difference signals I and Q.

[0056] The three primary color signals R, G, and B of the master picture plane from the matrix circuit 24 and the three primary color signals R, G, and B of the slave picture plane from the matrix circuit 30 are supplied to a synthesizing circuit 31. In the synthesizing circuit 31, the three primary color signals R, G, and B of the master picture plane and the three primary color signals R, G, and B of the slave picture plane are synthesized.

[0057] An output of the synthesizing circuit 31 is supplied to an adding circuit 32 of a display signal. A display signal is supplied from a display generating circuit 51 to the adding circuit 32. An output of the adding circuit 32 is supplied to an image receiving tube 33.

[0058] The video signal of the master picture plane is supplied to a sync generating circuit 35 via the output terminal 13D of the switching circuit 13. The video signal of the slave picture plane is supplied to the sync generating circuit 35 via the output terminal 14D of the switching circuit 14. Horizontal and vertical sync signals are extracted by the sync generating circuit 35. The horizontal sync signal extracted by the sync generating circuit 35 is supplied to a horizontal oscillating circuit 36. The vertical sync signal extracted by the sync generating circuit 35 is supplied to a vertical oscillating circuit 44.

[0059] A horizontal pulse synchronized with the horizontal sync signal from the sync generating circuit 35 is formed by the horizontal oscillating circuit 36. The horizontal pulse is supplied to a horizontal output circuit 38 via a horizontal driving circuit 37. A horizontal saw-tooth wave current is supplied to a horizontal deflecting coil of the image receiving tube 33 by the horizontal output circuit 38.

[0060] At this time, a flyback pulse is generated for a blanking period of the saw-tooth wave. The flyback pulse is fed back to the horizontal oscillating circuit 36. The feedback pulse and an output of the horizontal oscillating circuit 36 are phase compared. On the basis of a comparison output, an oscillating frequency is controlled. Thus, an AFC (Automatic Frequency Control) loop is constructed and the oscillating operation of the horizontal oscillating circuit 36 is stably held.

[0061] The flyback pulse is stepped up and a high voltage is formed by a high voltage circuit 39. The high voltage is applied as an anode voltage or a focusing voltage to the image receiving tube 33.

[0062] The vertical oscillating circuit 44 generates a saw-tooth wave synchronized with the vertical sync signal from the sync generating circuit 35. An output of the vertical oscillating circuit 44 is supplied to a vertical output circuit 46 via a vertical driving circuit 45. A vertical saw-tooth wave current is supplied to a vertical deflecting coil of the image receiving tube 33 by the vertical output circuit 46.

[0063] The controller 10 controls the whole operation. An input is supplied from a remote commander 48 to the controller 10 via a photosensing circuit 47. A reception channel or the like is set on the basis of the input. The display signal is generated from the display generating circuit 51 on the basis of an output of the controller 10.

[0064] A horizontal pulse and a vertical pulse which are synchronized with the horizontal sync signal and the vertical sync signal are supplied from the horizontal oscillating circuit 36 and vertical oscillating circuit 44 to the display generating circuit 51. The flyback pulse from the horizontal output circuit can be used as it is as a horizontal pulse. The display signal is generated by a display generating circuit 40 at the timing based on the horizontal and vertical pulses. The display signal is supplied to the adding circuit 32.

[0065] In the adding circuit 32, the display signal from the display generating circuit 51 is multiplexed to the three primary color signals R, G, and B from the synthesizing circuit 31. Thus, a setting state of a channel and a sound volume is displayed on the screen of the image receiving tube 33.

[0066] FIG. 2 shows a block diagram of the embodiment of the image processing circuits 29 and 28 as an essence of the invention. According to the embodiment, extraction and scaling of an arbitrary portion of an input image which is supplied are performed by a field memory. Parameters of a writing range (HAct, VAct) and a reading range (HSize, VSize) are supplied to a divider 111. A ratio of magnification or reduction of the image is set into the divider 111 by the writing range (HAct, VAct) and reading range (HSize, VSize) as will be explained hereinlater. The set ratio is supplied to horizontal interpolating circuits 112 and 115 and vertical interpolating circuits 113 and 116.

[0067] In the horizontal interpolating circuit 112, when the ratio of the reduction is supplied from the divider 111 for the inputted image, an interpolation in the horizontal direction is performed on the basis of the ratio. The image subjected to the interpolation in the horizontal direction is supplied to the vertical interpolating circuit 113. In the vertical interpolating circuit 113, when the ratio of the reduction is supplied from the divider 111 for the image from the horizontal interpolating circuit 112, an interpolation in the vertical direction is performed on the basis of the ratio. The image subjected to the interpolation in the vertical direction is supplied to a field memory 114.

[0068] The image supplied from the vertical interpolating circuit 113 on the basis of a control signal that is supplied from a write memory control circuit 117 is written into the field memory 114. The horizontal sync signal, the vertical sync signal, and the parameters of the write start position (HPhase, VPhase) and writing range (HAct, VAct) are supplied to the write memory control circuit 117. The parameters have a relation shown in FIG. 3. The image surrounded by the writing range (HAct, VAct) is written into the field memory 114.

[0069] The image written in the field memory 114 is read out therefrom on the basis of a control signal which is supplied from a read memory control circuit 118. The horizontal sync signal, the vertical sync signal, and the parameters of the read start position (HPosition, VPosition) and reading range (HSize, VSize) are supplied to the read memory control circuit 118. The parameters have a relation shown in FIG. 4. The image written in the field memory 114 is read out so as to be displayed in a range surrounded by the reading range (HSize, VSize). The read-out image is supplied to the horizontal interpolating circuit 115.

[0070] In the horizontal interpolating circuit 115, when the magnification ratio is supplied from the divider 111 for the image from the field memory 114, an interpolation in the horizontal direction is performed on the basis of the ratio. The image subjected to the interpolation in the horizontal direction is supplied to the vertical interpolating circuit 116. In the vertical interpolating circuit 116, when the magnification ratio is supplied from the divider 111 for the image from the horizontal interpolating circuit 115, an interpolation in the vertical direction is performed on the basis of the ratio. The image subjected to the interpolation in the vertical direction is outputted.

[0071] The outputted image is multiplexed as a slave picture plane 122 of PinP into a master picture plane 121 as shown in FIG. 5. In an example of FIG. 5, a TV news program is displayed on the master picture plane 121 and a score display portion of a baseball relay of a program on a different channel is extracted and displayed on the slave picture plane 122, so that the progress of the score can be successively confirmed.

[0072] In the case where an image to be displayed is a letter box signal in P&P, the letter box signal is detected. As shown in FIG. 6, a picture plane 126 in which unnecessary portions of the letter box signal, namely, upper and lower black edge portions are removed is displayed at a position adjacent to a picture plane 125.

[0073] As shown in FIG. 3, in response to the horizontal sync signal and the vertical sync signal upon writing, the write start position (HPhase, VPhase) and the writing range (HAct, VAct) in each of the horizontal and vertical directions are determined and the writing to the field memory 114 is controlled, thereby allowing only an arbitrary portion of the input image to be written into the field memory 114. As shown in FIG. 4, even at the time of the reading, in response to the horizontal sync signal and the vertical sync signal upon reading, the read start position (HPosition, VPosition) and the reading range (HSize, VSize) in each of the horizontal and vertical directions are determined and the reading from the field memory 114 is controlled, thereby enabling an arbitrary portion of the input image extracted and written in the field memory 114 upon writing to be displayed with an arbitrary size at an arbitrary position.

[0074] Now, assuming that the magnification or reduction ratio set in the divider 111 is equal to

[0075] HSize/HAct≧1 and VSize/VAct≧1,

[0076] a magnifying process is performed. When reading from the field memory 114, the reading operation is performed twice on a pixel unit basis or on a line unit basis. After that, the interpolating processes are executed by the horizontal interpolating circuit 115 and vertical interpolating circuit 116 in order to improve the picture quality. By those processes, the magnifying process of the arbitrary portion of the input image can be performed.

[0077] Now, assuming that the magnification or reduction ratio set in the divider 111 is equal to

[0078] HSize/HAct<1 and VSize/VAct<1,

[0079] a reducing process is performed. Before writing into the field memory 114, the interpolating processes are performed to the image by the horizontal interpolating circuit 112 and vertical interpolating circuit 113. When writing into the field memory 114, the decimation is performed on a pixel unit basis or on a line unit basis. In case of the reducing process, as mentioned above, the signal is decimated on a pixel unit basis or on a line unit basis and written into the field memory 14. Therefore, the interpolating processes are executed in the horizontal and vertical directions in the horizontal interpolating circuit 112 and vertical interpolating circuit 113 so that the signal can be easily decimated, and an arbitrary reduction is performed. Upon reading, the image is continuously read out in accordance with the read start position (HPosition, VPosition) and the reading range (HSize, VSize) supplied to the read memory control circuit 118. By those processes, a reducing process of an arbitrary portion of the input image can be performed.

[0080] For example, as shown in FIG. 7A, hitherto, after the write start position HPhase, a period of time during which the writing is permitted, namely, the writing range HAct is fixed. However, as shown in FIG. 7B, after the write start position HPhase, the writing range HAct can be varied. Although the writing range HAct has been described in FIGS. 7A and 7B, the writing range VAct can be also similarly varied.

[0081] By newly providing the parameters (HAct, VAct) to decide the range on the writing side as mentioned above, an arbitrary portion of a program on a different channel can be written into the field memory 114. The magnification or reduction ratio of the extracted portion is set by the parameters of the writing range (HAct, VAct) and reading range (HSize, VSize).

[0082] In the embodiment, although the image displayed on the slave picture plane of PinP or the image displayed on the second picture plane of P&P is the arbitrary portion of the image of the program on a different channel, an arbitrary portion of an image other than the input signal displayed on the master picture plane or the first picture plane, for example, the image from the video input can be used.

[0083] According to the invention, small characters or a small person is magnified and displayed on the slave picture plane of PinP. That is, by extracting only the necessary information of the arbitrary portion of the image and displaying on the slave picture plane, the small characters or small person can be discriminated. For example, by extracting only the portion of the score display of the baseball relay of the program on a different channel and displaying on the slave picture plane of PinP, the progress of the score of the baseball relay can be successively confirmed while watching a TV drama.

[0084] Further, according to the invention, by removing the upper and lower black edge portions even for the letter box signal, a P&P display can be performed at the inherent aspect ratio.

[0085] Industrial Applicability

[0086] As mentioned above, in the television apparatus, the display method of the television apparatus, and the picture plane control apparatus and method according to the invention, only the necessary area can be extracted from the video signal serving as a slave picture plane of PinP or the first and/or the second picture plane of P&P and they are useful in case of further performing the reduction or magnification to such a signal and displaying it onto the picture plane.