Active matrix type device using forcible rewriting

[0002] This application is a Divisional of Ser. No. 08/392,475, filed Feb. 22, 1995, now U.S. Pat. No. 5,767,832.

[0003] The present invention relates to an active matrix type display device and a display method thereof. The active matrix type display device means a display device in which pixels are arranged at respective intersecting points of a matrix, every pixel is provided with a switching element, and image information is controlled by on/off switching of the switching elements. Examples of display media for the active matrix type display device are a liquid crystal, plasma and other bodies or states whose optical characteristic (reflectance, refractive index, transmittance, light emission intensity, or the like) can be changed electrically. The invention particularly relates to an active matrix type display device which uses, as the switching element, a three-terminal element, i.e., a field-effect transistor having the gate, source and drain.

[0004] In describing the invention, the term “row” of a matrix means a structure in which a signal line (gate line) that is disposed parallel with a row concerned is connected to the gate electrodes of transistors belonging to the row. The term “column” means a structure in which a signal line (source line) disposed parallel with a column concerned is connected to the sources (or drains) of transistors belonging to the column. A circuit for driving the gate lines and a circuit for driving the source lines are called a gate driver and a source driver, respectively.

[0005] Flat panel displays (FPDs) have been developed as new display devices to replace a CRT display. The active matrix type display device is typical of those flat panel displays. In the active matrix type display device, a screen is divided into pixels and the individual pixels are provided with respective switching elements, which control display information that is retained by the pixels. A typical example of the active matrix type display device is a thin-film transistor (TFT) active matrix display using a TN (twisted nematic) liquid crystal.

[0006] In this display device, the display medium is the TN liquid crystal and the image information is voltages of the pixels. That is, the transmittance of the TN liquid crystal (display medium) is controlled by a voltage retained by each pixel. Conventionally, in this type of active matrix type display device, an image is rewritten by updating display contents of all the pixels by top-to-bottom sequential scanning of rows. The image rewriting is performed at a frequency of every frame, i.e., 30 to 60 times per second (30-60 Hz).

[0007] However, for certain types of display contents, the image rewriting of such a frequency is not always necessary. For example, a still image need not be rewritten until voltages retained by the pixels decrease to such low values as cannot provide sufficient display quality. Even in the case of moving images, not all the pixels display different image information every time.

[0008] The image rewriting requires output of signals, which is a factor of increasing power consumption and, therefore, an obstacle to portable applications.

[0009] The present invention has been made in view of the above circumstances, and has an object of reducing power consumption by making the frequency of image rewriting as low as possible in an active matrix type electro-optical device.

[0010] To attain the above object, the invention is characterized by the following steps.

[0011] First, a signal to be applied to the pixels of a certain row is compared with a corresponding signal of the immediately previous frame. A signal (refresh pulse) indicating the necessity of rewriting is output only when the two signals are different for at least one pixel of the row concerned. The difference between the two signals (which are, for example, and input signal and an output signal of a delay circuit) is detected by comparing the two signals in the delay circuit.

[0012] The rewriting is then effected by applying a gate pulse to a gate line of the row concerned by using the refresh pulse, to thereby make the gate electrodes of active matrix transistors of the row concerned in an on state.

[0013] If a signal to be applied to the pixels of the row concerned is the same as a corresponding signal of the immediately previous frame for all the pixels, no refresh pulse is issued as a general rule. However, if a state in which image information is kept completely the same continues over a very large number of frames, no execution of rewriting for such a long time causes various problems. For example, where a TN liquid crystal is used as the display medium, application of a voltage of the same polarity for a long time causes an electrolysis, resulting in its deterioration. Therefore, polarity inversion needs to be performed regularly. Where only a single transistor is used as the active matrix switching element, image information (for instance, a voltage) stored in a pixel is varied by a source-drain leak current etc.

[0014] Considering the above, in the invention, rewriting to pixels is forcibly effected one per several frames even if no change occurs in image information. Where a liquid crystal material is used as the display medium, it is favorable that the polarity of voltages applied to the liquid crystal be inverted (applying AC voltages) in the process of forcibly effecting the rewriting to pixels.

[0015] In the above manner, power consumption can be reduced by decreasing the frequency of image rewriting as a whole by effecting the rewriting to only pixels or rows which need the rewriting. To avoid deterioration of display characteristics, it is effective that the regular rewriting be effected in the following manner.

[0016] Assume a matrix that is composed of 20 rows, i.e., a 1st row, 2nd row, 3rd, . . . , 19th row and 20th row. It is also assumed that completely the same image continues to be displayed by this matrix, and that forcible rewriting is performed once per 5 frames.

[0017] The simplest scheme is to perform rewriting to all the rows in the first frame and perform no rewriting in the second to fifth frames. However, in this scheme, the brightness varies during the second to fifth frames by such phenomena as reduction of pixel voltages. The same brightness as in the first frame is restored by rewriting in the sixth frame.

[0018] If the one-frame period is 30 msec, the interval between two rewriting operations is 150 msec. Therefore, a brightness variation due to the rewriting in the sixth frame is sufficiently recognizable, as a flicker, to the naked eye.

[0019] This problem can be solved by distributing rewriting operations to the first and fifth frames rather than effecting the rewriting only in the first frame. More specifically, four rows are subjected to rewriting in one frame. For example, in the first frame, rewriting is forcibly performed on only the 1st row, 6th row, 11th row and 16th row. In the second frame, rewriting is performed on the 2nd row, 7th row, 12th row and 17th row. In the third frame, rewriting is performed on the 3rd row, 8th row, 13th row and 18th row. In the fourth frame, rewriting is performed on the 4th row, 9th row, 14th row and 19th row. In the fifth frame, rewriting is performed on the 5th row, 10th row, 15th row and 20th row. The similar operations are performed in the sixth frame onward. Rewriting operations may be allocated in a different manner according to the same principle.

[0020] Stated more generally, where the entire matrix is divided into N groups each consisting of m rows, N rows are subjected to forcible rewriting in one frame and rewriting to the entire rows is completed in m frames.

[0021] In this case, for example, the above-mentioned 1st row may be referred to as a first group, first row; the above-mentioned 7th row as a second group, second row; the above-mentioned 14th row as a third group, fourth row; and the above-mentioned 20th row as a fourth group, fifth row. On the other hand, the groups and rows may be given numbers in different manners.

[0022] It is possible to make a flicker not recognizable by distributing forcible rewriting operations in the above manner. As a typical example, there is a rule that in the (k−1)th frame counted from a frame next to the frame (called the first frame) in which the first row of each group is subjected to forcible rewriting, i.e., in the kth frame (k=1, 2, 3, . . . , m), the kth row should be subjected to forcible rewriting. The above-described example satisfies this rule.

[0023] However, it is not required at all to satisfy such regularity. It is sufficient to satisfy a rule that in m consecutive frames, forcible rewriting should be performed in one frame on one row of a gate line group consisting of m arbitrary rows, and all the rows of that group should be subjected to rewriting.

[0024] If the invention is viewed in a different way, it is understood that it is sufficient to satisfy a rule that in the mth frame counted from a frame next to the frame (called the first frame) in which a certain row is subjected to forcible rewriting, i.e., in the (m+1)th frame, the same row should again be subjected to forcible rewriting.

[0025] Further, where a liquid crystal material is used as the display medium, it is favorable that the polarity of voltages applied to the pixels of a row concerned in the (m+1)th frame be opposite to the polarity of voltages applied to the same pixels in the first frame and the (2m+1)th frame. This is because utilizing such forcible rewriting the liquid crystal material can be supplied with indispensable AC voltages.

[0026] FIG. 1 is a block diagram showing a circuit configuration of a first embodiment;

[0027] FIG. 2 shows a data comparison circuit in the first embodiment;

[0028] FIG. 3 shows a refresh pulse generating circuit in the first embodiment;

[0029] FIG. 4 is a time chart showing how refresh pulses are generated by the circuit of FIG. 3;

[0030] FIG. 5 shows a start pulse generating circuit of a gate driver in the first embodiment;

[0031] FIG. 6 shows another start pulse generating circuit of the gate driver in the first embodiment;

[0032] FIG. 7 is a time chart showing how start pulses are generated by the circuit of FIG. 5 or 6;

[0033] FIG. 8 shows the gate driver and its peripheral circuits in the first embodiment;

[0034] FIG. 9 shows outputs of the gate drivers in the first embodiment;

[0035] FIG. 10 is a time chart showing how gate pulses are output;

[0036] FIG. 11 is a block diagram showing a circuit configuration of a second embodiment;

[0037] FIG. 12 shows a refresh pulse generating circuit in the second embodiment;

[0038] FIG. 13 is a time chart showing how refresh pulses are generated by the circuit of FIG. 12; and

[0039] FIG. 14 is a time chart showing how gate pulses are output.

[0040] A first embodiment of the invention will be described with reference to FIGS. 1-10. FIG. 1 shows a circuit configuration of this embodiment. An active matrix employs field-effect transistors (for instance, thin-film transistors) as the switching elements, and has a size of N×m rows and M columns. The rows are divided into N groups each including m gate lines. An ith group, jth row gate line is written as (i. j).

[0041] An analog video signal is converted by an A/D converter to a digital signal, which is sent to a memory. On the other hand, a sync signal is separated from the video signal by a sync separation circuit, and supplied to a clock generator.

[0042] Two memories, i.e., memory 1 and memory 2 are provided. (Alternatively, three or more memories may be provided.) A switch S1 sends data to memory 1 or memory 2. The data stored into the memory is immediately read out via a switch S2. That is, the switch S2 operates to read out the data from one of memory 1 and memory 2 which is not selected by the switch S1.

[0043] The reason why two or more memories are used to perform write and read operations is that the data sequence needs to be converted. In an ordinary video signal, data are arranged in the following order:

[0044] (1. 1), (1. 2), (1. 3), (1. 4), . . . , (1. m)

[0045] (2. 1), (2. 2), (2. 3), (2. 4), . . . , (2. m)

[0046] (3. 1), (3. 2), (3. 3), (3. 4), . . . , (3. m)

[0047] (4. 1), (4. 2), (4. 3), (4. 4), . . . , (4. m)

[0048] (N. 1), (N. 2), (N. 3), (N. 4), . . . , (N. m)

[0049] In this embodiment, the scanning order needs to be changed to the following by a method described later:

[0050] (1. 1), (2. 1), (3. 1), (4. 1), . . . , (N. 1)

[0051] (1. 2), (2. 2), (3. 2), (4. 2), . . . , (N. 2)

[0052] (1. 3), (2. 3), (3. 3), (4. 3), . . . , (N. 3)

[0053] (1. 4), (2. 4), (3. 4), (4. 4), . . . , (N. 4)

[0054] (1. m), (2. m), (3. m), (4. m), . . . , (N. m)

[0055] The signal obtained by the above data order change is sent to a frame memory and a data comparison circuit. The same signal is also supplied to a source driver. If the source driver is of a digital type, the signal can be input thereto as it is. However, if the source driver is of a analog type, the signal needs to be subjected to D/A conversion before being input thereto.

[0056] FIG. 2 shows details of the data comparison circuit. The frame memory stores one-frame previous data. A shift register 1 sends data of a row concerned of the current frame to latch 1. A shift register 2 sends data of the row concerned of the immediately previous frame to latch 2.

[0057] Assume that the gate driver currently applies a voltage to, for instance, the ith group, jth row. In this case, current data of the ith group, jth row is stored in latch 1 and data of the same row of the one-frame previous frame is stored in latch 2. One row includes M pixels, and two data of each pixel are compared with each other by one of M EXOR circuits shown on the bottom side of FIG. 2. If the current data and the one-frame previous data are different from each other, the EXOR circuit supplies an output to an OR circuit provided downstream thereof. That is, if the current data and the one-frame previous data are different from each other for at least one of the M pixels, the OR circuit supplies a signal to the refresh pulse generating circuit.

[0058] As soon as the comparison of the itch group, jth row is finished, a comparison of the (i+1)th group, jth row is started. In this manner, the data comparison is performed one after another.

[0059] The output of the data comparison circuit is sent, via the refresh pulse generating circuit, to an AND circuit array, which is provided between the gate driver and the active matrix. The existence of an output from the data comparison circuit means that the current information of the row concerned is different than the one-frame previous information. Therefore, a gate pulse needs to be generated to perform rewriting on the row concerned. As is apparent from FIG. 3, the OR circuit immediately supplies a refresh pulse to the AND circuit array upon reception of the data comparison signal. In response, an AND circuit of the row (ith group, jth row) that has received the output of the gate driver operates to output a gate pulse.

[0060] If the data comparison circuit generates no output, a signal to cause regular, forcible rewriting should be supplied to the AND circuit array. The circuit of FIG. 3 is adapted to perform such an operation. For simplicity, assume a 20-row matrix of N=4 and m=5. FIG. 4 is a time chart showing signals at points {circle around (1)}-{circle around (5)} in FIG. 3 and a refresh pulse output. In FIG. 4, a horizontal clock includes 20 pulses in a one-frame period. By dividing the frequency of the horizontal clock signal by N (=4), the number of pulses in the one-frame period can be reduced to 5.

[0061] Receiving the pulses thus generated, delay circuits (DFFs) operate to finally generate refresh pulses, which sequentially delay by a time equal to the one-frame period, to thereby return to the original timing in a 5-frame period. In FIG. 4, refresh pulses of the 5th and 6th frames are connected to each other. If no signal is output from the data comparison circuit (that is, if there is no change in the image information), only the refresh pulses shown in FIG. 4 are output.

[0062] Now, a description will be made of the gate driver. As described above, the invention employs the scanning order that is different from the ordinary order. Therefore, the gate driver has a special configuration. FIG. 8 shows an example of the gate driver. That is, in this embodiment, m N-stage shift registers are provided in parallel. Start pulses SP₁-SP_mfor the respective shift registers are synthesized by a circuit shown in FIG. 5 or 6.

[0063] FIG. 9 is a time chart showing pulses at points immediately before the AND circuit array which pulses are generated by the above circuits and output from the gate driver of the matrix of N=4 and m=5. Circled numerals in FIG. 9 indicate the output order of the pulses. That is, the pulses are output, in order, to the first group, first row, the second group, first row, the third group, first row, the fourth group, first row, the first group, second row, the second group, second row, . . .

[0064] The output pulses (SR outputs) of the gate driver which pulses have been synthesized in the above manner are combined with a refresh pulse in the AND circuit array in a manner shown in FIG. 10. For simplicity, it is assumed that the discussion is directed to a still image and there is no output from the data comparison circuit. Although FIG. 10 shows pulses for only the first group, fourth row (1. 4), the second group, second row (2. 2), the third group, fifth row (3. 5), and the fourth group, first row (4. 1), the same thing applies to the other rows. The shift registers (SRs) for the respective rows regularly output pulses in the first to fifth frames. Only when a refresh pulse coexists with one of the output pulses of the shift registers, it is supplied, as a gate pulse, to the matrix.

[0065] For example, in the case of the row (1. 4), the refresh pulse does not coexist with the SR output in any of the first to third frames and the fifth frame and, therefore, the AND circuit does not produce a gate pulse. A gate pulse is produced only in the fourth frame in which the refresh pulse coexists with the SR output. Similarly, a gate pulse is supplied to the row (2. 2) only in the second frame, to the row (3. 5) only in the fifth frame, and to the row (4. 1) only in the first frame.

[0066] That is, in this embodiment, a gate pulse is supplied to the ith group, jth row only in the jth frame.

[0067] It goes without saying that when there exists an output from the data comparison circuit, a refresh pulse is generated each time and a gate pulse is supplied to the corresponding row.

[0068] A second embodiment of the invention will be described with reference to FIGS. 11-14. FIG. 10 shows a circuit configuration of this embodiment. An active matrix employs field-effect transistors (for instance, thin-film transistors) as the switching elements, and has a size of N×m rows and M columns. The rows are divided into N groups each including m gate lines. An ith group, jth row gate line is written as (i. j).

[0069] An analog video signal is converted by an A/D converter to a digital signal, which is sent to a data comparison circuit. On the other hand, a sync signal is separated from the video signal by a sync separation circuit, and supplied to a clock generator.

[0070] In contrast to the first embodiment, the second embodiment employs the scanning order that is the same as the order in the ordinary display scheme. Therefore, the change of the data order as performed in the first embodiment is not necessary. That is, in this embodiment, the scanning is performed in the following order:

[0071] (1. 1), (1. 2), (1. 3), (1. 4), . . . , (1. m)

[0072] (2. 1), (2. 2), (2. 3), (2. 4), . . . , (2. m)

[0073] (3. 1), (3. 2), (3. 3), (3. 4), . . . , (3. m)

[0074] (4. 1), (4. 2), (4. 3), (4. 4), . . . , (4. m)

[0075] (N. 1), (N. 2), (N. 3), (N. 4), . . . , (N. m)

[0076] The frame memory and the data comparison circuit of this embodiment are the same as those of the first embodiment (see FIG. 2). The current frame data of a row concerned is compared with the one-frame previous data stored in the frame memory. If they are different from each other, a signal is sent from the data comparison circuit to a refresh pulse generating circuit provided downstream thereof.

[0077] The output of the data comparison circuit is sent, via the refresh pulse generating circuit having a configuration shown in FIG. 12, to an AND circuit array, which is provided between the gate driver and the active matrix. The existence of an output from the data comparison circuit means that the current information of the row concerned (for example, ith group, jth row) is different from the one-frame previous information. Therefore, a gate pulse needs to be generated to perform rewriting on the row concerned. As is apparent from FIG. 12, the OR circuit immediately supplies a refresh pulse to the AND circuit array upon reception of the data comparison signal. In response, an AND circuit of the row (ith group, jth row) that has received the output of the gate driver operates to output a gate pulse.

[0078] If the data comparison circuit generates no output, a signal to cause regular, forcible rewriting should be supplied to the AND circuit array. The circuit of FIG. 12 is adapted to perform such an operation. For simplicity, assume a 20-row matrix of N=4 and m=5. FIG. 13 is a time chart showing signals at points {circle around (1)}-{circle around (4)} in FIG. 12 and a refresh pulse output. In FIG. 13, a horizontal clock includes 20 pulses in a one-frame period. By dividing the frequency of the horizontal clock signal by 2m (=10), the number of pulses in the one-frame period can be reduced to 2.

[0079] Receiving the pulses thus generated, delay circuits (DFFs) operate to finally generate refresh pulses. Four refresh pulses are output in the one-frame period, and the intervals between those pulses are the same in a single frame. In a transition from the first frame to the second frame, the first pulse is delayed by a one-pulse period. Similarly, the first pulse delays by a one-pulse period in each transition from the second frame to the third frame, the third frame to the fourth frame, and the fourth frame to the fifth frame.

[0080] When a one-cycle operation of the first frame to the fifth frame is completed, a new cycle starts from the sixth frame. As is apparent from FIG. 13, in a transition from the fifth frame to the sixth frame, the last pulse of the fifth frame is connected to the first pulse of the sixth frame. The refresh pulses are synthesized in the above manner, and supplied to the AND circuit array. If no signal is output from the data comparison circuit (that is, if there is no change in the image information), only the refresh pulses shown in FIG. 13 are output.

[0081] The gate driver of this embodiment is the same as that in the first embodiment, and is composed of a single shift register of m×N stages. Outputs of the respective stages of the shift register are supplied to the AND circuit array in the following order:

[0082] (1. 1), (1. 2), (1. 3), (1. 4), . . . , (1. m)

[0083] (2. 1), (2. 2), (2. 3), (2. 4), . . . , (2. m)

[0084] (3. 1), (3. 2), (3. 3), (3. 4), . . . , (3. m)

[0085] (4. 1), (4. 2), (4. 3), (4. 4), . . . , (4. m)

[0086] (N. 1), (N. 2), (N. 3), (N. 4), . . . , (N. m)

[0087] The output pulses (SR outputs) of the gate driver which pulses have been synthesized in the above manner are combined with a refresh pulse in the AND circuit array in a manner shown in FIG. 14. For simplicity, it is assumed that the discussion is directed to a still image and there is no output from the data comparison circuit. Although FIG. 14 shows pulses for only the first group, fourth row (1. 4), the second group, second row (2. 2), the third group, fifth row (3. 5), and the fourth group, first row (4. 1), the same thing applies to the other rows. The shift registers (SRs) for the respective rows regularly output pulses in the first to fifth frames. Only when a refresh pulse coexists with one of the output pulses of the shift registers, it is supplied, as a gate pulse, to the matrix.

[0088] For example, in the case of the row (1. 4), the refresh pulse does not coexist with the SR output in any of the first to third frames and the fifth frame and, therefore, the AND circuit does not produce a gate pulse. A gate pulse is produced only in the fourth frame in which the refresh pulse coexists with the SR output. Similarly, a gate pulse is supplied to the row (2. 2) only in the second frame, to the row (3. 5) only in the fifth frame, and to the row (4. 1) only in the first frame.

[0089] That is, in this embodiment, a gate pulse is supplied to the ith group, jth row only in the jth frame.

[0090] It goes without saying that when there exists an output from the data comparison circuit, a refresh pulse is generated each time and a gate pulse is supplied to the corresponding row.

[0091] The invention can reduce power consumption in the active matrix circuit. Further, the invention can suppress a deterioration in the image quality by distributing forcible refresh operations to several frames as described in the first and second embodiments.

[0092] It is more effective to combine the invention with various display schemes using an active matrix type device. In active matrix circuits, respective pixels have subtle differences in the display performance due to very small differences in characteristics of individual switching elements. For example, where thin-film transistors (TFTs) are used as the switching elements, a TFT having a large off-current is associated with a large leak current in a non-selected state (supplied with no gate pulse), and is therefore inferior in the charge retaining ability. In a pixel associated with such a TFT, the source should be given a higher voltage than in the ordinary case.

[0093] It is desired that the video signal be compensated, in advance, for such characteristics of the switching elements that constitute the active matrix. Such a compensation circuit may be provided after the A/D conversion circuit of the first or second embodiment. This type of compensating operation enables display of images which are clearer and in which defects are less likely to appear. That is, the invention, which performs digital processing, can be combined with other display schemes that require digital processing, to thereby cause a synergetic effect.

[0094] The invention can also be combined with a display scheme (for instance, refer to Japanese Patent Unexamined Publication No. Hei. 5-35202) in which gradational display is performed by applying a digital signal, rather than an analog signal, to pixels, to thereby provide further advantages. As such, the invention is useful in the industry concerned.