Voltage comparator, operational amplifier and analog-to-digital conversion circuit employing the same

[0002] 1. Field of the Invention

[0003] The present invention relates to a voltage comparator, an operational amplifier, and an analog-to-digital conversion circuit, having an analog-to-digital converter and a multistage pipeline (multi-step flush) structure, employing the voltage comparator and the operational amplifier.

[0004] 2. Description of the Prior Art

[0005] Following the recent development of the digital processing technique for video signals, an analog-to-digital conversion circuit (A-D converter) for processing video signals is increasingly demanded. In general, a two-step flush (two-step parallel) system is widely employed for such an analog-to-digital conversion circuit for processing video signals, which must perform high-speed conversion.

[0006] However, the analog-to-digital conversion circuit of the two-step flush system cannot attain sufficient conversion accuracy for an enormous number of converted bits. To this end, an analog-to-digital conversion circuit having a multistage pipeline (multi-step flush) structure has been developed.

[0007] FIG. 14 is a block diagram showing the structure of a conventional analog-to-digital conversion circuit 101 having a multistage pipeline structure. The analog-to-digital conversion circuit 101 shown in FIG. 14 has a 10-bit four-stage pipeline structure.

[0008] Referring to FIG. 14, the analog-to-digital conversion circuit 101 includes a sample-and-hold circuit 102, a first-stage circuit 103, a second-stage circuit 104, a third-stage circuit 105, a fourth-stage circuit 106, a plurality of latch circuits 107 and an output circuit 108.

[0009] Each of the first-stage (initial stage) to third-stage circuits 103 to 105 comprises a sub A-D converter 109, a D-A converter 110 and a differential amplifier 111. The fourth-stage (final stage) circuit 106 comprises only a sub A-D converter 109.

[0010] The first-stage circuit 103 has a 4-bit structure, and the second- to fourth-stage circuits 104 to 106 have 2-bit structures respectively.

[0011] Operations of the analog-to-digital conversion circuit 101 are now described. The sample-and-hold circuit 102 samples an analog input signal Vin and holds the same for a constant time. The analog input signal Vin outputted from the sample-and-hold circuit 102 is transferred to the first-stage circuit 103.

[0012] In the first-stage circuit 103, the sub A-D converter 109 A-D converts the analog input signal Vin. The sub A-D converter 109 transfers the result of A-D conversion, i.e., a high order 4-bit digital output (2⁹, 2⁸, 2⁷, 2⁶) to the D-A converter 110 while transferring the same to the output circuit 108 through four latch circuits 107. The differential amplifier 111 amplifies the difference between the result of D-A conversion of the D-A converter 110 and the analog input signal Vin. The differential amplifier 111 transfers its output to the second-stage circuit 104.

[0013] The second-stage circuit 104 performs operations similar to those of the first-stage circuit 103 on the output from the differential amplifier 111 of the first-stage circuit 103. The third-stage circuit 105 performs operations similar to those of the first-stage circuit 103 on an output from the differential amplifier 111 of the second-stage circuit 104. The second-stage circuit 104 provides an intermediate high order 2-bit digital output (2⁵, 2⁴), while the third-stage circuit 105 provides an intermediate low order 2-bit digital output (2³, 2²).

[0014] In the fourth-stage circuit 106, the sub A-D converter 109 A-D converts an output from the differential amplifier 111 of the third-stage circuit 105, to provide a low order 2-bit digital output (2¹, 2⁰).

[0015] The digital outputs from the first- to fourth-stage circuits 103 to 106 simultaneously reach the output circuit 108 through the respective latch circuits 107. In other words, the latch circuits 107 are adapted to synchronize the digital outputs from the circuits 103 to 106 with each other.

[0016] The output circuit 108 outputs a 10-bit digital output Dout of the analog input signal Vin in parallel after digital correction, if necessary.

[0017] Thus, in each of the first- to third-stage circuits 103 to 105 of the analog-to-digital conversion circuit 101, the differential amplifier 111 amplifies the difference between the analog input signal Vin or the output from the differential amplifier 111 of the precedent circuit 103 or 104 and the result of D-A conversion of the digital output thereof.

[0018] Even if the number of converted bits is increased to reduce the least significant bit (LSB), therefore, the resolution of comparators forming each sub A-D converter 109 can be substantially improved for attaining sufficient conversion accuracy.

[0019] Following the recent speed increase of electronic apparatuses, a higher conversion speed is required to analog-to-digital converters. In order to increase the conversion speed of the aforementioned conventional analog-to-digital conversion circuit 101, the GB product (gain-bandwidth product) of an operational amplifier forming each differential amplifier 111 must be increased. However, improvement of the GB product of the operational amplifier is limited. Therefore, it is difficult to further increase the conversion speed of the analog-to-digital conversion circuit 101.

[0020] As hereinabove described, the A-D converter of each circuit is referred to as the sub A-D converter 109, to be distinguished from the overall analog-to-digital conversion circuit 101. A total parallel comparison (flush) system which can perform high-speed conversion is employed for the sub A-D converter 109. The sub A-D converter 109 includes a plurality of comparators comparing an input voltage with a plurality of reference voltages. Each comparator is formed by a differential voltage comparator.

[0021] FIG. 15 is a circuit diagram of a conventional differential voltage comparator.

[0022] Referring to FIG. 15, a differential amplification circuit 10 includes P-channel MOS field-effect transistors (hereinafter referred to as PMOS transistors) 1 and 2, N-channel MOS field-effect transistors (hereinafter referred to as NMOS transistors) 3 and 4 and a constant current source 7.

[0023] The PMOS transistors 1 and 2 are connected between a node ND and output nodes NO1 and NO2 respectively. The NMOS transistors 3 and 4 are connected between the output nodes NO1 and NO2 and a node NS respectively.

[0024] The node ND is supplied with a power supply voltage V_DD, while the node NS is grounded through the constant current source 7. The PMOS transistors 1 and 2 are supplied with a bias voltage VB in the gates thereof respectively. The gates of the NMOS transistors 3 and 4 are connected to input nodes NA and NB respectively.

[0025] The input nodes NA and NB are connected to nodes N1 and N2 through capacitors 5 and 6 respectively. Switches SW11 and SW21 are connected between the input nodes NA and NB and the output nodes NO1 and NO2 respectively. Switches SW12 and SW13 are connected in parallel with the node N1, while switches SW22 and SW23 are connected in parallel with the node N2.

[0026] The switches SW12 and SW13 are supplied with input voltages V₁(+) and V₂(+) in input ends thereof respectively, while the switches SW22 and SW23 are supplied with input voltages V₁(−) and V₂(−) in input ends thereof respectively. Output voltages V₀(+) and V₀(−)are derived from the output nodes NO1 and NO2 respectively.

[0027] FIG. 16 is adapted to illustrate operations of the differential voltage comparator shown in FIG. 15.

[0028] First, the switches SW11, SW21, SW12 and SW22 are moved to ON, while the switches SW13 and SW23 are moved to OFF. At this time, differential input voltages between the input nodes NA and NB and between the output nodes NO1 and NO2 are 0 V.

[0029] Then, the switches SW11 and SW21 are moved to OFF, and thereafter the switches SW12 and SW22 are moved to OFF, while the switches SW13 and SW23 are moved to ON. Thus, voltages of the input nodes NA and NB change by V₂(+)−V₁(+)and V₂(−)−V₁(−) respectively. The difference between the input voltages V₁(+) and V₂(+) is referred to as a differential input voltage ΔV(+), and that between the input voltages V₁(−) and V₂(−) is referred to as a differential input voltage ΔV(−).

[0030] The differential amplification circuit 10 compares the differential input voltages ΔV(+) and ΔV(−) with each other, so that one of the output voltages V₀(+) and V₀(−) from the output nodes NO1 and NO2 changes toward the power supply voltage V_DDand the other one changes toward the ground potential. Thus, the differential output voltage between the output nodes NO1 and NO2 changes to a positive or negative side.

[0031] In the differential voltage comparator shown in FIG. 15, each of the switches SW11 to SW13 and SW21 to SW23 is generally formed by a CMOS switch. FIGS. 17(a) and 17(b) are circuit diagrams of such a CMOS switch SW.

[0032] The switch SW shown in FIG. 17(a) is formed by a PMOS transistor 501 and an NMOS transistor 502, as shown in FIG. 17(b). The PMOS and NMOS transistors 501 and 502 are supplied with complementary control signals SA and SB in the gates thereof respectively.

[0033] In such a CMOS switch SW, parasitic capacitances Cs are present between the gates and sources and between the gates and drains of the PMOS and NMOS transistors 501 and 502. Therefore, switching noise depending on an input voltage in an ON or OFF state of the CMOS switch SW is transmitted through capacitive coupling of the parasitic capacitances Cs.

[0034] In the differential voltage comparator shown in FIG. 15, such switching noise causes noise n in the differential input voltage between the input nodes NA and NB, as shown in FIG. 16. Thus, the differential output voltage between the output nodes NO1 and NO2 temporarily changes on the basis of the noise n and thereafter changes to indicate the essential result of comparison. Consequently, it takes time to stabilize the differential output voltage between the output nodes NO1 and NO2 in the state indicating the essential result of comparison, and hence a subsequent circuit receiving the output signals V₀(+) and V₀(−) of the differential voltage comparator cannot obtain the result of comparison in a short time. Therefore, the speed of an analog-to-digital conversion circuit employing such a differential voltage comparator cannot be increased.

[0035] An object of the present invention is to provide an analog-to-digital conversion circuit which is increased in conversion speed while maintaining high conversion accuracy.

[0036] Another object of the present invention is to provide a voltage comparator which can perform a high-speed operation while eliminating influence by noise, an analog-to-digital converter comprising the voltage comparator, and an analog-to-digital conversion circuit comprising the analog-to-digital converter.

[0037] Still another object of the present invention is to provide an operating method of a voltage comparator which can perform a high-speed operation while eliminating influence by noise.

[0038] An analog-to-digital conversion circuit according to an aspect of the present invention comprises a plurality of stages of circuits each including an analog-to-digital converter, a digital-to-analog converter, a subtraction circuit, and operational amplifiers provided in a plurality of stages.

[0039] In this analog-to-digital conversion circuit, the operational amplifiers in each stage of the circuits are provided in a plurality of stages, whereby the loop constant of the operational amplifier per stage as well as the load capacitance of the operational amplifier per stage can be reduced. Thus, the limit operating frequency of each operational amplifier is increased. Consequently, the conversion speed can be increased while maintaining high conversion accuracy without improving the performance of each operational amplifier.

[0040] The plurality of stages of circuits may be in a multistage pipeline structure. Further, the gain of each stage of the operational amplifiers provided in a plurality of stages in at least second and higher stages of the circuits may be set to exceed 1.

[0041] Thus, the gain of the operational amplifier per stage can be reduced while keeping the gain of each of the second and higher stages of the circuits.

[0042] An output of a precedent operational amplifier of the plurality of stages of operational amplifiers in each stage of the circuits may be supplied to the subtraction circuit in the same stage of the circuits, and an output of a subsequent operational amplifier of the plurality of stages of operational amplifiers in each stage of the circuits may be supplied to the analog-to-digital converter and the operational amplifier in the subsequent stage of the circuits.

[0043] In this case, amplification by the precedent operational amplifier and analog-to-digital conversion by the analog-to-digital converter can be performed in parallel with each other in the circuit of each stage. Thus, analog-to-digital conversion, digital-to-analog conversion and amplification in each stage of the circuits can be implemented within one clock. Consequently, the timings of analog-to-digital conversion by the analog-to-digital converter and digital-to-analog conversion by the digital-to-analog converter are relaxed in the circuit of each stage.

[0044] An analog-to-digital conversion circuit according to another aspect of the present invention has a multistage pipeline structure formed by a plurality of stages of circuits, and each stage of the circuits excluding the final stage of circuits includes an analog-to-digital converter converting an analog signal supplied from the precedent stage of the circuits to a digital signal, at least one stage of first operational amplifier amplifying an analog signal supplied from the precedent stage of the circuits, a digital-to-analog converter converting a digital signal outputted from the analog-to-digital converter to an analog signal, a subtraction circuit performing subtraction of an analog signal outputted from the first operational amplifier and an analog signal outputted from the digital-to-analog converter, and at least one stage of second operational amplifier amplifying an analog signal outputted from the subtraction circuit.

[0045] In this analog-to-digital conversion circuit, each stage of the circuits includes at least one first operational amplifier and at least one second operational amplifier, whereby the loop constant of the operational amplifier per stage as well as the load capacitance of the operational amplifier per stage can be reduced. Thus, the limit operating frequency of each operational amplifier is increased. Consequently, the conversion speed can be increased while maintaining high conversion accuracy without improving the performance of each operational amplifier itself.

[0046] Further, amplification by the first operational amplifier and analog-to-digital conversion by the analog-to-digital converter can be performed in parallel with each other in the circuit of each stage. Thus, analog-to-digital conversion, digital-to-analog conversion and amplification in each stage of the circuits can be implemented within one clock. Consequently, the timings of analog-to-digital conversion by the analog-to-digital converter and digital-to-analog conversion by the digital-to-analog converter are relaxed in the circuit of each stage.

[0047] The gain of the first operational amplifier in the initial stage of the circuits may be at least 1. When the gain of the first operational amplifier in the initial stage of the circuits is 1, the first operational amplifier performs a sample-and-hold operation. When the gain of the first operational amplifier in the initial stage of the circuits is in excess of 1, on the other hand, the first operational amplifier performs amplification.

[0048] The final stage of the circuits may include an analog-to-digital converter converting an analog signal supplied from the precedent stage of the circuits to a digital signal.

[0049] In this case, the analog-to-digital converter in the final stage of the circuits provides lower order bits of a digital output.

[0050] The initial stage of the circuits may have a bit structure set to be larger by at least two bits than that in the second and higher stages of the circuits, and the second to final stages of the circuits may have a bit structure uniformly divided.

[0051] Thus, the speed of conversion can be increased while maintaining higher conversion accuracy.

[0052] A voltage comparator according to still another aspect of the present invention comprises a comparing circuit performing a comparing operation, and an output circuit starting an output operation after a constant time from starting of the comparing operation of the comparing circuit.

[0053] This voltage comparator starts the output operation after the constant time from starting of the comparing operation, thereby outputting an output signal indicating the result of comparison after noise substantially disappears.

[0054] Therefore, the output signal is not influenced by the noise but immediately changes to a state indicating the essential result of comparison. Therefore, a voltage comparator which can perform a high-speed operation while eliminating influence by noise is implemented.

[0055] The comparing circuit may have first and second output terminals outputting signals complementary to each other, and the output circuit may include a switch substantially shorting the first and second output terminals when noise appears and opening the first and second output terminals after the noise substantially disappears.

[0056] In this case, the first and second terminals are substantially shorted when noise appears and then opened after the noise substantially disappears, thereby outputting complementary output signals indicating the result of comparison after the noise substantially disappears.

[0057] Therefore, the output signals are not influenced by noise but immediately change to states indicating the essential result of comparison. Therefore, a voltage comparator which can perform a high-speed operation while eliminating influence by noise is implemented.

[0058] A voltage comparator according to a further aspect of the present invention comprises a comparing circuit comparing first and second input voltages inputted in first and second input terminals respectively with each other and outputting the results of comparison as first and second output voltages complementary to each other from first and second output terminals, and a switch substantially shorting the first and second output terminals before the first and second input voltages are inputted to the first and second input terminals and opening the first and second output terminals in a delay by a constant time from supply of the first and second input voltages to the first and second input terminals.

[0059] This voltage comparator substantially shorts the first and second output terminals before receiving the first and second input voltages and opens the first and second output terminals in a delay by a constant time from supply of the first and second input voltages, thereby outputting the complementary first and second output voltages indicating the results of comparison after noise appearing in supply of the first and second input voltages substantially disappears.

[0060] Therefore, the first and second output signals are not influenced by noise but immediately change to states indicating the essential results of comparison. Therefore, a voltage comparator which can perform a high-speed operation while eliminating influence by noise is implemented.

[0061] The first input voltage may be a first differential input voltage, and the second input voltage may be a second differential input voltage.

[0062] In this case, the voltage comparator substantially shorts the first and second output terminals before receiving the first and second differential input voltages and opens the first and second output terminals in a delay by a constant time from supply of the first and second input voltages, thereby outputting the complementary first and second output voltages indicating the results of comparison after noise appearing in supply of the first and second differential input voltages substantially disappears.

[0063] Therefore, the first and second output signals are not influenced by noise but immediately change to states indicating the essential results of comparison. Therefore, a voltage comparator which can perform a high-speed operation while eliminating influence by noise is implemented.

[0064] A voltage comparator according to a further aspect of the present invention comprises a differential amplification circuit having first and second input terminals and first and second output terminals, a first switch connected between the first input terminal and the first output terminal, a second switch connected between the second input terminal and the second output terminal, a first capacitance connected to the first input terminal, a second capacitance connected to the second input terminal, and a third switch connected between the first and second output terminals. The first, second and third switches are brought into ON states while first and second input voltages are supplied to input ends of the first and second capacitances respectively, thereafter the first and second switches are brought into OFF states while third and fourth input voltages are supplied to the input ends of the first and second capacitances respectively, and the third switch is brought into an OFF state after a constant time.

[0065] In this voltage comparator, the first and second input voltages are supplied to the input ends of the first and second capacitances respectively in ON states of the first, second and third switches. Thereafter the third and fourth input voltages are supplied to the input ends of the first and second capacitances respectively in OFF states of the first and second switches. Then, the third switch is brought into an OFF state after a constant time. Thus, the voltage comparator compares the differential voltage between the first and third input voltages supplied to the input end of the first capacitance with the differential voltage between the second and fourth input voltages supplied to the input end of the second capacitance when the third switch enters an OFF state, so that the first and second output terminals output the results of comparison as complementary output signals.

[0066] In this case, the third switch enters an OFF state after a constant time from supply of the third and fourth input voltages, whereby the output terminals output the results of comparison after switching noise substantially disappears. Therefore, the first and second output signals are not influenced by noise but immediately change to states indicating the essential results of comparison. Thus, a voltage comparator which can perform a high-speed operation while eliminating influence by noise is implemented.

[0067] The differential amplification circuit may include a first transistor connected between a first power supply potential and the first output terminal, a second transistor connected between the first power supply potential and the second output terminal, a third transistor connected between a second power supply potential and the first output terminal, a fourth transistor connected between the second power supply potential and the second output terminal, and a constant current source interposed in a path between the first power supply potential and the first and second transistors or in a path between the second power supply potential and the third and fourth transistors, while control electrodes of the first and second transistors may be connected to the first and second input terminals respectively.

[0068] In this case, the first, second, third and fourth transistors and the constant current source differentially amplify the differential voltage between the first and third input voltages and that between the second and fourth input voltages.

[0069] A prescribed bias voltage may be supplied to control electrodes of the third and fourth transistors. Thus, the third and fourth transistors serve as loads.

[0070] Alternatively, the differential amplification circuit may include a first transistor connected between a first power supply potential and the first output terminal, a second transistor connected between the first power supply potential and the second output terminal, a third transistor connected between a second power supply potential and the first output terminal, a fourth transistor connected between the second power supply potential and the second output terminal, and a constant current source interposed in a path between the first power supply potential and the first and second transistors or in a path between the second power supply potential and the third and fourth transistors, while control electrodes of the third and fourth transistors may be connected to the first and second input terminals respectively.

[0071] In this case, the first, second, third and fourth transistors and the constant current source differentially amplify the differential voltage between the first and third input voltages and that between the second and fourth input voltages.

[0072] A prescribed bias voltage may be supplied to control electrodes of the first and second transistors. Thus, the first and second transistors serve as loads.

[0073] Each of the first, second and third switches may be a complementary switch formed by a first conductivity type channel transistor and a second conductivity type channel transistor.

[0074] Even if switching noise is inputted to the first and second input terminals through parasitic capacitances present in the respective transistors of the complementary switch, the output terminals output the output signals indicating the results of comparison after the switching noise substantially disappears.

[0075] The voltage comparator may further comprise a fourth switch connected between the first input terminal and a prescribed voltage source and a fifth switch connected between the second input terminal and the prescribed voltage source, the fourth and fifth switches may be brought into ON states when the third switch is in an ON state, and the fourth and fifth switches may be brought into OFF states when the third switch is in an OFF state.

[0076] In this case, a voltage from the voltage source is supplied to the first and second output terminals when the first and second input voltages are inputted in the first and second input terminals, and the first and second output terminals are cutoff from the voltage source after a constant time from supply of the third and fourth input voltages to the first and second input terminals. Thus, the first and second input terminals are kept at the same potential before change of the output signals. Therefore, the output signals stably change with no influence by noise.

[0077] An operational amplifier according to a further aspect of the present invention comprises an amplification circuit having first and second output terminals outputting output signals complementary to each other, and a switch substantially shorting the first and second output terminals when noise appears and opening the first and second output terminals after the noise substantially disappears.

[0078] This operational amplifier substantially shorts the first and second terminals when noise appears and opens the first and second output terminals after the noise substantially disappears, thereby outputting the complementary output signals indicating results of comparison after the noise substantially disappears.

[0079] Therefore, first and second output signals are not influenced by noise but immediately change to states indicating the essential results of comparison. Thus, an operational amplifier which can perform a high-speed operation while eliminating influence by noise is implemented.

[0080] An operational amplifier according to a further aspect of the present invention comprises an amplification circuit differentially amplifying first and second input voltages inputted to first and second input terminals respectively and outputting first and second output voltages complementary to each other from first and second output terminals, and a switch substantially shorting the first and second output terminals before the first and second input voltages are inputted to the first and second input terminals and opening the first and second output terminals in a delay by a constant time from supply of the first and second input voltages to the first and second input terminals.

[0081] This operational amplifier substantially shorts the first and second output terminals before supply of the first and second input voltages and opens the first and second output terminals in a delay by the constant time from supply of the first and second input voltages, thereby outputting the complementary first and second output voltages indicating the results of comparison after noise appearing in supply of the first and second input voltages substantially disappears.

[0082] Therefore, the first and second output signals are not influenced by noise but immediately change to states indicating the essential results of comparison. Thus, an operational amplifier which can perform a high-speed operation while eliminating influence by noise is implemented.

[0083] The first input voltage may be a first differential input voltage, and the second input voltage may be a second differential input voltage.

[0084] In this case, the operational amplifier substantially shorts the first and second output terminals before supply of the first and second differential input voltages and opens the first and second output terminals in a delay by the constant time from supply of the first and second differential input voltages, thereby outputting the complementary first and second output voltages indicating the results of comparison after noise appearing in supply of the first and second differential input voltages substantially disappears.

[0085] Therefore, the first and second output signals are not influenced by noise but immediately change to states indicating the essential results of comparison. Thus, an operational amplifier which can perform a high-speed operation while eliminating influence by noise is implemented.

[0086] An analog-to-digital converter according to a further aspect of the present invention comprises a plurality of comparators each comparing an input voltage with at least one referential potential, and each of the plurality of comparators comprises a differential amplification circuit having first and second input terminals and first and second output terminals, a first switch connected between the first input terminal and the first output terminal, a second switch connected between the second input terminal and the second output terminal, a first capacitance connected to the first input terminal, a second capacitance connected to the second input terminal, and a third switch connected between the first output terminal and the second output terminal. The first, second and third switches are brought into ON states while first and second input voltages are supplied to input ends of the first and second capacitances respectively, thereafter the first and second switches are brought into OFF states while third and fourth input voltages are supplied to the input ends of the first and second capacitances respectively, and the third switch is brought into an OFF state after a constant time.

[0087] Each comparator is formed by the aforementioned voltage comparator, whereby the analog-to-digital converter can perform a high-speed operation while eliminating influence by noise.

[0088] An analog-to-digital conversion circuit according to a further aspect of the present invention has a multistage pipeline structure formed by a plurality of stages, and each of the plurality of stages includes an analog-to-digital converter, a digital-to-analog converter and a differential amplifier. The analog-to-digital converter includes a plurality of comparators each comparing an input voltage with at least one referential potential, a differential amplification circuit having first and second input terminals and first and second output terminals, a first switch connected between the first input terminal and the first output terminal, a second switch connected between the second input terminal and the second output terminal, a first capacitance connected to the first input terminal, a second capacitance connected to the second input terminal, and a third switch connected between the first output terminal and the second output terminal. The first, second and third switches are brought into ON states while first and second input voltages are supplied to input ends of the first and second capacitances respectively, thereafter the first and second switches are brought into OFF states while third and fourth input voltages are supplied to the input ends of the first and second capacitances respectively, and the third switch is brought into an OFF state after a constant time.

[0089] This analog-to-digital conversion circuit employing the aforementioned analog-to-digital converter can perform a high-speed operation while eliminating influence by noise. Thus, a high-accuracy analog-to-digital conversion circuit which has a large number of bits and high resolution and can perform a high-speed operation is implemented.

[0090] An analog-to-digital conversion circuit according to a further aspect of the present invention has a multistage pipeline structure formed by a plurality of stages, and each of the plurality of stages includes an analog-to-digital converter, a digital-to-analog converter and a differential amplifier. The differential amplifier includes an operational amplifier, which comprises an amplification circuit differentially amplifying first and second input voltages inputted to first and second input terminals respectively and outputting first and second output voltages complementary to each other from first and second output terminals, and a switch substantially shorting the first and second output terminals before the first and second input voltages are inputted to the first and second input terminals and opening the first and second output terminals in a delay by a constant time from supply of the first and second input voltages to the first and second input terminals.

[0091] This analog-to-digital conversion circuit employing the aforementioned operational amplifier can perform a high-speed operation while eliminating influence by noise. Thus, a high-accuracy analog-to-digital conversion circuit which has a large number of bits and high resolution and can perform a high-speed operation is implemented.

[0092] An operating method of a voltage comparator according to a further aspect of the present invention, which is applied to a voltage comparator comprising a differential amplification circuit having first and second input terminals and first and second output terminals, a first capacitance connected to the first input terminal and a second capacitance connected to the second input terminal, includes steps of substantially shorting the first input terminal and the first output terminal, the second input terminal and the second output terminal and the first and second output terminals respectively while supplying first and second input voltages to input ends of the first and second capacitances respectively, thereafter opening the first input terminal and the first output terminal as well as the second input terminal and the second output terminal while supplying third and fourth input voltages to the input ends of the first and second capacitances respectively, and opening the first and second output terminals after a constant time.

[0093] In the operating method of a voltage comparator, the first and second input voltages are first supplied to the input ends of the first and second capacitances respectively in ON states of first, second and third switches. Thereafter the third and fourth input voltages are supplied to the input ends of the first and second capacitances respectively in OFF states of the first and second switches. Then, the third switch is brought into an OFF state after a constant time. Thus, the differential voltage between the first and third input voltages supplied to the input end of the first capacitance is compared with that between the second and fourth input voltages supplied to the input end of the second capacitance when the third switch is brought into an OFF state-, so that the first and second output terminals output the results of comparison as complementary output signals.

[0094] In this case, the third switch is brought into an OFF state after the constant time from supply of the third and fourth input voltages, whereby the results of comparison are outputted after switching noise substantially disappears. Therefore, the first and second output signals are not influenced by noise but immediately change to states indicating the essential results of comparison. Thus, a voltage comparator which can perform a high-speed operation while eliminating influence by noise is implemented.

[0095] The operating method of a voltage comparator may further include steps of applying a prescribed voltage to the first and second output terminals when these output terminals are substantially shorted, and cutting off the first and second output terminals from the prescribed voltage when these output terminals are opened.

[0096] In this case, a voltage from a voltage source is supplied to the first and second output terminals of the differential amplification circuit when the first and second input voltages are inputted in the first and second input terminals and the first and second output terminals are cut off from the voltage source after the constant time from supply of the third and fourth input voltages to the first and second input terminals. Thus, the first and second output terminals are kept at the same potential before change of the output signals. Therefore, the output signals stably change with no influence by noise.

[0097] The foregoing and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

[0098] FIG. 1 is a block diagram showing the structure of an analog-to-digital conversion circuit according to an embodiment of the present invention;

[0099] FIG. 2 is a block diagram showing the structure of a principal part of the inventive analog-to-digital conversion circuit;

[0100] FIG. 3 is a waveform diagram showing operation timings in the analog-to-digital conversion circuit shown in FIG. 2;

[0101] FIG. 4 is a block diagram showing the structure of a principal part of a comparative analog-to-digital conversion circuit;

[0102] FIG. 5 is a waveform diagram showing operation timings in the analog-to-digital conversion circuit shown in FIG. 4;

[0103] FIG. 6 is a circuit diagram showing the structure of a principal part of an operational amplifier in each of the inventive and comparative analog-to-digital conversion circuits;

[0104] FIG. 7 is a circuit diagram showing a differential voltage comparator according to another embodiment of the present invention;

[0105] FIG. 8 is adapted to illustrate operations of the differential voltage comparator shown in FIG. 7;

[0106] FIG. 9 is a circuit diagram showing an operational amplifier according to still another embodiment of the present invention;

[0107] FIG. 10 is a circuit diagram of a bias voltage generation circuit;

[0108] FIG. 11 is adapted to illustrate operations of the operational amplifier shown in FIG. 9;

[0109] FIG. 12 is a block diagram showing the structure of an analog-to-digital conversion circuit having a multistage pipeline structure according to a further embodiment of the present invention;

[0110] FIG. 13 is a circuit diagram of a sub A-D converter and a D-A converter in the analog-to-digital conversion circuit shown in FIG. 12;

[0111] FIG. 14 is a block diagram showing the structure of a conventional analog-to-digital conversion circuit;

[0112] FIG. 15 is a circuit diagram of a conventional differential voltage comparator;

[0113] FIG. 16 is adapted to illustrate operations of the differential voltage comparator shown in FIG. 15; and

[0114] FIGS. 17(a) and 17(b) are circuit diagrams showing the structure of a CMOS switch.

[0115] FIG. 1 is a block diagram showing the structure of an analog-to-digital conversion circuit 301 according to an embodiment of the present invention. The analog-to-digital conversion circuit 301 shown in FIG. 1 has a 10-bit four-stage pipeline structure.

[0116] Referring to FIG. 1, the analog-to-digital conversion circuit 301 includes a sample-and-hold circuit 302, first- to fourth-stage circuits 303 to 306, a plurality of latch circuits 307 and an output circuit 308.

[0117] The first-stage (initial stage) circuit 303 comprises a sub A-D converter 309, a D-A converter 310, an operational amplifier 311a,a subtraction circuit 312 and another operational amplifier 313. Each of the second- and third-stage circuits 304 and 305 comprises a sub A-D converter 309, a D-A converter 310, an operational amplifier 311, a subtraction circuit 312 and another operational amplifier 313.

[0118] As described later, the operational amplifier 311aprovided in the first-stage circuit 303 has a gain 1 and serves as a sample-and-hold circuit. The gain of the operational amplifier 313 in each of the first- to third-stage circuits 303 to 305 is 2. The fourth-stage (final stage) circuit 306 comprises only a sub A-D converter 309.

[0119] The first-stage circuit 303 has a 4-bit structure, and each of the second- to fourth-stage circuits 304 to 306 has a 2-bit structure. In the first- to third-stage circuits 303 to 305, the sub A-D converters 309 and the D-A converters 310 are set at the same bit numbers (bit structures).

[0120] Operations of the analog-to-digital conversion circuit 301 shown in FIG. 1 are now described. The sample-and-hold circuit 302 samples an analog input signal Vin and holds the same for a constant time. The analog input signal Vin outputted from the sample-and-hold circuit 302 is transferred to the first-stage circuit 303.

[0121] In the first-stage circuit 303, the sub A-D converter 309 A-D converts the analog input signal Vin. The sub A-D converter 309 transfers the result of A-D conversion, i.e., a high order 4-bit digital output (2⁹, 2⁸, 2⁷, 2⁶) to the D-A converter 310 while transferring the same to the output circuit 308 through four latch circuits 307. The D-A converter 310 converts the high order 4-bit digital output (2⁹, 2⁸, 2⁷, 2⁶), i.e., the result of A-D conversion of the sub A-D converter 309, to an analog signal.

[0122] On the other hand, the operational amplifier 311asamples the analog input signal Vin and holds the same for a constant time. The subtraction circuit 312 performs subtraction of the analog input signal Vin outputted from the operational amplifier 311aand the result of D-A conversion of the D-A converter 310. The operational amplifier 313 amplifies an output of the subtraction circuit 312. An output of the operational amplifier 313 is transferred to the second-stage circuit 304.

[0123] In the second-stage circuit 304, the sub A-D converter 309 A-D converts the output from the operational amplifier 313 of the first-stage circuit 303. The sub A-D converter 309 transfers the result of A-D conversion to the D-A converter 310 while transferring the same to the output circuit 30820 through three latch circuits 307. Thus, the second-stage circuit 304 provides an intermediate high order 2-bit digital output (25, 24).

[0124] On the other hand, the operational amplifier 311 amplifies the output from the operational amplifier 313 of the first-stage circuit 303. The subtraction circuit 312 performs subtraction of an output of the operational amplifier 311 and the result of D-A conversion of the D-A converter 310. The operational amplifier 313 amplifies an output of the subtraction circuit 312. An output of the operational amplifier 313 is transferred to the third-stage circuit 305.

[0125] The third-stage circuit 305 performs operations similar to those of the second-stage circuit 304 on the output from the operational amplifier 313 of the second-stage circuit 304. Thus, the third-stage circuit 305 provides an intermediate low order 2-bit digital output (2³, 2²).

[0126] In the fourth-stage circuit 306, the sub A-D converter 309 A-D converts an output from the operational amplifier 313 of the third-stage circuit 305, to provide a low order 2-bit digital output (2¹, 2⁰).

[0127] The digital outputs from the first- to fourth-stage circuits 303 to 306 simultaneously reach the output circuit 308 through the respective latch circuits 307. Namely, the latch circuits 307 are adapted to synchronize the digital outputs from the circuits 303 to 306 with each other.

[0128] The output circuit 308 outputs a 10-bit digital output Dout of the analog input signal Vin in parallel after digital correction, if necessary.

[0129] The conversion speed of the inventive analog-to-digital conversion circuit is now described in comparison with that of a comparative analog-to-digital conversion circuit. The inventive analog-to-digital conversion circuit has the structure shown in FIG. 1, and the comparative analog-to-digital conversion circuit has the structure shown in FIG. 14.

[0130] FIG. 2 is a block diagram showing the structure of a principal part of the inventive analog-to-digital conversion circuit, and FIG. 3 is a waveform diagram showing operation timings in the analog-to-digital conversion circuit shown in FIG. 2. FIG. 4 is a block diagram showing the structure of a principal part of the comparative analog-to-digital conversion circuit, and FIG. 5 is a waveform diagram showing operation timings in the analog-to-digital conversion circuit shown in FIG. 4.

[0131] In the inventive analog-to-digital conversion circuit shown in FIG. 2, the loop constants of the operational amplifiers 311aand 313 in the first-stage circuit 303 are set at 1 and 2 respectively, whiled those of the operational amplifiers 311 and 313 in the second- and third-stage circuits 304 and 305 are set at 2.

[0132] Further, the bit number (bit structure) of the sub A-D converter 309 provided in the first-stage circuit 303 is 4, while those of the sub A-D converters 309 in the second- to fourth-stage circuits 304 to 306 are 2.

[0133] In the comparative analog-to-digital conversion circuit shown in FIG. 4, on the other hand, subtraction circuits 112 and operational amplifiers 113 in first- to third-stage circuits 103 to 105 form the differential amplifier 111 shown in FIG. 14. The loop constants of the operational amplifiers 113 in the first- to third-stage circuits 103 to 105 are set at 4 respectively.

[0134] Further, the bit number (bit structure) of the sub A-D converter 109 provided in the first-stage circuit 103 is 4, while those of the sub A-D converters 109 in the second- to fourth-stage circuits 104 to 106 are 2.

[0135] In an analog-to-digital conversion circuit of a multistage pipeline structure, a limit operating frequency f_SYSis decided through a loop frequency f_LOOPof each operational amplifier as follows:

[0136] f_SYS≈½×f_LOOP=½×1/Ai×f_OP  (1)

[0137] where f_OPrepresents a GB product (gain-bandwidth product) frequency of each operational amplifier, Ai represents the loop constant of each operational amplifier, and ½ represents an operating margin.

[0138] From the above expression (1), it is necessary to reduce the loop constant Ai for increasing the limit operating frequency f_SYSof the analog-to-digital conversion circuit.

[0139] In the comparative analog-to-digital conversion circuit, the loop constant Ai is set at 4. In this case, the GB product frequency f_OPof each operational amplifier must be at least 160 MHz, in order to increase the operating frequency f_SYSto 20 MHz.

[0140] The inventive analog-to-digital conversion circuit having the plurality of stages of operational amplifiers 311a,311 and 313 in the first- to third-stage circuits 303 to 305 can reduce the loop constant Ai of the operational amplifiers 311a,311 and 313 without changing the gain per circuit stage.

[0141] As hereinabove described, the loop constants Ai of the operational amplifiers 311aand 313 provided in the first-stage circuit 303 are set at 1 and 2 respectively, and those of the operational amplifiers 311 and 313 provided in the second- and third-stage circuits 304 and 305 are set at 2.

[0142] In general, a limit speed (GB product) of an operational amplifier for obtaining the same dc gain is as follows:

[0143] GB product≈gm/CL

[0144] where CL represents a load capacitance, and gm represents a mutual conductance. Assuming that the mutual conductance gm is constant in the above expression, the limit speed (GB product) of the operational amplifier depends on the load capacitance CL.

[0145] FIG. 6 shows the structure of a principal part of each operational amplifier 200 employed for each of the inventive and comparative analog-to-digital conversion circuits. As shown in FIG. 6, a capacitor 201 is connected to an inversion input terminal of the operational amplifier 200, while an output terminal thereof is connected to the inversion input terminal through a capacitor 202.

[0146] It is assumed that KC and C represent the capacitance values of the capacitors 201 and 202 respectively. When input voltage change V_iis supplied to an input end of the capacitor 201, output voltage change ΔV_ois as follows:

[0147] ΔV_o=(KC/C)·ΔV_i=K·ΔV_i

[0148] Thus, the input capacitance is increased when the gain K of the operational amplifier is increased. In other words, the input capacitance value of the subsequent operational amplifier is reduced when the gain K of each operational amplifier is reduced, for reducing the load capacitance of each operational amplifier.

[0149] In the inventive analog-to-digital conversion circuit, the loop constants Ai of the operational amplifiers 311 and 313 are half those of the operational amplifiers 113 in the comparative analog-to-digital conversion circuit, thereby halving the load capacitances of the operational amplifiers 311a,311 and 313.

[0150] When the operational amplifiers 311a,311 and 313 have the same performance, therefore, the limit GB product frequency f_OPMAXthereof is 320 MHz. Therefore, the loop frequency f_LOOPis 160 MHz, and the limit operating frequency f_SYSis 80 MHz.

[0151] Table 1 shows the speed performance of the inventive and comparative analog-to-digital conversion circuits.

[0152] As shown in Table 1, the limit operating frequency f_SYSof the inventive analog-to-digital conversion circuit is 80 MHz, i.e., four times that of the comparative circuit. Therefore, the inventive analog-to-digital conversion circuit obtains a conversion speed of four times that of the comparative circuit.

[0153] The inventive analog-to-digital conversion circuit performs the respective operations in synchronization with a clock signal CLK of 80 MHz, as shown in FIG. 3. On the other hand, the comparative analog-to-digital conversion circuit performs the respective operations in synchronization with a clock signal CLK of 20 MHz, as shown in FIG. 5.

[0154] In the comparative analog-to-digital conversion circuit, the sub A-D converter 109, the D-A converter 110 and the operational amplifier 113 execute A-D conversion, D-A conversion and amplification and holding within a half clock respectively in the second-stage circuit 104, for example, as shown by broken lines in FIG. 5.

[0155] In the inventive analog-to-digital conversion circuit, on the other hand, the sub A-D converter 309 and the operational amplifier 311 perform A-D conversion and amplification and holding at the same timing while the D-A converter 310 and the operational amplifier 313 perform D-A conversion and amplification and holding at the same timing in the second-stage circuit 304, for example, as shown by broken lines in FIG. 3.

[0156] In this case, the A-D converter 309, the D-A converter 310 and the operational amplifiers 311 and 313 execute the A-D conversion, the D-A conversion and the amplification and holding respectively within one clock. Therefore, the timings of the sub A-D converter 309 and the D-A converter 310 are relaxed.

[0157] Thus, the two-stage operational amplifiers 311a,311 and 313 are provided in the first- to third-stage circuits 303 to 305 in the analog-to-digital conversion circuit according to the embodiment, whereby the loop constants of the operational amplifiers 311a,311 and 313 can be reduced while the load capacitances thereof are also reduced. Consequently, the conversion speed can be increased without improving the performance of the operational amplifiers 311a,311 and 313.

[0158] Further, the initial stage circuit 303 has the 4-bit structure and the second- to final stage circuits 304 to 306 are uniformly divided in 2-bit structures respectively, so that the A-D conversion circuit has a 4-2-2-2 structure thereby attaining high conversion accuracy (refer to Japanese Patent Laying-Open No. 9-69776 (1997), for example).

[0159] While the gain of the operational amplifier 311aprovided in the initial stage circuit 303 is 1 in the aforementioned structure, the operational amplifier 311amay have a gain of 2, similarly to the remaining operational amplifiers 311.

[0160] While each of the first- to third-stage circuits 303 to 305 is provided with two stages of operational amplifiers 311aor 311 and 313 in the aforementioned embodiment, each circuit may alternatively be provided with three or more stages of operational amplifiers.

[0161] FIG. 7 is a circuit diagram of a differential voltage comparator according to another embodiment of the present invention.

[0162] Referring to FIG. 7, a differential amplification circuit 10 includes formed by P-channel MOS field-effect transistors (hereinafter referred to as PMOS transistors) 1 and 2, N-channel MOS field-effect transistors (hereinafter referred to as NMOS transistors) 3 and 4 and a constant current source 7. In general, an NMOS transistor of a saturated operation is employed for the constant current source 7.

[0163] The PMOS transistors 1 and 2 are connected between a node ND and output nodes NO1 and NO2 respectively. The NMOS transistors 3 and 4 are connected between the output nodes NO1 and NO2 and a node NS respectively.

[0164] The node ND is supplied with a power supply voltage V_DD, and the node NS is grounded through the constant current source 7. A bias voltage V_Bis supplied to gates of the PMOS transistors 1 and 2. Gates of the NMOS transistors 3 and 4 are connected to input nodes NA and NB respectively.

[0165] The input nodes NA and NB are connected to nodes N1 and N2 through capacitors 5 and 6 respectively. Switches SW11 and SW21 are connected between the input nodes NA and NB and the output nodes NO1 and NO2 respectively. Switches SW12 and SW13 are connected in parallel with the node N1, while switches SW22 and SW23 are connected in parallel with the node N2.

[0166] Particularly in the differential voltage comparator according to this embodiment, a switch SW30 is connected between the output nodes NO1 and NO2. Each of the switches SW11 to SW13, SW21 to SW23 and SW30 is formed by a CMOS switch similar to that shown in FIGS. 17(a) and 17(b).

[0167] Input voltages V₁(+) and V₂(+) are supplied to input ends of the switches SW12 and SW13 respectively, while input voltages V₁(−) and V₂(−) are supplied to input ends of the switches SW22 and SW23 respectively. Output voltages V_o(+) and V_o(−) are derived from the output nodes NO1 and NO2 respectively.

[0168] FIG. 8 is adapted to illustrate operations of the differential voltage comparator shown in FIG. 7.

[0169] First, the switches SW11, SW21, SW12 and SW22 are moved to ON and the switches SW13 and SW23 are moved to OFF, while the switch SW30 is moved to ON. At this time, the differential input voltage between the input nodes NA and NB as well as that between the output nodes NO1 and NO2 are 0 V.

[0170] Then, the switches SW11 and SW21 are moved to OFF, and thereafter the switches SW12 and SW22 are moved to OFF and the switches SW13 and SW23 are moved to ON respectively. Thus, the voltage of the input node NA changes to V₂(+)−V₁(+), and that of the input node NB changes to V₂(−)−V₁(−). The difference between the input voltages V₁(+) and V₂(+) is referred to as a differential input voltage ΔV(+), and that between the input voltages V₁(−) and V₂(−) is referred to as a differential input voltage ΔV(−).

[0171] Noise n resulting from switching noise of the switches SW12, SW13, SW22 and SW23 is transiently caused in the differential input voltage between the input nodes NA and NB. The switch SW30 is moved to OFF after a lapse of a constant time corresponding to the time of generation of the noise n. At this point of time, one of the output voltages V_o(+) and V_o(−) from the output nodes NO1 and NO2 changes toward the power supply voltage V_DDand the remaining one changes toward the ground potential on the basis of the result of comparison of the differential input voltages ΔV(+) and ΔV(−) of the input nodes NA and NB. Thus, the differential output voltage between the output nodes NO1 and NO2 changes to a positive or negative side from 0 V on the basis of the result of comparison.

[0172] In this case, the differential output voltage between the output nodes NO1 and NO2 immediately changes to a state indicating the result of comparison with no influence by the noise n, whereby no standby time is required for stabilizing the differential output voltage from the state based on the noise n to that indicating the result of comparison, and the result of comparison can be obtained in a short time. Thus, the differential voltage comparator according to this embodiment can perform a high-speed operation while eliminating influence by noise by delaying the output timing for the result of comparison by a slight time corresponding to that generating the noise n. In this case, the differential voltage comparator may output the result of comparison after the noise n substantially disappears.

[0173] FIG. 9 is a circuit diagram of an operational amplifier according to still another embodiment of the present invention.

[0174] In the operational amplifier shown in FIG. 9, output circuits 41 and 42 are connected to output nodes NO1 and NO2 similar to those of the differential voltage comparator shown in FIG. 7 respectively. FIG. 9 omits illustration of capacitors 5 and 6 which are connected to input nodes NA and NB and switches SW12, SW13, SW22 and SW23.

[0175] The output circuit 41 is formed by a PMOS transistor 11, an NMOS transistor 12 and a capacitor 13. The PMOS transistor 11 is connected between a power supply voltage V_DDand an output node NOA, while the NMOS transistor 12 is connected between the output node NOA and a ground potential. The capacitor 13 is connected between the output nodes NO1 and NOA. A gate of the PMOS transistor 11 is connected to the output node NO1, and that of the NMOS transistor 12 is supplied with a bias voltage V_B.

[0176] The output circuit 42 is formed by a PMOS transistor 21, an NMOS transistor 22 and a capacitor 23. The PMOS transistor 21 is connected between the power supply voltage V_DDand an output node NOB, while the NMOS transistor 22 is connected between the output node NOB and the ground potential. The capacitor 23 is connected between the output node NOB and the ground potential. A gate of the PMOS transistor 21 is connected to the output node NO2, and that of the NMOS transistor 22 is supplied with the bias voltage V_B.

[0177] The output node NOA of the output circuit 41 outputs an output voltage VO(+), and the output node NOB of the output circuit 42 outputs an output voltage VO(−).

[0178] Further, the output nodes NO1 and NO2 are connected to a node NC through switches SWA and SWB respectively. The gates of the PMOS transistors 1 and 2 are connected to the node NC, which is supplied with the bias voltage V_B.

[0179] FIG. 10 is a circuit diagram of a bias voltage generation circuit 30. The bias voltage generation circuit 30 shown in FIG. 10 is formed by a PMOS transistor 31, an NMOS transistor 32 and a constant current source 33. The PMOS transistor 31 is connected between the power supply voltage V_DDand the node NC. The node NC is grounded through the NMOS transistor 32 and the constant current source 33. Gates of the PMOS transistor 31 and the NMOS transistor 32 are connected to the node NC. The node NC outputs the bias voltage V_B.

[0180] FIG. 11 is adapted to illustrate operations of the operational amplifier shown in FIG. 9. In the operational amplifier shown in FIG. 9, operations of a part corresponding to the differential voltage comparator shown in FIG. 7 are similar to those shown in FIG. 8.

[0181] As shown in FIG. 11, the switch SW30 is first moved to ON. At this time, the switches SWA and SWB are also moved to ON. Thus, the bias voltage V_Bis applied to the output nodes NO1 and NO2.

[0182] Then, the switch SW30 is moved to OFF. At the same time, the switches SWA and SWB are also moved to OFF. Thus, the output voltages VO(+) and VO(−) of the output nodes NOA and NOB change to positive or negative sides on the basis of the differential input voltage between the input nodes NA and NB.

[0183] Thereafter the switch SW30 is moved to ON. At the same time, the switches SWA and SWB are also moved to ON. Thus, the bias voltage V_Bis applied to the output nodes NO1 and NO2.

[0184] Thus, the output voltages VO(+) and VO(−) change after the noise n resulting from switching noise of the switches SW12, SW13, SW22 and SW23 (see FIG. 7) disappears in the operational amplifier according to this embodiment, whereby the result of amplification is obtained in a short time.

[0185] Further, the output nodes NO1 and NO2 are kept at the bias voltage V_Bbefore outputting the result of amplification, whereby the output voltages VO(+) and VO(−) stably change with no influence by noise. Thus, a high-speed operation is enabled while eliminating influence by noise.

[0186] FIG. 12 is a block diagram showing the structure of an analog-to-digital conversion circuit 501 according to a further embodiment of the present invention. The analog-to-digital conversion circuit 501 shown in FIG. 12 has a 10-bit four-stage pipeline structure.

[0187] Referring to FIG. 12, the analog-to-digital conversion circuit 501 includes a sample-and-hold circuit 502, a first-stage circuit 503, a second-stage circuit 504, a third-stage circuit 505, a fourth-stage circuit 506, a plurality of latch circuits 507 and an output circuit 508.

[0188] Each of the first-stage (initial stage) to third-stage circuits 503 to 505 comprises a sub A-D converter 509, a D-A converter 510 and a differential amplifier 511. The differential amplifier 511 is prepared from an operational amplifier identical to that according to the second embodiment. The fourth-stage (final stage) circuit 506 comprises only a sub A-D converter 509.

[0189] The first-stage circuit 503 has a 4-bit structure, and each of the second- to fourth-stage circuits 504 to 506 has a 2-bit structure. In the first- to third-stage circuits 503 to 505, the sub A-D converters 509 and the D-A converters 510 are set at the same bit number (bit structure) n.

[0190] Operations of the analog-to-digital conversion circuit 501 are now described. The sample-and-hold circuit 502 samples an analog input signal Vin and holds the same for a constant time. The analog input signal Vin outputted from the sample-and-hold circuit 502 is transferred to the first-stage circuit 503.

[0191] In the first-stage circuit 503, the sub A-D converter 509 A-D converts the analog input signal Vin. The sub A-D converter 509 transfers the result of A-D conversion, i.e., a high order 4-bit digital output (2⁹, 2⁸, 2⁷, 2⁶) to the D-A converter 510 while transferring the same to the output circuit 508 through four latch circuits 507. The differential amplifier 511 amplifies the difference between the result of D-A conversion of the D-A converter 510 and the analog input signal Vin. The differential amplifier 511 transfers its output to the second-stage circuit 504.

[0192] The second-stage circuit 504 performs operations similar to those of the first-stage circuit 503 on the output from the differential amplifier 511 of the first-stage circuit 503. The third-stage circuit 505 performs operations similar to those of the first-stage circuit 503 on an output from the differential amplifier 511 of the second-stage circuit 504. The second-stage circuit 504 provides an intermediate high order 2-bit digital output (2⁵, 2⁴), while the third-stage circuit 505 provides an intermediate low order 2-bit digital output (2³, 2²).

[0193] In the fourth-stage circuit 506, the sub A-D converter 509 A-D converts an output from the differential amplifier 511 of the third-stage circuit 505, to provide a low order 2-bit digital output (2¹, 2⁰).

[0194] The digital outputs from the first- to fourth-stage circuits 503 to 506 simultaneously reach the output circuit 508 through the respective latch circuits 507. In other words, the latch circuits 507 are adapted to synchronize the digital outputs from the circuits 503 to 506 with each other.

[0195] The output circuit 508 outputs a 10-bit digital output Dout of the analog input signal Vin in parallel after digital correction, if necessary.

[0196] Thus, in each of the first- to third-stage circuits 503 to 505 of the analog-to-digital conversion circuit 501, the differential amplifier 511 amplifies the difference between the analog input signal Vin or the output of the differential amplifier 511 of the precedent circuit 503 or 504 and the result of D-A conversion of its digital output.

[0197] Even if the number of converted bits is increased to reduce the least significant bit (LSB), therefore, the resolution of each sub A-D converter 509 can be substantially improved for attaining sufficient conversion accuracy.

[0198] FIG. 13 is a circuit diagram of each sub A-D converter 509 and each D-A converter 510 in the analog-to-digital conversion circuit 501 shown in FIG. 13. The sub A-D converter 509 and the D-A converter 510 shown in FIG. 13 are a total parallel comparison (flush) system sub A-D converter and a capacitance array system D-A converter respectively.

[0199] The sub A-D converter 509 includes n resistances R and n comparators C1 to Dn. Each of the comparators D1 to Dn is prepared from a differential voltage comparator identical to that shown in FIG. 7.

[0200] All resistors R have the same resistance value and are serially connected between a node N31 receiving a high-potential side reference voltage VRT and a node N32 receiving a low-potential side reference voltage VRB. It is assumed that nodes N41 to N4n between the n resistors R connected between the nodes N32 and N31 have potentials VR(1) to VR(n) respectively.

[0201] An input signal VI (the analog input signal Vin or the output from the differential amplifier 511 of the precedent circuit 503, 504 or 505) is inputted in positive input terminals of the comparators D1 to Dn. The potentials VR(1) to VR(n) of the nodes N41 to N4n are applied to negative input terminals of the comparators D1 to Dn respectively.

[0202] Thus, outputs of the comparators D1 to Dn go high if the input signal VI is higher than the potentials VR(1) to VR(n), or go low when the input signal VI is lower than the potentials VR(1) to VR(n).

[0203] The D-A converter 510 includes n switches E1 to En, F1 to Fn, G1 to Gn and H1 to Hn which are connected in the form of an array, n positive capacitors B1 to Bn and n negative capacitors C1 to Cn.

[0204] All capacitors B1 to Bn and C1 to Cn have the same capacitance value c. A differential positive output voltage VDA(+) is formed from first terminals (hereinafter referred to as output terminals) of the capacitors B1 to Bn, while a differential negative output voltage VDA(−) is formed from first terminals (hereinafter referred to output terminals) of the capacitors C1 to Cn. Second terminals of the capacitors B1 to Bn and C1 to Cn are referred to as input terminals.

[0205] First and second terminals of the switches E1 to En are connected to the node N31 and the input terminals of the capacitors B1 to Bn respectively. First and second terminals of the switches F1 to Fn are connected to the node N31 and the input terminals of the capacitors C1 to Cn respectively. First and second terminals of the switches G1 to Gn are connected to the node N32 and the input terminals of the capacitors B1 to Bn respectively. First and second terminals of the switches H1 to Hn are connected to the node N32 and the input terminals of the capacitors C1 to Cn respectively.

[0206] The switches E1 to En, F1 to Fn, G1 to Gn and H1 to Hn form four series of switches. For example, the switches E1, F1, G1 and H1 are a series of switches, and the switches En, Fn, Gn and Hn are another series of switches. The switches E1 to En, F1 to Fn, G1 to Gn and H1 to Hn are turned on or off in accordance with output levels of the comparators D1 to Dn respectively. For example, the switches En and Hn are moved to ON and the switches Gn and Fn are moved to OFF when the output of the comparator Dn is at a high level. When the output of the comparator Dn is at a low level, on the other hand, the switches En and Hn are moved to OFF and the switches Gn and Fn are moved to ON.

[0207] The output of the comparator D1 forming the sub A-D converter 509 is in an open state. The switches E1 and F1 are fixed in ON states at a prescribed timing, and the switches G1 and H1 are fixed in OFF states at a prescribed timing.

[0208] The voltage of the input signal VI for the sub A-D converter 509 is in the range between the high-potential side reference voltage VRT and the low-potential side reference voltage VRB. In other words, the input signal VI for the sub A-D converter 509 never falls below the low-potential side reference voltage VRB. Therefore, the output of the comparator D1 necessarily goes high. Thus, the switches E1, G1, F1 and H1 can be fixed in OFF states at prescribed timings regardless of the output of the comparator D1.

[0209] Operations of the D-A converter 510 are now described. Under initial conditions, the potentials of the input and output terminals of the capacitors B1 to Bn are 0 V, and all switches E1 to En, F1 to Fn, G1 to Gn and H1 to Hn are in OFF states. Under the initial conditions, therefore, the quantity Q1 of charges (electricity) stored in all capacitors B1 to Bn and C1 to Cn is zero.

[0210] When outputs from m ones of the n comparators D1 to Dn go high, m and (n−m) ones of the switches E1 to En enter ON and OFF states respectively, while (n−m) and m ones of the switches G1 to Gn enter ON and OFF states respectively. In accordance with such ON-OFF operations of the switches E1 to En, the quantity Q2 of charges stored in all capacitors B1 to Bn is expressed as follows:

[0211] Q2=m(VRT−VDA(+))c+(n−m)(VRB−VDA(+))c  (A1)

[0212] From the principle of conservation of charge, Q1=Q2. Hence, the differential positive output voltage VDA(+) is expressed as follows:

[0213] VDA(+)=VRB+m(VRT−VRB)/n  (A2)

[0214] When the outputs of m ones of the n comparators D1 to Dn go high, m and (n−m) ones of the switches H1 to Hn enter ON and OFF states respectively, while (n−m) and m ones of the switches F1 to Fn enter ON and OFF states respectively. In accordance with such ON-OFF operations of the switches H1 to Hn and F1 to Fn, the quantity Q3 of charges stored in all capacitors C1 to Cn is expressed as follows:

[0215] Q3=(n−m)(VRT−VDA(−))c+m(VRB−VDA(−))c  (A3)

[0216] From the principle of conservation of charge, Q1=Q3. Hence, the differential negative output voltage VDA(−) is expressed as follows:

[0217] VDA(−)=VRB−(m−1)(VRT−VRB)/n  (A4)

[0218] Hence, from the above expressions (A2) and (A4), a differential voltage ΔVDA is expressed as follows:

[0219] ΔVDA=VDA(+)−VDA(−)=VRB−VRT+(m−1)(VRT−VRB)/n−(VRT−VRB)/n  (A5)

[0220] The analog-to-digital conversion circuit 501 according to this embodiment, employing differential voltage comparators identical to that shown in FIG. 7 as the comparators D1 to Dn of each sub A-D converter 509 while employing operational amplifiers identical to that shown in FIG. 9 as the differential amplifiers 511 of the respective stages, can perform a high-speed operation while eliminating influence by noise. Thus, an analog-to-digital conversion circuit having a large bit number and high resolution, which can perform a high-speed operation in high accuracy is implemented.

[0221] While the comparators D1 to Dn compare the input signal VI with a plurality of reference potentials in the sub A-D converter 509 shown in FIG. 13, the inventive voltage comparator is also applicable to the case of comparing an input signal with at least one reference potential.

[0222] While the voltage comparator according to the present invention is applied to an analog-to-digital conversion circuit of a multistage pipeline structure in the aforementioned embodiment, the inventive voltage comparator is also applicable to a ΔΣ (delta-sigma) or sequential comparison analog-to-digital conversion circuit.

[0223] Although the present invention has been described and illustrated in detail, it is clearly understood that the same is by way of illustration and example only and is not to be taken by way of limitation, the spirit and scope of the present invention being limited only by the terms of the appended claims.