Method for forming a transistor within an integrated circuit

[0002] The present invention relates to integrated circuit fabrication, and more specifically to a method for forming a transistor within an integrated circuit.

[0003] The semiconductor industry continually strives to increase device performance by reducing the distance between individual devices, and by reducing the size of the devices themselves. Unfortunately, this continuing reduction in device dimensions has begun to adversely effect the performance and the reliability of integrated circuits.

[0004] Specifically, the reduction in transistor gate length has made it more difficult to control the drain saturation current of submicron transistors, especially submicron PMOS transistors. The source and drain regions of a transistor are fabricated using dopants that rapidly diffuse through silicon. Present integrated circuit fabrication processes, however, cannot uniformly and repeatedly control the lateral diffusion of these dopants. As a result, submicron transistors often have non-uniform drain saturation currents. This occurs because the overlap between the gate electrode and the source and drain regions cannot be repeatedly controlled, due to the uncontrolled lateral diffusion of the dopants which are used to form the source and drain regions.

[0005] Accordingly, a need exists for a method to form transistors in an integrated circuit which have improved drain saturation currents.

[0006] The present invention may be more fully understood by a description of certain preferred embodiments in conjunction with the attached drawings in which:

[0007] FIGS. 1-6 illustrate, in cross-section and plan view, process steps in accordance with the present invention.

[0008] FIGS. 1 through 6, illustrate in cross-section and plan view, process steps for forming a transistor in an integrated circuit in accordance with the present invention. Shown in FIG. 1, is a portion of an integrated circuit structure 10 comprising a semiconductor substrate 12, a gate dielectric layer 14, and a gate electrode 16 having a sidewall 18 and a sidewall 20.

[0009] In one embodiment, semiconductor substrate 12 is a monocrystalline silicon substrate. Alternatively, semiconductor substrate 12 may be a silicon-on-insulator (SOI) substrate, a silicon-on-sapphire (SOS) substrate, a silicon-germanium substrate, or the like.

[0010] Gate dielectric layer 14 overlies semiconductor substrate 12, and in one embodiment gate dielectric layer 14 is a layer of thermal silicon dioxide, which is formed by thermally oxidizing a portion of semiconductor substrate 12. Alternatively, gate dielectric layer 14 may be a layer of silicon nitride, a layer of silicon oxynitride, a layer of chemical vapor deposited silicon dioxide, or the like. In addition, a combination of the foregoing dielectric materials may also be used to form gate dielectric layer 14. For example, gate dielectric layer 14 may comprise a layer of silicon oxynitride overlying a layer of thermal silicon dioxide, or a layer of chemically vapor deposited silicon dioxide overlying a layer of thermal silicon dioxide.

[0011] Gate electrode 16 overlies gate dielectric layer 14, and is formed using conventional photolithographic patterning and etching techniques. Gate electrode 16 may be formed using a silicon layer such as polysilicon or amorphous silicon, a metal layer such as copper, tantalum, molybdenum or tungsten, a metal silicide layer such as tungsten silicide, titanium silicide or cobalt silicide, a metal nitride layer such as titanium nitride, tantalum nitride or tungsten nitride, tungsten-silicon-nitride, or the like. In addition, a combination of the foregoing materials may also be used to form gate electrode 16. For example, gate electrode 16 may comprise a layer of cobalt silicide overlying a layer of polysilicon, or a layer of tungsten nitride overlying a layer of tungsten.

[0012] In FIG. 2, a spacer layer 22 is formed overlying gate electrode 16. In one embodiment spacer layer 22 is a dielectric layer, such as a layer of silicon dioxide, a layer of silicon nitride, a layer of boro-phosphate-silicate-glass (BPSG), a layer of phosphate-silicate-glass (PSG), a layer of spin-on-glass (SOG), a layer of silicon oxynitride, or the like. In addition, a combination of the foregoing dielectric materials may also be used to form spacer layer 22. For example, spacer layer 22 may comprise a layer of silicon nitride overlying a layer of silicon dioxide, or a layer of BPSG overlying a layer of silicon oxynitride. In an alternative embodiment, spacer layer 22 is a silicon layer, such as a layer of polysilicon, or amorphous silicon. Spacer layer 22 may be formed using conventional plasma deposition techniques, chemical vapor deposition techniques, spin-on coating techniques, or a combination thereof. For example, in a particular embodiment wherein spacer layer 22 comprises a layer of silicon dioxide, spacer layer 22 may be plasma deposited using tetraethylorthosilicate (TEOS) as source gas. Similarly, in a particular embodiment wherein spacer layer 22 comprises a layer of silicon nitride or silicon oxynitride, spacer layer 22 may be plasma deposited using silane (SiH4) as a source gas. It should be appreciated that prior to forming spacer layer 22, a portion of gate electrode 16 may also be oxidized to form an oxide layer (not shown) that lies between a portion of gate electrode 16 and spacer layer 22. Similarly, it should also be appreciated that after forming spacer layer 22, a portion of gate electrode 16 may also be oxidized to form an oxide layer (not shown) that lies between a portion of gate electrode 16 and spacer layer 22.

[0013] In FIG. 3, spacer layer 22 is then etched to form a structure 26 and a sidewall spacer 24, wherein structure 26 comprises sidewall spacer 24 and gate electrode 16. Sidewall spacer 24 has a first portion 28 and a second portion 30, and gate electrode 16 lies between first portion 28 and second portion 30, as shown in FIG. 3. In addition, first portion 28 has a sidewall spacer width 32, gate electrode 16 has a gate width 34, and second portion 30 has a sidewall spacer width 36. It is important to note that structure 26 has a total width 38 which comprises the sidewall spacer width 32, the gate width 34, and the sidewall spacer width 36, as shown in FIG. 3. In a preferred embodiment, first portion 28 and second portion 30 have approximately the same sidewall spacer width.

[0014] At least a portion of structure 26 is then measured in order to determine whether or not a process condition in a subsequent integrated circuit fabrication process needs to be adjusted. In one embodiment, the sidewall spacer width 32 of first portion 28 is measured. In an alternative embodiment, the sidewall spacer width 36 of second portion 30 is measured. In another embodiment, the total width 38 of structure 26 is measured. In yet another embodiment, the total width 38 of structure 26 and the gate width 34 of gate electrode 16 are measured in order to determine the sidewall spacer width 32 of first portion 28 and/or the sidewall spacer width 36 of second portion 30. In a preferred embodiment, these measurements are made using a scanning electron microscope (SEM). In one embodiment these measurements are made without cleaving structure 26, and thus it is non-destructively measured. In an alternative embodiment structure 26 is cleaved, and thus it is destructively measured.

[0015] In one embodiment, at least a portion of structure 26 is measured in order to determine whether or not an etch condition in the spacer etch process needs to be adjusted. For example, if a portion of sidewall spacer 24 on semiconductor substrate 12 is measured and found to have a sidewall spacer width which is too large, then an etch condition in the spacer etch process is adjusted so that a sidewall spacer subsequently formed on a second semiconductor substrate has the appropriate sidewall spacer width. More specifically, the spacer etch process is adjusted to decrease the sidewall spacer width of the sidewall spacer formed on the second semiconductor substrate. It should be appreciated that this can be achieved in a variety of ways. For example, one or more of the following etch conditions may be adjusted in order to obtained the desired sidewall spacer width on the second semiconductor substrate: RF power, magnetic field strength, an etch gas flow rate, an etch gas flow ratio, electrostatic chuck temperature, etch pressure, or the like. For example, in a particular embodiment wherein spacer layer 22 comprises silicon dioxide the carbon tetrafluoride (CF4) to trifluoromethane (CHF3) flow ratio may be adjusted in order to achieve the desired sidewall spacer width. Similarly, if a portion of sidewall spacer 24 on semiconductor substrate 12 is measured and found to have a sidewall spacer width which is too small, then an etch condition in the spacer etch process is adjusted so that a sidewall spacer subsequently formed on a second semiconductor substrate has the appropriate sidewall spacer width. More specifically, the spacer etch process is adjusted to increase the sidewall spacer width of the sidewall spacer formed on the second semiconductor substrate. It should be appreciated that this can be achieved in a variety of ways. For example, one or more of the following etch conditions may be adjusted in order to obtained the desired sidewall spacer width: RF power, magnetic field strength, an etch gas flow rate, an etch gas flow ratio, electrostatic chuck temperature, etch pressure, or the like. For example, in a particular embodiment wherein spacer layer 22 comprises silicon dioxide the carbon tetrafluoride (CF4) to trifluoromethane (CHF3) flow ratio may be adjusted in order to achieve the desired sidewall spacer width.

[0016] It should be appreciated that monitoring and adjusting the spacer etch process, as described above, allows transistors with improved drain saturation currents to be fabricated. A uniform and repeatable lateral diffusion distance for source and drain dopants is achieved by controlling the sidewall spacer width. Therefore, uniform and repeatable overlap between the gate electrode and the source and drain regions is achieved, and transistors having improved drain saturation currents are fabricated with the present invention.

[0017] Shown in FIG. 4, is a top down view of integrated circuit structure 10 of FIG. 3.

[0018] In FIG. 5, a dopant 40 is then implanted into a portion of semiconductor substrate 12 to form doped region 42 and doped region 44. In one embodiment, dopant 40 comprises a p-type dopant, such as boron (B) or boron difluoride (BF2), and doped region 42 and doped region 44 are p-type conductivity regions. In alternative embodiment, dopant 40 comprises an n-type dopant, such as arsenic (As), phosphorous (P), or antimony (Sb), and doped region 42 and doped region 44 are n-type conductivity regions.

[0019] In an alternative embodiment of the present invention, at least a portion of structure 26 is measured in order to determine whether or not an implant condition in the implant process needs to be adjusted prior to forming doped region 42 and doped region 44. For example, if a portion of sidewall spacer 24 is measured and found to have a sidewall spacer width which is too large, then the implant dose can be increased to increase the doping concentration of doped region 42 and doped region 44. Similarly, if a portion of sidewall spacer 24 is measured and found to have a sidewall spacer width which is too small, then the implant dose can be decreased to decrease the doping concentration of doped region 42 and doped region 44. Alternatively, if a portion of sidewall spacer 24 is measured and found to have a sidewall spacer width which is too large, then the implant energy can be increased to increase the lateral straggle of dopant 40 within semiconductor substrate 12. Similarly, if a portion of sidewall spacer 24 is measured and found to have a sidewall spacer width which is too small, then the implant dose can be decreased to decrease the lateral straggle of dopant 40 within semiconductor substrate 12. It should be appreciated that other implant conditions, besides energy and dose may be adjusted. For example, implant temperature or implant angle may also be adjusted to form doped region 42 and doped region 44.

[0020] It should be appreciated that adjusting the implant process based on measurements taken after the spacer etch process, as described above, allows transistors with improved drain saturation currents to be fabricated. A uniform and repeatable lateral diffusion distance for source and drain dopants is achieved by controlling the implant process. Therefore, uniform and repeatable overlap between the gate electrode and the source and drain regions is achieved, and transistors having improved drain saturation currents are fabricated with the present invention.

[0021] In FIG. 6, doped region 42 and doped region 44 are then annealed to form annealed region 46 and annealed region 48. The anneal causes dopant within doped region 42 to laterally diffuse under first portion 28 of sidewall spacer 24, and dopant within doped region 44 to laterally diffuse under second portion 30 of sidewall spacer 24, as shown in FIG. 6. Note, in this particular embodiment annealed region 46 and annealed region 48 define a channel region 50 for a transistor 52, wherein transistor 52 comprises gate electrode 16, gate dielectric layer 14, annealed region 46, annealed region 48, and channel region 50.

[0022] Note, in this particular embodiment, transistor 52 is formed without lightly doped drain (LDD) regions. It should be appreciated, however, that transistor 52 may also be formed with LDD regions. In that case, prior to depositing spacer layer 22, a dopant similar to that described in FIG. 5 would be introduced into semiconductor substrate 12 using gate electrode 16 as an implant mask to form lightly doped regions on either side of gate electrode 16. Note if transistor 52 is an NMOS transistor then the LDD regions would be n-type conductivity regions, and if transistor 52 is a PMOS transistor then the LDD regions would be p-type conductivity regions.

[0023] In another embodiment of the present invention, at least a portion of structure 26 is measured in order to determine whether or not an annealing condition in the anneal process needs to be adjusted prior to forming annealed region 46 and annealed region 48. For example, if a portion of sidewall spacer 24 is measured and found to have a sidewall spacer width which is too large, then the annealing temperature can be increased to increase the lateral diffusion distance of dopant from doped region 42 and doped region 44. Similarly, if a portion of sidewall spacer 24 is measured and found to have a sidewall spacer width which is too small, then the annealing temperature can be decreased to decrease the lateral diffusion distance of dopant from doped region 42 and doped region 44. Alternatively, if a portion of sidewall spacer 24 is measured and found to have a sidewall spacer width which is too large, then the annealing time can be increased to increase the lateral diffusion distance of dopant from doped region 42 and doped region 44. Similarly, if a portion of sidewall spacer 24 is measured and found to have a sidewall spacer width which is too small, then the annealing time can be decreased to decrease the lateral diffusion distance of dopant from doped region 42 and doped region 44.

[0024] In a preferred embodiment, doped region 42 and doped region 44 are annealed in a rapid thermal annealing system for a time ranging from approximately 5 seconds to approximately 60 seconds, at a temperature ranging from approximately 700° C. to approximately 1100° C. In an alternative embodiment, doped regions 42 and doped regions 44 are annealed in a furnace system for time ranging from approximately 15 minutes to approximately 2 hours, at a temperature ranging from approximately 700° C. to approximately 900° C.

[0025] It should be appreciated that other annealing conditions besides temperature and time may also be adjusted. For example, the rate at which doped region 42 and doped region 44 are ramped up to the peak annealing temperature, the rate at which doped region 42 and doped region 44 are ramped down from the peak annealing temperature, or gas flow rate during the anneal may also be adjusted in order to form annealed region 46 and annealed region 48.

[0026] It should be appreciated that adjusting the anneal process based on measurements taken after the spacer etch process, as described above, allows transistors with improved drain saturation currents to be fabricated. A uniform and repeatable lateral diffusion distance for source and drain dopants is achieved by controlling the anneal process. Therefore, uniform and repeatable overlap between the gate electrode and the source and drain regions is achieved, and transistors having improved drain saturation currents are fabricated with the present invention.

[0027] Thus it is apparent that there has been provided, in accordance with the present invention, a method for forming a transistor within an integrated circuit that fully meets the need and advantages set forth previously. Although the invention has been described and illustrated with reference to specific embodiments thereof, it is not intended that the invention be limited to these illustrative embodiments. Those skilled in the art will recognize that modifications and variations can be made without departing from the spirit of the invention. Therefore, it is intended that this invention encompass all such variations and modifications as fall within the scope of the appended claims.