Active matrix type liquid crystal display

[0002] The present invention relates to an active matrix type liquid crystal display using a horizontal electric field system.

[0003] As regards the display of information on a liquid crystal display (hereinafter, referred to as a LCD), an electric field is applied to liquid crystal (hereinafter, referred to as LC) molecules in a LC layer interposed between substrates to thereby change the direction of orientation of the LC molecules, and the display is obtained by a change in the optical quality of the LC layer resulting from the change in the direction of orientation of the LC molecules.

[0004] Particularly, an active matrix type LCD using active elements, which are represented by thin film transistor elements, has been employed as a display terminal of an OA apparatus having lower power consumption, by which the standard CRT will be replaced in terms of a response characteristic capable of coping with moving images at high precision and the like.

[0005] A conventional TN display system of the active matrix type LCD has a disadvantage in that it has a narrow visual field angle, which has posed a problem for the desired replacement of the standard CRT in terms of image quality.

[0006] On the other hand, a system (horizontal electric field system) for displaying information through the use of a change in double refraction properties of a LC by making the direction of an electric field to be applied to the LC, using comb-teeth electrodes, substantially parallel to the substrate surface, has been proposed, for example, in Japanese Patent Publication No. 63-21907 by “R. Kiefer, B. Weber, F. Windcheid and G. Baur, Proceedings of the Twelfth International Display Research Conference (Japan Display 192) pp. 547-550”.

[0007] This horizontal electric field system has advantages, such as wider visual field angle, and lower loading capacity than the conventional TN system, and this technique offers hope as a full-fledged active matrix type LCD capable of replacing the standard CRT.

[0008] As regards how to apply an electric field to the LC, a vertical electric field is applied to a LC layer using solid (transparent) electrodes in the TN system, whereas a horizontal electric field is applied using striped comb-teeth electrodes in the horizontal electric field system. In the horizontal electric field system, since the electric field is applied using comb-teeth-shaped electrodes, there was a problem in that its characteristic property greatly fluctuates depending upon the electrode finish width in the manufacturing process.

[0009] More specifically, in a case where comb-teeth electrodes are formed by a conventional process, when the electrode width varies because of the photo-mask precision, exposure uniformity of photolithography and variations of etching, fluctuation in the electrode interval caused thereby causes variations in the horizontal electric field intensity even if the same voltage is applied between these electrodes, thus causing luminance unevenness on the display surface.

[0010] Further, as regards the electro-optic characteristic including threshold, in the TN system, the electro-optic characteristic does not directly depend upon the electrode interval (=thickness of LC layer) because the interval between a pair of electrodes which apply the electric field to the LC layer coincides with the thickness of the LC layer; whereas, in the horizontal electric field system, changes in the characteristic due to fluctuation of the electrode interval become great because the electro-optic characteristic directly depends thereon independently.

[0011] In the horizontal electric field system, therefore, when the comb-teeth electrode interval fluctuates owing to variations in the electrode finish width, a large shift occurs in the electro-optical characteristic curve, which mainly causes display luminance unevenness.

[0012] In order to solve this problem, a method to secure the above-described electrode finish precision by forming paired electrodes, which apply the horizontal electric field to the LC layer, in the same layer, and by dividing a display surface to combine a small-area high precision photo-process with a stepper, has been proposed by, for example, “Y. Matsutani, S. Tahata, M. Hayashi, T. Onawa, K. Kobayashi, K. Nagata and M. Morishita, (SID97 Digest) pp. 14 to 18”. However, this method is inferior from the point of view of mass production of the display device because the divided photo-process using this stepper takes time, and this is considered to be a serious problem particularly when a large screen is increasingly used for the LCD in the future. As described above, the conventional horizontal electric field system active matrix type LCD has had a problem in that the electrode finish width is susceptible to the influence of the mass production process fluctuation, and surface luminance unevenness resulting from this fluctuation is prone to occur, resulting in inferior mass productivity.

[0013] It is an object of the present invention to provide an active matrix type LCD using the horizontal electric field system, which is excellent in mass producibility, in high image quality and which hardly causes display unevenness resulting from fluctuations in the electrode finish width.

[0014] According to the present invention, an attempt is made to solve the above-stated problems by causing other fluctuation factors at the same time which cancel and compensate for the effect of the electrode interval fluctuations to thereby reduce display luminance unevenness resulting from the electrode interval fluctuations in a horizontal electric field system of a LCD.

[0015] Hereinafter, the relationship between fluctuation factors, which cause display luminance unevenness in the horizontal electric field system, will be described.

[0016] In a translucent LCD element, a display luminance unevenness occurs because of unevenness in the transmission factor, and this is most easily recognized visually at a low transmission factor (relative transmission factor of 10% to 20%) corresponding to a low luminance. Since a transmission factor-voltage (T-V) characteristic in this low transmission factor area is considered to dominate the luminance fluctuation caused by a pixel electrode width fluctuation, we have considered a model in which the T-V characteristic in the low transmission factor area is linearly approximated. That is, the transmission factor-electric field (T-E) characteristic in the low transmission factor area is linearly approximated as follows:

[0017] T(E)=α(E−Eth)

[0018] Eth=(Π/d)(K2/ΔE)

[0019] (Eth is threshold electric field, and is considered to be a constant here). When the horizontal electric field E is further approximated to E=V/1 using a pixel electrode interval 1, the transmission factor-voltage (T-V) characteristic can be expressed as follows:

[0020] T(V)=(α/1)(V−Eth1)

[0021] In this respect, this T-V characteristic model can be considered to be a model obtained by tangent-approximating not only limited to the low transmission factor area, but at any arbitrary point.

[0022] From the above equation, fluctuation (ΔT) in the transmission factor due to minute fluctuation in each parameter is given by: $\begin{array}{cc}\begin{array}{c}\Delta T=\left(\partial T/\partial V\right)\Delta v+\left(\partial T/\partial 1\right)\Delta 1+\left(\partial T/\partial \alpha \right)\Delta \alpha \\ =\left(\alpha /1\right)\Delta V-\left(\alpha V/1^2\right)\Delta 1+\left(\left(V-V-\mathrm{Eth1}\right)/1\right)\Delta \alpha \end{array}& \left(1\right)\end{array}$

[0023] This is a sensitivity analysis equation for each fluctuation factor with respect to total transmission factor fluctuation ΔT. The Δ1 term is a term of fluctuation of the electrode interval 1 due to the pixel electrode width fluctuation which is the matter at issue now, and this becomes the main cause for the transmission factor fluctuation ΔT in the left side, causing the display luminance unevenness. As a method of reducing the transmission factor fluctuation ΔT to decrease the display luminance unevenness, a method can be considered for canceling the fluctuation among a plurality of terms which are factors for the transmission factor fluctuation. If, for example, the LC driving voltage V of the second term of the right side is increased (or decreased) with positive correlation with the electrode interval fluctuation in the first term at the same time, the respective fluctuations will be compensated by each other to reduce the total transmission factor fluctuation. This compensation condition can be expressed by the following equation:

[0024] (V/1)Δ1=ΔV  (2)

[0025] The above equation represents a condition under which the effect of the drop (EΔ1˜(V/1)Δ1) in the horizontal electric field applied to the LC layer due to an increase Δ1 in the pixel electrode interval in the left side is compensated for by a rise ΔV (the same with fluctuation in both in opposite directions) in the effective driving voltage on the right side.

[0026] It has been found that in order to compensate for the influence of such electrode interval fluctuation by the driving voltage fluctuation, it is necessary as a precondition to cause both the driving voltage fluctuation and the electrode interval fluctuation to simultaneously occur with a positive correlation therebetween.

[0027] A method for causing the above-described two fluctuations to simultaneously occur will be described with reference to the drawings.

[0028] FIG. 1 is a conceptual plan view showing one pixel on a thin film transistor (TFT: Thin Film Transistor) substrate side and its surrounding portion in an example of a horizontal electric field system active matrix type LC display element according to the present invention using TFT as an active element. FIG. 2 is a cross-sectional view taken on line 6—6 of FIG. 1. FIG. 3 is a cross-sectional view taken on line 7—7 of FIG. 1. FIG.4 is a cross-sectional view taken on line 8—8 of FIG. 1. As shown in these views, an active matrix type LCD according to the present invention is structured such that one of the common electrode-pixel electrodes, which apply a horizontal electric field to the LC as a pair, is formed as the same layer (SD layer) as the source/drain electrode at the top of this TFT. Also, as shown in FIG. 4, in accordance with the present invention, the charge storage capacity is formed by overlapping the common electrode and the pixel electrode, and the overlap area which determines this storage capacity value is structured to be determined by the pixel electrode side in the SD layer. According to the present invention, the electrodes in the SD layer are structured such that they are collectively, on the entire display surface, formed in an SD process with the same photo-mask. More specifically, according to the present invention, in a case where the electrode finish width of the SD layer fluctuates because of variations in photolithography or etching in the SD process, the LCD is structured such that the pixel common electrode interval, on which the horizontal electric field to be applied to the LC is dependent, the source/drain electrode dimensions, on which the TFT characteristic is dependent, and the overlap area of the pixel common electrode, which determines the storage capacity, simultaneously fluctuate with correlation to one another. With this structure, since the influence of the finish dimension fluctuation of the SD layer on the display characteristic becomes most significant as compared with dimensional fluctuations in the other layers, it is possible to restrain the greater part of the influence of the total electrode dimensional fluctuation by minimizing the influence of the dimensional fluctuation in the SD process.

[0029] In this respect, an electrode having the same layer as the TFT source/drain electrode is not restricted to the pixel electrode in the above-described example, but the common electrode, or the pixel electrode, or both of the common electrodes may be used. In any of these instances, the TFT source/drain electrode dimensions, the storage capacity portion dimension, and the pixel common electrode interval are determined by the same process (photo, etching process), whereby those dimensional fluctuations simultaneously occur with correlation to one another.

[0030] Against the background of the structure of the present invention, we have considered the compensation conditions for transmission factor fluctuation due to the electrode interval fluctuation. The electrode dimensional fluctuation in the SD process causes fluctuation in the effective driving voltage, and if it is exerted in a direction to compensate for the influence of the above-described electrode interval fluctuation, it is considered that as a result, the luminance (transmission factor) fluctuation based on the electrode finish dimensional fluctuation in the SD process can be reduced. Next, a method for causing such an effective driving voltage fluctuation as to cause the above-described compensation due to dimensional fluctuation in the SD process will be described.

[0031] As a mechanism in which the driving voltage varies by dimensional fluctuation in a TFT electrode and the like, as described above, a so-called feed through voltage is known. The feed through voltage refers to a drop in source potential caused by capacity division of a charge which has been maintained at the TFT parasitic capacity immediately after the TFT is turned off. This feed through voltage ΔV_Scan be generally represented by the following equation if it is considered that the influence of recharging due to a delay in the gate pulse, which causes a difference in image quality between the center and both ends of the display surface, is restrained to some degree in the design and is ignored:

[0032] Δ_VS=(1/Ctot){Cgson(V_GH−V_GL)−ΔCgs(V_D−V_GL)}  (3)

[0033] Ctot=Cgsoff+Cstg+ClC

[0034] ΔCgs=Cgson−Cgsoff

[0035] where Cgson and Cgsoff are values of gate-source parasitic capacity during TFT-on or TFT-off, respectively, CLC and Cstg are values of pixel LC capacity and storage capacity, respectively, and V_GH, V_GLand V_Dare high gate pulse potential, low gate pulse potential and drain potential, respectively.

[0036] From the above equations, it can be seen that the feed through voltage is dependent on the high gate pulse potential as viewed from the low gate pulse potential and the drain potential, and is determined by the gate-source parasitic capacity value Cgs of the TFT. As regards Cgs, assuming a Mayer model with a sufficiently high charging ratio (V_CS−V_TH>>V_DS) for the intrinsic parasitic capacity, and MIS type capacity for the overlap capacity, the gate-source parasitic capacity can be expressed as follows:

[0037] Cgson=(W_aCo/2)1g

[0038] Cgsoff={(WCoCa)/(Co+Ca)1_s={(WCo)/2}{(Ca/(Co+Ca)}(1_g−L)

[0039] where L and W are the TFT channel length and width (W is defined as the width of the source electrode which determines Cgsoff here) shown in the cross-sectional view 3 and the plan view 5 of the TFT portion, respectively, and W_ais the width of an amorphous silicon (a-Si) layer which determines Cgson during TFT-on (W_ais determined in the a-Si layer process and not in the SD process).

[0040] 1_sand 1_dare overlaps of the source-drain electrode on the gate electrode portion (width 1_g), respectively, and it is assumed here that both are the same (accordingly, L=1_g−21_s). Co and Ca are capacity per unit area of the gate insulating layer and the a-Si layer, respectively.

[0041] When we consider the relationship between TFT dimensional fluctuation and Cgs fluctuation in the SD process from the above equation, it can be seen that Cgson is not affected by the dimensional fluctuation in the SD process, whereas Cgsoff and ΔCgs vary depending upon the channel length L and width W to be determined in the SD process.

[0042] A description will be made of variations in the effective driving voltage which is caused by fluctuation in the TFT channel dimension. First, in the case of driving with the common electrode potential, whose conceptual driving wave-forms are shown in FIG. 6, fixed, we consider the effective voltage to be actually applied to the LC taking the feed through voltage into consideration. In the case of common-fixed driving, the drain potential is expressed by the following equation correspondingly to positive charging (V_D⁺) and negative charging (V_D⁻) of the video signal voltage V_stg.

[0043] V_D±=±V_SIG+V_D-CENTER

[0044] where, when the driving voltage, which becomes a peak transmission factor in the T-V characteristic of pixels, is set to V_MAX, the video signal voltage V_SIGis inputted approximately within the following range:

[0045] 0(black display)≦V_SIG≦V_MAX(white display)

[0046] (In the horizontal electric field system, white and black in the TN system are reversed).

[0047] The LC driving effective value voltage Vlc varies as shown in the FIG. 6 Driving Voltage Wave-form Diagram through the feed through voltage, and is concretely expressed as follows:

[0048] V_LC={square root over ( )}[{(V_D⁺−ΔV_S⁺−V_COM){circumflex over ( )}2+(V_D⁻−Δ_COM){circumflex over ( )}2}/2]

[0049] where ΔV_S⁺ and ΔV_S⁻ are values of feed through voltage during positive and negative charging, respectively.

[0050] By substituting the equation of V_D± and the following equation into the above equation,

[0051] V_COM=V_D-CENTER−(½)(ΔV_S⁺+ΔV_S⁻)

[0052] V_LC=|V_SIG+(½)(ΔV_S⁻−ΔV_S⁺)|

[0053] is given.

[0054] The second term in the right-hand side represents a change in the driving voltage by contribution of the feed through voltage, and the amount of change is a half of the difference in feed through voltage between that during positive charging and that during negative charging.

[0055] When the feed through voltage ΔV_Sof the equation (3) and the above equation of V_D± are substituted into the above equation, since V_LCsatisfies the relation of V_SIG≧0 and ΔCgs≧0,

[0056] V_LC=V_SIG{1+(ΔCgs/Ctot)}

[0057] is given.

[0058] From this equation, it can be seen that variations in driving voltage based on the feed through voltage in the case of a common-fixed driving are proportionate to ΔCgs/Ctot.

[0059] Next, we consider a case of common AC driving in which the common electrode potential has been converted into AC, which is frequently used as a method of providing the drain driver with low withstand voltage.

[0060] In the common AC driving, the common potential is, as its name indicates, converted into AC at voltage width V_CPPwith V_COMCas the center as follows:

[0061] V_COM±=±(½)V_CPP+V_COMC

[0062] where the center potential V_COMCis given by the following same equation as the common fixation:

[0063] V_COM=V_D-CENTER−(½)(ΔV_S⁺ΔV_S⁻)

[0064] The drain potential at common AC can also be considered as the same shape as at common fixation:

[0065] V_D±=±V_SIG+V_D-CENTER

[0066] The video signal voltage V_SIGin the case of common AC is deflected to the AC converted common potential including also the phase, and therefore, it is considered that V_SIGcan take either a positive or negative value, assuming that positive is antiphase to common and negative is in-phase.

[0067] In the case of causing it to correspond to the equation at a common fixation, it is to be deflected as a common potential amplitude V_CPP=V_MAXwithin the following range:

[0068] −(½)V_MAX(black display)≦V_SIG≦(½)V_MAX(white display)

[0069] That is, since V_SIGcan be deflected both positive and negative as shown in the above equation, the variation width (output width of drain driver) of the drain potential becomes a half of that at the common fixation, although the variation width of V_SIGbecomes the same V_MAXas at common fixation.

[0070] In actual common AC driving, in order to further reduce the variation width of the drain potential, the voltage applied to the pixel is not deflected from 0V as described above, but is deflected from threshold V_THof the T-V characteristic of pixels.

[0071] In other words, by increasing the common potential amplitude by V_TH, we get V_CPP=V_MAX+V_TH. This portion, that is,

[0072] −(½)(V_MAX−V_TH)(black display)≦V_SIG≦(½)(V_MAX−V_TH) (white display)

[0073] and the variation width of drain potential can be further decreased by V_THinto V_MAX−V_TH.

[0074] After all, the effective value voltage V_LCfor LC driving at common AC is represented by:

[0075] V_LC={square root over ( )}[{(V_D⁺−ΔV_S⁺−V_COM−){circumflex over ( )}2+((V_D⁻−ΔV_S⁻V_COM+){circumflex over ( )}2}/2]

[0076] By substituting the equations concerning the above-described V_COMCand V_D± the following equation can be obtained:

[0077] V_LC=(½)|2V_SIG+V_CPP+V_S⁻ΔV_S⁺|

[0078] As regards the feed through voltage during common AC driving, taking into consideration that the gate potential is also converted into AC by the foregoing equation of ΔV_sat common AC,

[0079] ΔV_S⁺=(1/Ctot){Cgson(V_GH⁻−V_GL⁻)−ΔCgs(V_D⁺−V_GL⁻)}

[0080] ΔV_S⁻=(1/Ctot){Cgson(V_GH⁺−V_GL⁺)−ΔCgs(V_D⁻−V_GL⁺)}

[0081] are given.

[0082] By substituting the above equation into the equation of V_LC, the following equation is given:

[0083] V_LC=(½)|2V_SIG+V_CPP+(Cgson/Ctot) (V_GH⁺−V_GL⁻−V_GH⁻+V_GL⁻) +(ΔCgs/ctot)(V_D⁺−V_D⁻+V_GL⁺−V_GL⁻)

[0084] When it is considered that the gate low potential is AC converted in the same phase and in the same amplitude as the common potential and a gate pulse having amplitude V_CPPis superposed thereon, the AC-conversion of the foregoing gate potential is represented by the following equations:

[0085] V_GL±=±(½)V_CPP+V_GLC

[0086] V_GH±=V_GPP+V_GL±

[0087] That is, the gate pulse wave-form becomes a 4-value AC wave-form.

[0088] When these are substituted, the term Cgson disappears in the above equation of V_LC, and when the equation of V_D± is further substituted, after all V_LCis:

[0089] V_LC=V′_SIG{1+(Δcgs/ctot)}

[0090] and the following equation is given:

[0091] V′_SIG=V_SIG+V_CPP/2

[0092] Since V′_SIG=V_SIG+V_CPP/2 corresponds to the V_SIGat common fixation in the above equation, this equation is considered to be equivalent to the corresponding equation at common fixation after all.

[0093] Accordingly, as regards effective driving voltage fluctuation caused by dimensional fluctuation in the SD process during common AC driving (hereinafter, called “full common AC driving”) in which such gate pulses as described above for both low and high are AC converted in the same manner, it is considered to be the same as at common fixation in the preceding paragraph.

[0094] On the other hand, in the common AC driving actually used with the products, the gate low potential is AC-converted in almost all cases in the same manner as described above, but as regards the gate high potential, a method using a fixed gate pulse is used because the withstand voltage of the gate driver can be kept low and the circuit can be simplified.

[0095] In this case, the gate pulse wave-form is represented by the following equation:

[0096] V_GL±=±(½)V_CPP+V_GLC

[0097] V_GH±=V_GPP

[0098] In other words, the gate high potential is not changed, but becomes constant by positive/negative charging, and the gate pulse wave-form becomes a 3-value AC wave-form.

[0099] When the foregoing gate pulse wave-form is substituted into the equation of V_LC, the Cgson term does not disappear, but remains in this case, and V_LCis represented by the following equation:

[0100] V_LC=V′_SIG[1+(ΔCgs/Ctot)−(Cgson/Ctot){V_CPP/ (2V_SIG+V_CPP)

[0101] The Cgson term newly added in the above equation is caused by a difference (the same as in the case of the foregoing full common AC driving) in the falling width of the gate pulse during positive/negative charging.

[0102] Summarizing the foregoing results, the effective driving voltage for both common fixation and common AC driving is represented by the following equation generalized:

[0103] V_LC=V′_SIG{1+(ΔC′gs/Ctot)

[0104] In the common-fixed driving,

[0105] V′_SIG=V_SIG,ΔC′gs=Cgs

[0106] In the full common AC driving, in which both the gate low potential and the gate high potential have been AC-converted,

[0107] V′_SIG=V_SIG+V_CPP/2

[0108] ΔC′gs=ΔCgs

[0109] In the ordinary common AC driving, in which only the gate low potential has been AC-converted,

[0110] V′_SIG=V_SIG+V_CPP/2

[0111] $\begin{array}{c}\Delta C^{\prime }\mathrm{gs}=\Delta \mathrm{Cgs}-\left\{V_{\mathrm{CPP}}/\left(2V_{\mathrm{SIG}}+V_{\mathrm{CPP}}\right)\right\}\mathrm{Cgson}\\ =\left(V_{\mathrm{SIG}}/V_{\mathrm{SIG}}\right)\mathrm{Cgson}-\mathrm{Cgsoff}\end{array}$

[0112] are given.

[0113] In the ordinary common AC driving, in which only the gate low potential has been AC-converted (while ΔC′gs=ΔCgs>0 in the common-fixed and full common AC driving), the last equation indicates that the effective value of ΔC′gs varies through the visual signal potential V_SIGso that it may become ΔC′gs<0 (at low luminance).

[0114] The means according to the present invention described so far will be re-confirmed here. A horizontal electric field system of the active matrix type LC display element according to the present invention is structured such that the TFT channel dimensions L, W, pixel electrode interval 1 and a stored capacity formation portion area S are formed by the same source/drain (SD) process, and the dimensional fluctuations due to fluctuation in the SD process condition occur with correlation to one another simultaneously

[0115] Concretely, when an one-side retreat amount from the design value of a finish value for the pixel electrode width in the SD process is set to Δ1, the pixel electrode interval 1, which is an interval with the common electrode in the gate/common (GC) layer in FIG. 2, is to be changed by Δ1.

[0116] On the other hand, the one-side retreat amount Δ1 in the foregoing SD process causes a fluctuation of ΔL=2Δ1 in the TFT channel length L and fluctuation of ΔW=−2Δ1 in the channel width W when the contribution of both electrodes, source/drain, is taken into consideration.

[0117] Further, the electrode finish width fluctuation in the SD process causes a change (by Δl) of the LC pixel capacity Clc contained in Ctot in the equation of the effective driving voltage V_LC, and a change based on a change ΔS in the overlap area S of the storage capacity C_stg, which is formed by the overlap of the pixel/common electrodes, and a change in the effective driving voltage caused by them is given by the following equation:

[0118] ΔV_LC(ΔL, ΔW, Δ1, ΔS) =∂V_LC/∂LΔL+∂V_LC/∂WΔW+∂V_LC/∂1Δ1+∂V_LC/∂SΔS

[0119] ={(∂ΔC′gs/∂L)(∂V_LC/∂ΔC′gs+(∂ΔCtot/∂L)(∂V_LC/∂Ctot)}(2Δ1+

[0120] {(∂ΔC′gs/∂W)(∂V_LC/∂ΔC′gs)+(∂Ctot/∂W)(∂V_LC/∂Ctot)}(−2Δ1)+{(∂Ctot/∂1)(2V_LC/∂Ctot)}Δ1+(∂Ctot/∂

[0121] S)(∂V_LC/∂Ctot)}{−2(1+A)1_st}Δ1=[(∂ΔC′gs/∂L−∂ΔC′gs/∂W)(∂V_LC/∂ΔC′gs)+{∂Ctot/∂L−∂Ctot/∂W+(½

[0122] ∂Ctot/∂1−(1+a)1_st(∂Ctot/∂S)}(∂V_LC/∂Ctot)]2Δ1

[0123] In the above equation, we have considered that the shape of an electrode overlapped portion, which forms the storage capacity C_stg, is a rectangle having a short side 1_stand a long side a 1_stand set a change ΔS in the area of this portion due to the one-side retreat amount Δ1 to the following equation (the second term of Δ1 is ignored).

[0124] Δs=(_st−2Δ1)(a1_st−2Δ1)−a_1st{circumflex over ( )}2˜−2(1+a)1_stΔ1

[0125] When this equation is substituted into an equation (2) for compensation condition obtained by sensitivity analysis,

[0126] V_LC/1 =2[(∂ΔC′gs/∂L−∂ΔC′gs/∂W)(∂V_LC/∂ΔC′gs)]+{∂Ctot/∂L−Ctot/∂W+(½)∂Ctot/∂1−(1+a)1_st(∂Ctot/∂S)}(∂V_LC/∂Ctot)]

[0127] By evaluating each partial differential term in the above equation to rewrite it using 1_totwhose definition will be indicated later, the following equation can be obtained as an equation for a compensation condition after all:

[0128] (1/1){1+(ΔC′gs/Ctot)}=(1/Ctot)(Cgsoff/1_s+2Cgsoff/W+ΔC′gs/1_tot)  (4)

[0129] The left-hand side of the above equation is a term for pixel electrode interval fluctuation while the right-hand side is a term for driving voltage fluctuation resulting from the feed through voltage, and the above equation indicates the condition on which these two contributions compensate for each other (within a range of minute fluctuation) so that total transmission factor fluctuation is apparently nullified.

[0130] Further, the physical meaning of each term of the above equation will be described. The first term on the left-hand side is a pixel electrode interval fluctuation term, and the second term is a correction term resulting from a change in the effective driving voltage due to the feed through voltage.

[0131] Since normally ΔC′gs<<Ctot, this correction term is an amount which can be substantially ignored as compared with the first term on the left-hand side.

[0132] On the other hand, as regards each term of the driving voltage fluctuation on the right-hand side, the first and second terms in the right-hand side are a contribution of changes in TFT channel length L and width W, respectively, the third term is a term for a change in off-state total loading capacity Ctot, and 1/1_tot, which is a coefficient of the change, is defined by the following equation.

[0133] 1/1_tot=(1/Ctot)[Cgsoff/1_s+2Cgsoff/W+Clc/1+2{(1+a)/a}Cstg/1_st]

[0134] Actually, the greater part of this term 1/1_totis a fluctuation term for the storage capacity Cstg, which is the last term.

[0135] The coefficient of the fluctuation term (the last term on the right-hand side of the above equation) of this storage capacity is determined by a rate of change, per one-side retreat amount Al of the electrode, of the area S of the electrode overlapped portion, which forms the storage capacity:

[0136] (ΔS/S)/Δ1˜−2(1+a)1_st/{a1_st{circumflex over ( )}2}=−2{(1+a)/a}/1_st

[0137] This coefficient (ΔS/S)/Δ1 varies depending upon the shape of the foregoing electrode overlapped portion.

[0138] We have considered a case where the shape of, for example, the storage capacity formation portion is changed and the long side of the foregoing rectangle is divided into N equal parts and separated to form a storage capacity.

[0139] In this case, the total area is not changed, but the storage capacity is to be formed by n rectangles each having an area S′=1_st(a/N)1_st.

[0140] In this case, the coefficient (ΔS/S)/Δ1 is given by:

[0141] (ΔS/S)Δ1={NΔS′/(NS′)}/Δ1=−N(1+a/N)1_st/(N(a/N)1_st{circumflex over ( )}2}=−2{1+(a/N)}/{(a/N)1_st)

[0142] and it is found that the term Cstg remains unchanged, “a” can be apparently made larger by a portion which has become a/N, ΔSIS)/Δ1, and as a result, 1/1_totcan be made large by the shape effect of the storage capacity.

[0143] We have considered the foregoing compensation condition for each of the respective driving methods.

[0144] First, we have considered the full common AC driving in which both common fixation and gate high/low have been AC-converted. Since ΔC′gs=ΔCgs and ΔCgs>0, the three terms for driving voltage fluctuation on the right-hand side are all positive, and all always exert an effect in a direction to compensate for the image electrode interval fluctuation on the left-hand side.

[0145] Also, in the case of the common fixation and full common AC driving, the equation for compensation condition does not depend upon the driving voltage condition (actually the pixel capacity Clc in the Ctot has dependence on the driving voltage ClC (V_LC)) as a matter of form.

[0146] In the case of the common AC driving, in which only the gate low potential has been AC-converted, which is normally used, ΔC′gs contains a direct driving voltage parameter V_SIG/V′_SIGunlike the above-described case, and therefore, it has a direct dependence on the image signal voltage.

[0147] From within the range of the video signal voltage during the foregoing common AC driving:

[0148] V_CPP=V_MAX+V_TH, −(½)(V_MAX−V_TH)(black display)≦V_SIG≦(½(V_MAX−V_TH)(white display),

[0149] and

[0150] V_TH≦V_SIG≦V_MAX

[0151] This parameter V_SIG/V′_SIGhas a negative value on the low transmission factor side, in which luminance unevenness poses a problem. In this case, therefore, the parameter V_SIG/V′_SIGis given in the equation (4) for compensation condition, by the following equation on the right-hand side thereof:

[0152] ΔC′gS=(V_SIG/V′_SIG)Cgson−Cgsoff<0

[0153] Therefore, in the case of the ordinary common AC driving, since on the low transmission factor side, the third term (fluctuation term for total loading capacity) on the right-hand side of the above-described equation for compensation condition normally becomes a negative term with nearly the same magnitude as the first or second term on the right-hand side, it is considered that in most cases, the three terms in the right-hand side cancel one another out so that the total on the right-hand side does not become great enough to compensate for the influence of the pixel electrode interval fluctuation on the left-hand side, or that the entire right-hand side becomes negative so that it does not tend to compensate for the left-hand side, but to increase conversely.

[0154] At this time, the correction term for the electrode interval fluctuation term of the second term on the left-hand side also becomes negative, and exerts an influence in a direction to reduce the transmission factor fluctuation caused by its influence, but the effect of this correction term is relatively small as described above, and the influence of the above-described driving voltage compensation which does not effectively work is by far greater.

[0155] It has been found that the common AC driving normally used for the above-described reasons is more disadvantageous in principle than the common fixation and the full common AC driving in planning to enlarge the SD process dimensional fluctuation margin using the driving voltage compensation with the above-described structure.

[0156] Accordingly, with the structure according to the present invention described so far, the pixel electrode interval, the TFT channel dimension and the storage capacity portion dimension are simultaneously formed in the SD process. In a case where the electrode finish width fluctuates in the SD process, when the pixel-common electrode interval 1 on which the horizontal electric field to be applied to the LC is dependent, the TFT channel dimension on which the effective driving voltage is dependent, and the storage capacity portion area simultaneously fluctuate with correlation to one another, their driving methods are set to the full common AC driving in which the common-fixed driving or both high and low gate pulses have been AC-converted, whereby it is possible to cause a change in the effective driving voltage caused by dimensional fluctuation to necessarily act in a direction to compensate for a change in the optical quality caused by a dimensional change of the electrode to which the horizontal electric field is applied so that the compensation operation can be effectively and reliably performed.

[0157] On the basis of the compensation effect described above, when comparing display luminance unevenness in a case where low luminance (10 to 20% relative luminance of maximum luminance), in which display unevenness is most conspicuous, is displayed by causing the TFT to be normally on with the gate voltage on all of the display surface, or all-pixel TFT of a LCD according to the present invention equal to or higher than the threshold, with that in a case where the same luminance is displayed on the same entire display surface by temporally turning on/off the TFT in the same manner as an actual state of use, the display luminance unevenness can be more noticeably improved in the latter in which the compensation effect acts than in the former in which the compensation effect does not act.

[0158] After further studying various ways, it has been found that in order to obtain the same display uniformity for substantially the same conditions as the method for securing electrode finish dimension precision by a combination of small-area high precision photo-process described in the prior art using a stepper, the reduction ratio of the display luminance unevenness can be set to 20% or more.

[0159] According to the present invention as described above, there can be provided a horizontal electric field system active matrix LCD which is less influenced by the mass production process fluctuation of the electrode finish width, and in which display luminance unevenness resulting from this fluctuation will hardly occur, and which is excellent in mass producibility and in high image quality. FIG. 19 is a view illustrating the general structure of the present invention.

[0160] It is composed of a scanning electrode driving circuit 18 for driving a scanning electrode; a signal electrode driving circuit 19 for driving a signal electrode; a control circuit 17 for controlling the scanning electrode driving circuit 18 and the signal electrode driving circuit 19; a common electrode driving circuit 20 for driving a common electrode; and a LC panel portion 21. The LC display panel 21 is composed of thin film semiconductor (TFT); a LC capacity portion Clc; and a storage capacity portion Cstg at each intersection between a signal line for transmitting a signal by the control of the signal electrode driving circuit 19 and the scanning lines of the scanning electrode driving circuit 18.

[0161] FIG. 1 is a partial plan view showing one pixel, and its surrounding portion, of a LC display portion in an active matrix type color LCD according to a first embodiment of the present invention;

[0162] FIG. 2 is a cross-sectional view showing a pixel taken on line 6—6 of FIG. 1;

[0163] FIG. 3 is a cross-sectional view showing a thin film transistor element TFT taken on line 7—7 of FIG. 1;

[0164] FIG. 4 is a cross-sectional view showing stored capacity Cstg taken on line 8—8 of FIG. 1;

[0165] FIG. 5 is an enlarged plan view showing a surrounding portion of the thin film transistor element TFT of FIG. 1;

[0166] FIG. 6 is a waveform diagram showing an example of the driving wave-form in an active matrix type color LCD according to the present invention;

[0167] FIG. 7 is a plan view illustrating the structure of a matrix surrounding portion of a display panel;

[0168] FIG. 8 is a cross-sectional view showing a gate signal terminal on the left side, and a panel edge portion without external connecting terminals on the right side;

[0169] FIG. 9(A) is a plan view and FIG. 9(B) is a cross-sectional view showing the vicinity of a connecting portion between a gate terminal GTM and gate wiring GL;

[0170] FIG. 10(A) is a plan view and FIG. 10(B) is a cross-sectional view showing the vicinity of a connecting portion between a drain terminal DTM and a drain signal line DL;

[0171] FIG. 11(A) is a plan view and FIG. 11(B) is a cross-sectional view showing the vicinity of connecting portions between a common electrode terminal CTM1, common bus line CB1 and common voltage signal line CL;

[0172] FIG. 12(A) is a plan view and FIG. 12(B) is a cross-sectional view showing the vicinity of connecting portions between a common electrode terminal CTM2, common bus line CB2 and common voltage signal line CL;

[0173] FIG. 13 is a circuit diagram showing a matrix portion and its surrounding portion of the active matrix type color LCD according to the present invention;

[0174] FIG. 14 is a part of a flow chart in a cross-sectional view for a pixel portion and a gate terminal portion showing manufacturing processes A to C on the substrate SUB1 side;

[0175] FIG. 15 is a part of the flow chart of FIG. 14 in a cross-sectional view for a pixel portion and a gate terminal portion showing manufacturing processes D to E on the substrate SUB1 side;

[0176] FIG. 16 is a part of the flow chart of FIG. 14 in a cross-sectional view for a pixel portion and a gate terminal portion showing manufacturing process G on the substrate SUB1 side;

[0177] FIG. 17 is a top view showing a state in which a surrounding driving circuit is packaged on a LC display panel;

[0178] FIG. 18 is an exploded perspective view showing a LC display module; and

[0179] FIG. 19 is a schematic diagram showing the general structure of the present invention.

[0180] Hereinafter, a description will be made of an embodiment in which the present invention is applied to an active matrix system color LCD. In this respect, in the following drawings to be described, those elements having the same function are designated by identical reference numerals and a repeated description thereof may be omitted.

[0181] (First Embodiment)

[0182] FIG. 1 is a plan view showing one pixel and its surrounding portions of an active matrix system color LCD of the present invention. As shown in FIG. 1, each pixel is arranged within an intersecting area (within an area enclosed by four signal lines) of a gate signal line (scanning signal line or horizontal signal line) GL, an opposed voltage wiring (common voltage signal line) CL and two adjacent drain signal lines (video signal line or vertical signal line) DL. Each pixel contains a thin film transistor TFT, a storage capacity Cstg, a pixel electrode PX and a common electrode CT. The gate signal line GL and the opposed voltage signal line CL extend in the lateral direction in the figure, and a plurality of lines are arranged in the vertical direction. The drain signal lines DL extend in the vertical direction, and a plurality of lines are arranged in the lateral direction. The pixel electrode PX is electrically connected to the thin film transistor TFT through the source electrode SD1, and the opposed electrode CT is also electrically connected to the opposed voltage signal line CL. The gate signal line GL is used to transmit a gate signal to the thin film transistor element of each pixel, the drain signal line DL is used to supply a drain signal voltage to the pixel electrode PX of each pixel through the thin film transistor element, and the common voltage signal line CL is used to supply a common voltage to the common electrode CT of each pixel.

[0183] The pixel electrode PX and the common electrode CT are opposed to each other, and an electric field substantially parallel to the substrate surface, which is generated between each pixel electrode PX and the common electrode CT, controls an optical state of the LC to control the display. The pixel electrode PX and the common electrode CT are constituted in a comb-teeth shape to become long and slender electrodes in the vertical direction in the figure.

[0184] In the present embodiment, the number of common electrodes CT within one pixel is three, and the number of pixel electrodes PX is two. However, their numbers are not restricted to these, but the number 0 (number of comb teeth) of the common electrodes CT within one pixel and the number P (number of comb teeth) of the pixel electrodes PX can be constituted so that the relation of 0=P+1 is satisfied.

[0185] In this respect, the electrode interval between the pixel electrode PX and the common electrode CT is changed depending upon the LC material being used. This is because, since the electric field intensity, which attains the maximum transmission factor, differs depending upon the LC material, the electrode interval is determined in response to the LC material, and the maximum transmission factor can be obtained within a range of the maximum amplitude of signal voltage which is set by the withstand voltage in the drain signal driving circuit (signal-side driver).

[0186] As shown in FIGS. 2 to 4, with reference to the LC composition layer LC, the thin film transistor TFT, the storage capacity Cstg and an electrode group are formed on the side of the lower transparent glass substrate SUB1, and the color filter FIL and a light-shielding black matrix pattern BM are formed on the side of the upper transparent glass substrate SUB2.

[0187] On the surface of the respective inside (LC side) of the transparent glass substrates SUB1, SUB2, there are provided an orientation film ORI1, ORI2 for controlling the initial orientation of the LC, and on the surface of the respective outside of the transparent glass substrates SUB1, SUB2, there are provided polarizing plates POL1, POL2.

[0188] First, a detailed description will be made of the structure of the lower transparent glass substrate SUB1 side (TFT substrate).

[0189] The thin film transistor TFT operates such that when a positive bias is applied to the gate electrode GT, the source-drain channel resistance becomes smaller, and when the bias is reduced to 0, the channel resistance becomes greater.

[0190] The thin film transistor TFT has, as shown in FIG. 3, an i type semiconductor layer AS consisting of gate electrodes GT, an insulating film GI, “i” type (intrinsic conductive decisive impurity is not doped) amorphous silicon (Si), and a pair of a source electrode SD1 and a drain electrode SD2. In this respect, the source/drain are originally determined by a bias polarity therebetween, and the polarity is reversed during operation in the circuit of this LCD. Therefore, the source/drain replace each other during operation. For the sake of simplicity in the following description, they are expressed by fixing one as the source and the other as the drain.

[0191] The gate electrode GT is formed so as to continue to the gate signal line GL, and is constituted such that a part of the region of the gate signal line GL belongs to the gate electrode GT. The gate electrode GT is a part beyond the active region of the thin film transistor TFT. In this example, the gate electrode GT is formed by a single layer of conductive film g3. For the conductive film g3, chrome-molybdenum alloy (Cr—Mo) film formed by, for example, sputtering is used, but the conductive film is not restricted thereto. Also, two layers of different types of metal may be formed.

[0192] The gate signal line GL is constituted by conductive film g3. The conductive film g3 of this gate signal line GL is formed in the same manufacturing process as the conductive film g3 of the gate electrode GT, and is integrally constituted. Through this gate signal line GL, gate voltage Vg is supplied to the gate electrode GT from an external circuit. In this example, for the conductive film g3, chrome-molybdenum alloy (Cr—Mo) film formed by, for example, sputtering is used. Also, the gate signal line GL and the gate electrode GT are not restricted to only a chrome-molybdenum alloy, but, for example, in order to provide low resistance, a two-layer structure comprising aluminum or aluminum alloy wrapped in chrome-molybdenum may be adopted. Further, a portion, which intersects the drain signal line DL, is made small to reduce the probability of short-circuit with the drain signal line DL, and it may be forked into two branches so that it can be cut off by a laser trimming cutter even if short-circuited.

[0193] The opposed voltage signal line CL is constituted by conductive film g3. The conductive film g3 of this opposed voltage signal line CL is formed in the same manufacturing process as the conductive film g3 of the gate electrode GT, the gate signal line GL and the common electrode CT, and is integrally formed with the common electrode CT. Through this opposed voltage signal line CL common voltage V_COMis supplied to the common electrode CT from an external circuit. Also, the opposed voltage signal line CL is not restricted to only a chrome-molybdenum alloy, but, for example, in order to provide low resistance, a two-layer structure comprising aluminum or an aluminum alloy wrapped in chrome-molybdenum may be adopted. Further, a portion, which intersects the drain signal line DL, is made small to reduce the probability of a short-circuit with the drain signal line DL, and it may be forked into two branches so that it can be cut off by a laser trimming cutter even if short-circuited.

[0194] The insulating film GI is, in a thin film transistor TFT, used as a gate insulating film to impart an electric field to the semiconductor layer AS together with the gate electrode GT. The insulating film GI is formed on the upper layer of the gate electrode GT and the gate signal line GL. For the insulating film GI, a silicon nitride film formed by, for example, plasma CVD is selected, and is formed to a thickness of 2000 to 4500 Å (in the present embodiment, about 3500 Å). The insulating film GI is also used as an interlaminar insulating film for the gate signal line GL, the opposed voltage signal line CL and the drain signal line DL, and contributes to their electric insulation.

[0195] The “i” type semiconductor layer AS is of amorphous silicon, and is formed to a thickness of 150 to 2500 Å (in the present embodiment, film thickness of about 1200 Å). A layer do is a N(+) type amorphous silicon semiconductor layer obtained by doping phosphorus (P) for ohmic contact, and is interposed between the “i” type semiconductor layer AS on the lower side and the conductive layer d3 on the upper side.

[0196] The “i” type semiconductor layer AS and the layer d0 are also provided between both cross-over portions, which are between the gate signal line GL and the opposed voltage signal line CL, and the drain signal line DL. The “i” type semiconductor layer AS at the cross-over portion reduces the possibility of a short-circuit between the gate signal line GL and the opposed voltage signal line CL at the cross-over portion, and the drain signal line DL.

[0197] Each of the source electrode SD1 and the drain electrode SD2 is constituted by conductive film d3 which is in contact with the N(+) type semiconductor layer d0.

[0198] The conductive film d3 is formed to a thickness of 500 to 3000 Å (in the present embodiment, about 2500 Å) using a chrome-molybdenum alloy (Cr—Mo) film formed by sputtering. Since it is subjected to low stress, the Cr—Mo film can be formed to have a comparatively large film thickness, which contributes to a wiring with low resistance. The Cr—Mo film has excellent adhesive properties with the N(+) type semiconductor layer d0. For the conductive film d3, a high-melting point metal (Mo, Ti, Ta, W) film and a high-melting point metal silicide (MOSi₂, TiSi₂, TaSi₂, WSi₂) film may be used in addition to the Cr—mo film, and a laminated structure with aluminum or the like may be adopted.

[0199] The drain signal line DL is constituted by the same layer of conductive film d3 as the source electrode SD1 and the drain electrode SD2. The drain signal line DL is integrally formed with the drain electrode SD2. In this example, the conductive film d3 is formed to a thickness of 500 to 3000 Å (in the present embodiment, about 2500 Å) using a chrome-molybdenum alloy (Cr—Mo) film formed by sputtering. Since it is subjected to low stress, the Cr—Mo film can be formed to have a comparatively large film thickness, which contributes to a wiring with low resistance. The Cr—Mo film has excellent adhesive properties with the N(+) type semiconductor layer d0. For the conductive film d3, a high-melting point metal (Mo, Ti, Ta, W) film and a high-melting point metal silicide (MOSi₂, TiSi₂, TaSi₂, WSi₂) film may be used in addition to the Cr—mo film, and a laminated structure with aluminum or the like may be adopted.

[0200] The conductive film d3, which forms the storage capacity Cstg, is formed to overlap the opposed voltage signal line CL in the source electrode SD1 portion of the thin film transistor TFT. This overlap is, as will be clear from FIG. 5, formed in the same manufacturing process with the source electrode SD1 (d3) as one electrode, and is integrally formed with the pixel electrode PX to constitute the storage capacity (electrostatic capacity element) Cstg having a common voltage signal CL as the other electrode. The dielectric film of this storage capacity Cstg is constituted by the insulating film GI which is used as the gate insulating film for the thin film transistor TFT.

[0201] As shown in FIG. 1, the storage capacity Cstg is formed on a part of the opposed voltage signal line CL as viewed plane-wise.

[0202] A protective film PSV1 is provided on the thin film transistor TFT. The protective film PSV1 is formed to mainly protect the thin film transistor TFT from humidity and the like, and a protective film having high transparence and yet excellent humidity resistance is used. The protective film PSV1 is formed by a silicon oxide film or silicon nitride film which is formed by, for example, a plasma CVD apparatus, and is formed to have thickness of 0.1 to about 1 μm.

[0203] The protective film PSV1 is removed so as to expose the external connecting terminals DTM, GTM. As regards the relationship in thickness between protective film PSV1 and insulating film GI, the former is made thicker in consideration of the protection effect, while the latter is made thinner in consideration of the mutual conductance of the transistor.

[0204] Also, it may be possible to adopt a laminated structure with a thick film constituted by an organic film such as polyimide for the protective film PSV1.

[0205] The pixel electrode PX is formed in the same manufacturing process as the source electrode SD1, and is also integrally formed with the source electrode SD1, and the conductive film d3 of a storage capacity formation portion.

[0206] The common electrode CT is integrally formed with the opposed voltage signal line CL.

[0207] The common electrode CT is constituted such that common voltage V_COMis applied thereto. In the present embodiment, the common voltage V_COMis set to a potential lower by feed through voltage ΔVs, which occurs when the thin film transistor element TFT is set to the off state, than an intermediate DC potential between driving voltage V_DMINat the minimum level to be applied to the drain signal line DL and the driving voltage V_DMAXat the maximum level.

[0208] This common potential is made to have a constant potential temporally in order to exhibit an effect of compensating for the influence of dimensional fluctuation according to the present invention.

[0209] Reverting to FIGS. 1 and 2, a detailed description will be made of the structure of the upper transparent glass substrate SUB2 side (color filter substrate).

[0210] On the side of the upper transparent glass substrate SUB2, a light shielding film BM (so-called black matrix) is formed like the BM borderline shown in FIG. 1 so as to prevent transmission light from a unnecessary gap portion (gap other than between pixel electrode PX and common electrode CT) from emitting on the display surface side to deteriorate the contrast ratio or the like. The light-shielding film BM also plays a role to prevent external light or back light from being incident on the “i” type semiconductor layer AS. More specifically, the “i” type semiconductor layer AS of the thin film transistor TFT is sandwiched between the light-shielding film BM and a slightly large gate electrode GT, which are located on the upper and lower sides thereof, respectively, so that the layer AS is not exposed to external natural light or the back light.

[0211] The light-shielding film BM, as shown in FIG. 1, indicates only one pixel, but is formed such that the inside is opened for each of all pixels. This pattern is an example. In a portion of the comb-teeth electrode at the end portion in which the electric field direction is disturbed, the display for the portion corresponds to video information within the pixel in a one-to-one relationship, and since black is displayed if black, and white is displayed if white, it can be utilized as a part of the display.

[0212] However, the light-shielding film BM must have shielding properties against light. Particularly, the gap between the pixel electrode PX and the common electrode CT requires an optical density of 3 or higher in order to suppress crosstalk (longitudinal smear) in the drain signal line direction. It may be formed by metal having an electrical conductivity, such as Cr, and it is preferably formed by a film having a high level of insulation characteristics so as not to affect the electric field between the pixel electrode PX and the common electrode CT. In the present embodiment, the film is formed to a thickness of about 1.2 μm by mixing black organic pigment with resist material.

[0213] Also, in order to improve the shielding properties against light, carbon or titanium oxide (Tix0y) may be mixed within such a range as to be able to maintain 108 Ωcm or more at which the insulation characteristics do not affect the electric field within the LC composition layer.

[0214] The light-shielding film BM also plays a role to make the contour of pixels of each line clear because effective display areas for each line are partitioned thereon.

[0215] The light-shielding film BM is formed in a picture-frame shape also at the surrounding portion, and is formed such that its pattern continues to the pattern of the matrix portion shown in FIG. 1. The light-shielding film BM at the surrounding portion extends outside a sealed portion SL to prevent leakage light of reflected light or the like resulting from a packaged apparatus such as a personal computer from entering the matrix portion, and also to prevent light such as back light from leaking outside the display area. On the other hand, this light-shielding film BM rests about 0.3 to 1.0 mm inside the edge of the substrate SUB2, and is formed so as to avoid the cut area of the substrate SUB2.

[0216] A color filter FIL is formed in a stripe-shape with red-green-blue repeated in a position opposed to the pixel. The color filter FIL is formed so as to overlap the light-shielding film BM portion.

[0217] The color filter FIL can be formed as follows: First, dyeing base material such as an acrylic resin is formed on the surface of the upper transparent glass substitute SUB2, and dyeing base material other than a red filter formation area is removed by the photolithography technique. Thereafter, the dyeing base material is colored with red pigment, and a fixing process is performed to form a red filter R. By performing a similar process, a green filter G and a blue filter B are formed in order. In this respect, dye may be used for dyeing.

[0218] An overcoat film OC is provided in order to prevent dye of the color filter FIL from leaking to LC composition layer LC, and to flatten a difference in level due to the color filter FIL and the light-shielding film BM. The overcoat film OC is formed by a transparent resin material such as, for example, an acrylic resin and epoxy resin. Also, as the overcoat film OC, an organic film of polyimide or the like, which is excellent in fluidity may be used.

[0219] Next, a description will be made of the LC layer, orientation film, a polarizing plate and the like.

[0220] As the LC composition, there is used a nematic LC having a positive dielectric constant anisotropism Δε of 13.2 and a refractive index anisotropism Δn of 0.081 (589 nm, 20° C.). The thickness (gap) of the LC composition layer is 3.8 μm, and the retardation Δn.d is 0.31 μm. This value for retardation Δn.d is set within a range of 0.25 μm and over to 0.35 μm incl. preferably within a range of 0.28 μm and over to 0.32 μm incl. When the orientation film and a polarizing plate to be described later are combined and the LC molecules are rotated 45° in the electric field direction from the initial orientation direction, it is possible to obtain the maximum transmission factor, and to obtain transmission light having hardly any dependency on wavelength within the range of visible light.

[0221] The thickness (gap) of the LC composition layer is controlled by a polymer bead subjected to a vertical orientation process. This control stabilizes the orientation of the LC molecules around the bead when black is displayed, thus obtaining an excellent black level, and improving the contrast ratio.

[0222] In this respect, the LC material is not particularly restricted, but the dielectric constant anisotropism Δε may be negative. The higher the dielectric constant anisotropism Δε, the more the driving voltage can be lowered, and the lower the refractive index anisotropism An, the more the thickness (gap) of the LC layer can be increased, the filling time for LC can be shortened, and variations in gap can be reduced.

[0223] As regards the resistivity of the LC composition, a composition having resistivity of 109 Ωcm and over to 1014 Ωcm incl., preferably 1011 Ωcm and over to 1013 Ωcm incl. is used. In this system, even if the resistance of the LC composition is low, voltage charged between the pixel electrode and the common electrode can be sufficiently maintained, and its lower limit is 109 Ωcm, preferably 1011 Ωcm. This is based on the fact that the pixel electrode and the common electrode are constituted on the same substrate. Also, since it is difficult to lessen the static electricity which enters the manufacturing process when the resistance is too high, the lower limit is 1014 Ωcm or less, preferably 1013 Ωcm or less.

[0224] For the orientation film OR1, a polyimide is used. The initial orientation directions RDR in the upper and lower substrates are made parallel to each other. As a method for imparting the initial orientation direction, rubbing is most generally used, but there is an oblique deposition in addition. FIG. 18 shows the relationship between the initial orientation direction RDR and the applied electric field direction EDR. In the present embodiment, the initial orientation direction RDR is about 75° with respect to the horizontal direction.

[0225] In this respect, the angle made by the initial orientation direction RDR and the applied electric field direction EDR must be 45° C. and over to 90° C. excl. if the dielectric constant anisotropism Δε of the LC material is positive, and must be over 0° C. and to 45° C. incl. if the dielectric constant anisotropism Δε is negative.

[0226] For the polarizing plate POL, a polarizing plate having an electrical conductivity is used, the polarizing transmitting shaft MAX1 of the lower polarizing plate POLL is caused to coincide with the initial orientation direction RDR, and the polarizing transmitting shaft MAX2 of the upper polarizing plate POL2 is caused to orthogonally intersect it. FIG. 18 shows this relationship. This provides a normally close characteristic in which the transmission factor is increased as the voltage (voltage between pixel electrode PX and common electrode CT) to be applied to the pixel according to the present invention is increased, and a good quality of black display can be performed when no voltage is applied.

[0227] In this respect, in the present embodiment, countermeasures against a defective display due to static electricity from outside and EMI are taken by causing the polarizing plate to have an electrical conductivity. As regards the electrical conductivity, if the countermeasures are taken only against the influence caused by static electricity, the seat resistance is 108Ω/□ or less, or preferably 104Ω/□ or less if countermeasures are taken against EMI. Also, the back (surface onto which the polarizing plate is adhered) of the surface of the LC composition sandwiched between the glass substrates may be provided with a conductive layer.

[0228] FIG. 7 is a view showing an essential plane around the matrix (AR) of a display panel PNL including upper and lower glass substrates SUB1, SUB2. FIG. 8 is a view showing a cross-section of the vicinity of the gate terminal GTM to which a scanning circuit should be connected on the left side and the vicinity of a seal portion in which there is no external connecting terminal on the right side.

[0229] In the manufacture of the panel, for a small size, a plurality of devices are simultaneously produced with a sheet of glass substrate and thereafter are divided in order to improve the throughput. For a large size, a glass substrate of a size which has been standardized for any type in order to share the use of the manufacturing plant, is processed and thereafter, is reduced to respective sizes suitable for each type. In either case, after a series of processes, the glass is cut off. FIGS. 7 and 8 show the latter example, and both figures show state after the upper and lower substrates SUB1, SUB2 are cut off. LN indicates the edge before both substrates are cut off. In either case, in the completed state, as regards a portion (upper side and left side in the figure) where external connecting terminal group Tg, Td and terminal COT (numerical subscript omitted) exist, the size of the upper substrate SUB2 is restricted inside the lower substrate SUB1 so as to expose the portion. As regards terminal group Tg, Td, a plurality of pieces of the gate terminal GTM, the drain terminal DTM and their drawn wiring portions, which are to be described later, are brought together in units of a tape carrier package TCP on which an integrated circuit chip CHI is mounted, and are called “terminal group Tg, Td”. The drawn wiring from the matrix portion in each group to the external connecting terminal portion is inclined as both ends are approached.

[0230] This is because terminals DTM, GTM of the display panel PNL are matched with the arrangement pitch of the package TCP and the connecting terminal pitch in each package TCP. The common electrode terminal COT is a terminal through which a common voltage is imparted to the common electrode CT from an external circuit. The opposed voltage signal line CL of the matrix portion is drawn out on the opposite side (right side in the figure) of the gate terminal GTM, and each common voltage signal line is collected by the common bus line CB to be connected to the common electrode terminal COT.

[0231] Between the transparent glass substrates SUB1 and SUB2, a seal pattern SL is formed so as to seal the LC except for the LC filling port INJ along their edges. The sealing material is made of, for example, epoxy resin.

[0232] The layers of the orientation film OR11, OR12 are formed inside the seal pattern SL. The polarizing plates POL1, POL2 are constituted on the surface outside of the lower transparent glass substrate SUB1 and the upper transparent glass substrate SUB2, respectively. The LC is encapsulated in an area partitioned by the seal pattern SL between the lower orientation film ORI1 and the upper orientation film ORI2 which set the direction of the LC molecules. The lower orientation film ORI1 is formed at the top of the protective film PSV1 on the side of the lower transparent glass substrate SUB1.

[0233] This LCD is assembled such that various layers are stacked separately on the side of the lower transparent glass substrate SUB1, and on the side of the upper transparent glass substrate SUB2, the seal pattern SL is formed on the substrate SUB2 side, the upper transparent glass substrate SUB2 is superimposed on the lower transparent glass substrate SUB2, the LC is injected from an opening INJ of the seal material SL, an injection port INJ is sealed with epoxy resin or the like, and the upper and lower substrates are cut off.

[0234] FIGS. 9(A) and 9(B) are views showing the connection construction from the gate signal line GL of display matrix to its external connecting terminal GTM, wherein FIG. 9(A) is a plan view and FIG. 9(B) is a cross-sectional view taken on line B—B of FIG. 9(A). In this respect, FIG. 9(A) corresponds to the lower portion of FIG. 7, and the portion of oblique wiring is represented by a straight line for convenience' sake.

[0235] In the figure, the Cr—Mo layer g3 is hatched for the sake of understanding.

[0236] The gate terminal GTM is composed of the Cr—Mo layer g3, and a transparent conductive layer i1, which further protects the surface of the Cr—Mo layer g3 and improves the reliability of connection with the TCP (Tape Carrier Package). This transparent conductive layer il employs a transparent conductive film ITO.

[0237] In FIG. 9(A), the insulating film GI and the protective film PSV1 are formed on the right side of their borderline, and the terminal portion GTM located at the left end is exposed from them so as to enable electric contact with an external circuit. In FIG. 9(B), only a pair of the gate line GL and the gate terminal are shown, but actually a plurality of such pairs are arranged in the upper and lower sides to constitute the terminal group Tg, the left end of the gate terminal is, in the manufacturing process, extended beyond the cut area of the substrate, and is short-circuited through wiring SHg (not shown). This is useful to prevent electrostatic destruction during rubbing of the orientation film ORI1 in the manufacturing process, and the like.

[0238] FIGS. 10(A) and 10(B) are views showing connection from the drain signal line DL to its external connecting terminal DTM, wherein FIG. 10(A) is the plan view and FIG. 10(B) is a cross-sectional view taken on line B—B of FIG. 10(A). In this respect, FIG. 10(A) corresponds to the upper right portion of FIG. 7, and the right end direction corresponds to the upper end portion of the substrate SUB1 although the direction of FIG. 10(A) is changed for the convenience' sake.

[0239] TSTD is an inspection terminal, and no external circuit is connected thereto, but it is widened more than the wiring portion so as to allow a probe or the like to contact it. Likewise, the drain terminal DTM also is widened more than the wiring portion so as to allow an external circuit to connect thereto. The external connecting drain terminal DTM is arranged in the up-and-down direction, and the drain terminal DTM constitutes the terminal group Td (numerical subscript omitted) as shown in FIG. 7. The drain terminal DTM is further extended beyond the cut line of the substrate SUB1, and all of it is short-circuited with each other through the wiring SHd (not shown) in order to prevent electrostatic destruction during manufacturing process. The inspection terminal TSTD is formed into the drain signal line DL every other line as shown in FIG. 10(A).

[0240] The drain connecting terminal DTM is formed by the transparent conductive layer i1, and a portion with the protective film PSV1 removed is connected to the drain signal line DL. This transparent conductive film il employs the transparent conductive film ITO as in the case of the gate terminal GTM.

[0241] The drawn wiring from the matrix portion to the drain terminal portion DTM is constituted by the same level of layer d3 as the drain signal line DL.

[0242] FIGS. 11(A) and 11(B) area views showing connection from the opposed voltage signal line CL to its external connecting terminal CTM, wherein FIG. 11(A) is the plan view and FIG. 11(B) is a cross-sectional view taken on line B—B of FIG. 11(A). In this respect, FIG. 11(A) corresponds to the upper left portion of FIG. 5.

[0243] Each opposed voltage signal line CL is brought together by a common bus line CB1 to be drawn out to the common electrode terminal CTM. The common bus line CB1 is structured such that a conductive layer 3 is stacked on a conductive layer g3 and they are electrically connected by the transparent conductive layer i1. This is because an attempt is made to reduce the resistance of the common bus line CB and to sufficiently supply a common voltage to each opposed voltage signal line CL from an external circuit. This structure is characterized by the fact that the resistance of the common bus line can be lowered particularly without adding any new conductive layer.

[0244] The common electrode terminal CTM is structured such that the transparent conductive layer il is stacked on the conductive layer g3 This transparent conductive layer i1 employs the transparent conductive film ITO as in the case of other terminals. In order to protect the surface of the conductive layer g3 and to prevent electric corrosion and the like, the conductive layer g3 is covered with a transparent conductive layer i1 having excellent durability. As regards connection between the transparent conductive layer i1, the conductive layer g3 and the conductive layer d3 the protective film PSV1 and the insulating film GI are formed with through-holes for conduction.

[0245] On the other hand, FIGS. 12(A) and 12(B) are views showing connection from the other end of the opposed voltage signal line CL to its external connecting terminal CTM2, wherein FIG. 12(A) is a plan view and FIG. 12(B) is a cross-sectional view taken on line B—B of FIG. 12(A). In this respect, FIG. 12(A) corresponds to the upper right portion of FIG. 5. At the common bus line CB2, each opposed voltage signal line CL is brought together at the other end (gate terminal GTM side) to be drawn out to the common electrode terminal CTM2. It is different from the common bus line CB1 in that it is formed by the conductive layer d3 and the transparent conductive layer i1 so as to be insulated from the gate signal line GL. It is insulated from the gate signal line GL by the insulating film GI.

[0246] FIG. 13 shows an equivalent circuit for the display matrix portion and a connection diagram for its peripheral circuit. FIG. 13 is a circuit diagram, but is drawn to the actual geometrical arrangement. AR designates a matrix array in which a plurality of pixels are two-dimensionally arranged.

[0247] In FIG. 13, X designates a drain signal line DL, and subscripts G, B and R are added to green, blue and red pixels, respectively. Y designates a gate signal line GL, and subscripts 1, 2, 3, . . . , and end are added in accordance with the order of the scanning timing.

[0248] A gate signal line Y (subscript omitted) is connected to a vertical scanning circuit V, and a drain signal line X (subscript omitted) is connected to a drain signal driving circuit H.

[0249] SUP designates a circuit including a power circuit for obtaining plural stabilized voltage sources voltage-divided from one voltage source, and a circuit for exchanging information for CRT (Cathode Ray Tube) from a host (host processor) with information for TFT LCD.

[0250] FIG. 6 shows driving the wave-form in a LCD according to the present embodiment. The common voltage V_COMis set to a fixed potential temporally in order to exhibit a dimensional compensation effect according to the present invention.

[0251] A gate signal V_Gtakes the on-level every one scanning period, and others take the off-level. The drain signal voltage is applied such that it is transmitted to one pixel by reversing the positive electrode and negative electrode every one frame with an amplitude twice as much as the voltage to be applied onto the LC layer. In this case, the drain signal voltage V_Dreverses in polarity every one column, and reverses in polarity every two lines. This provides a structure (dot inversion driving) in which pixels, whose polarity has been reversed, adjoin each other left, right, up or down, thereby making it difficult for flicker or crosstalk (smear) to be generated. The common voltage V_COMis set to a voltage which is a fixed amount lower than center voltage of inversion of drain signal voltage.

[0252] This compensates for the feed through voltage which is generated when the thin film transistor element changes from on to off, and operates to apply an AC voltage having few DC components to the LC (because after images, deterioration or the like becomes heavy when DC is applied to LC).

[0253] With reference to FIGS. 14 to 16, the description will be made of a manufacturing process for an active matrix type LCD according to the present invention.

[0254] FIGS. 14 to 16 each show part of a process at the center, a cross-sectional view taken on line 7—7 of FIG. 1 in the TFT portion on the left side, and a cross-sectional view taken on line 6—6 of FIG. 1 on the right side.

[0255] As shown in FIGS. 14 to 16, an active matrix type LCD according to the present invention is manufactured by a plurality of processes (A) to (G). Processes (A) to (G), except for processes (B) and (D), are divided corresponding to each photographic process, and any cross-sectional view for each process shows a stage in which working occurs after the photographic process is finished and photo-resist was removed. The photographic process is, in this description, a series of operations from coating of photo-resist to development through selective exposure using a mask.

[0256] The process (A) will be described.

[0257] The process (A) is, as the first step, to provide a conductive film g3 having a film thickness of 2000 Å consisting of Cr—Mo and the like on the lower transparent glass substrate SUB1 consisting of AN635 glass (commercial name) by sputtering. After a photographic process for Cr—Mo in the second step, the conductive film g3 is selectively etched using dibasic cerium ammon nitrate. By this process, the gate electrode GT is formed in the TFT portion while the common electrode is formed in the pixel comb-teeth electrode portion. In this respect, in a place not shown, there is formed a bus line Shg, through which the gate signal line GL, the common voltage signal line CL, the gate terminal GTM, a first conductive layer of the common bus line CB1, a first conductive layer of the common electrode terminal CTM1, and the gate terminal GTM are connected.

[0258] The process (B) will be described.

[0259] In the process (B), ammonia gas, silane gas and nitrogen gas are introduced into a plasma CVD apparatus to provide a silicon nitride film having a film thickness of 3500 Å, silane gas and hydrogen gas are introduced into the plasma CVD apparatus to provide “i” type amorphous Silicon film having film thickness of 1200 Å, and thereafter, hydrogen gas and phosphine gas are introduced into the plasma CVD apparatus to provide a N(+) type amorphous Silicon film having a film thickness of 300 Å.

[0260] The process (C) will be described.

[0261] In the process (C), after a photographic process for a-Si, a N(+) type amorphous Silicon film or “i” type amorphous Silicon film is selectively etched using SF₆, CC14 as a dry etching gas to thereby form an island of an “i” type semiconductor layer AS.

[0262] The process (D) will be described.

[0263] In the process (D), in the first step, a conductive film d3 having film thickness of 300 Å consisting of Cr is provided by sputtering. After the photographic process for Cr—Mo is performed as the second step, in the third step, the conductive film d3 is etched using the same liquid as in the process (A) to thereby form a bus line SHd (not shown) which short-circuits the drain signal line DL, the source electrode SD1 (including stored capacity Cstg formation portion), the pixel electrode PX, the drain electrode SD2, the first conductive layer of the common bus line CB2 and the drain terminal DTM (these are patterned using the same photo-mask, and are collectively formed).

[0264] In the fourth step, CC14 and SF6 are introduced into a dry etching apparatus, and a N(+) type amorphous Silicon film is etched to thereby selectively remove the N(+) type semiconductor layer d0 between the source and drain. After the conductive film d3 is patterned with a mask pattern, the N(+) type semiconductor layer d0 is removed with the conductive film d3 serving as a mask. More specifically, as regards the N(+) type semiconductor layer d0 which has remained on the “i” type semiconductor layer AS, all portions other than the conductive film d1 and a conductive film d2 are removed by a self-align process. At this time, the N(+) type semiconductor layer d0 is etched so that all of its thickness portion is removed, and therefore, the surface portion of the “i” type semiconductor layer AS is also somewhat etched, but the degree of the etching can be controlled by the etching time.

[0265] The process (E) will be described.

[0266] In the first step of the process (E), ammonia gas, silane gas and nitrogen gas are introduced into a plasma CVD apparatus to provide a silicon nitride film having a film thickness of 0.4 μm. After performing a photographic process for SiN as the second step, the silicon nitride film is selectively etched using SF₆as a dry etching gas in the third step, whereby the protective film PSV1 and the insulating film GI are patterned. The protective film PSV1 and the insulating film GI are patterned using the same photo-mask, and are collectively worked.

[0267] FIG. 17 is a top view showing a state in which a drain signal driving circuit H and a vertical scanning circuit V are connected to the display panel PNL shown in FIG. 7 and the like. CH1 designates a driving IC chip (lower five chips are driving IC chips on the vertical scanning circuit side, and ten chips each on the left side are driving IC chips on the drain signal driving circuit side) for driving the display panel PNL. TCP designates a tape carrier package comprising a driving IC chip CH1 packaged by the Tape Automated Bonding method (TAB), and PCB1 designates a driving circuit substrate on which the above-described TCP, a capacitor and the like are packaged, which is divided into two: for the drain signal driving circuit and for the gate signal driving circuit. FGP designates a frame ground pad, in which a spring-shaped fragment provided by cutting into a shield case SHD is soldered. FC designates flat cable through which the lower driving circuit substrate PCB1 and the left-side driving circuit substrate PCB1 are electrically connected. For the flat cable FC, there is used flat cable obtained by sandwiching plural lead wire (phosphor bronze material coated with Sn plating) between stripe-shaped polyethylene layer and polyvinyl alcohol layer and supporting as shown in FIG. 16.

[0268] FIG. 18 is an exploded perspective view showing each component of a LC display module MDL.

[0269] SHD designates a frame-shaped shield case (metal frame) consisting of a metallic plate; LCW denotes its display window; PNL denotes a LC display panel; SPB denotes a light diffusion board; LCB denotes a light guiding object; RM denotes a reflective plate; BL denotes a back-light fluorescent tube; and LCA denotes a back-light case, and each member is stacked in a vertical arrangement relationship as shown in FIG. 17 to constitute a module MDL.

[0270] The module MDL is adapted to be entirely fixed by claws and hooks provided for the shield case SHD.

[0271] The back-light case LCA has a shape to accommodate the back-light fluorescent tube BL, the light diffusion board SPB, the light guiding object LCB and the reflective plate RM, and light from the back-light fluorescent tube BL arranged on the side of the light guiding object LCB is made into uniform back light on the display surf ace by the light guiding object LCB, the reflective plate RM and the light diffusion board SPB to be emitted on the LC display panel PNL side.

[0272] An inverter circuit substrate PCB3 is connected to the back-light fluorescent tube BL as a power supply therefor.

[0273] In order to quantitatively measure display unevenness on a LC display element constituted in the present embodiment, a display surface was picked up (after gentle luminance shading over a wide range on the entire display surface, which is not recognized as display unevenness, is removed) with a CCD camera in a low luminance (10% relative luminance of the maximum luminance) display state, in which display unevenness is most conspicuous, to measure the contrast of the maximum luminance unevenness. As a result, the contrast was about 2%, and no display unevenness was recognized even in an image quality inspection by visual inspection, but a display with a high level of uniformity could be obtained.

[0274] Further, when comparing display luminance unevenness in a case where 10% relative luminance of the maximum luminance was displayed by causing the TFT to be normally on with the gate voltage of all pixels TFT in the above-described LCD at the threshold level or higher, with that in a case where the same entire display surface was displayed at the same luminance by temporally turning on/off the TFT in the same manner as in the actual state of use, the display luminance unevenness resulting from (disassembled after inspection, and the orientation film and the like on the surface of the TFT substrate are removed to observe and measure variations in electrode dimensions for confirmation) dimensional fluctuation in the electrode formation process of a TFT substrate could be confirmed even by visual inspection in the former display when the TFT was always on, whereas the display luminance unevenness could not be visually recognized in the latter normal driving lighting.

[0275] In the above-described comparison in measurement using the CCD camera, the contrast of the maximum luminance unevenness of the latter was reduced by 30% as compared with the former.

[0276] (Second Embodiment)

[0277] In the above-described first embodiment, the common voltage V_COMto be applied to the common electrode CT is set to the AC voltage, which temporally varies between substantially two values in synchronism with variations in the drain signal voltage, and further the gate signal V_Gis adapted to take substantially four values in synchronism with variations in the above-described common voltage. Except for those features above-described, a LCD was manufactured in the same manner as in the first embodiment, and this was made into a second embodiment.

[0278] In order to exhibit the compensation effect for display unevenness caused by electrode dimensional fluctuation according to the present invention, the gate signal, which takes substantially four values, was adapted to selectively take either of two on-level values and either of two off-level values so that the falling width of the gate pulse at the time when the TFT is off becomes substantially the same between positive charging and negative charging periods in synchronism with the above-described AC-converted common voltage.

[0279] Since the maximum amplitude of the drain signal voltage could be reduced because of the above-described AC-converted common voltage, a circuit having a low withstand voltage was used for the drain signal driving circuit (signal-side driver).

[0280] As regards a LCD according to the second embodiment, when the contrast of the maximum luminance unevenness was measured as in the case of the first embodiment, it was about 1%, no display unevenness was seen even in the image quality inspection by visual inspection, but display with a high level of uniformity was obtained.

[0281] As in the case of the first embodiment, when comparing display luminance unevenness on the entire display surface in a case where 10% relative luminance of the maximum luminance was displayed by causing the TFT to be normally on with the gate voltage of all pixels TFT as the threshold or higher, with that in a case where the same entire display surface was displayed at the same luminance by temporally turning on/off the TFT in the same manner as in the actual state of use, the contrast of the maximum luminance unevenness in the latter was reduced to less than a half of that in the former in the comparison in a measurement using the CCD camera as in the case of the first embodiment.

[0282] In the above-described second embodiment, the structure is arranged such that the gate signal VG has substantially two values in synchronism with the variations in the common voltage only at the off-level, and has, at the on-level, substantially the same values during positive/negative charging to have substantially three values in total. Except for those features above-described, a LCD was manufactured in the same manner as in the second embodiment, and this was made into a first comparative example.

[0283] As in the case of the above-described first embodiment, when comparing display luminance unevenness in a case where 10% relative luminance of the maximum luminance was displayed on the entire display surface by causing the TFT to be normally on with the gate voltage of all pixels TFT at the threshold level or higher, with that in a case where the same entire display surface was displayed at the same luminance by temporally turning on/off the TFT in the same manner as in the actual state of use, any difference between both was hardly visually recognized, but display luminance unevenness resulting from dimensional fluctuation could be confirmed even by visual inspection for both.

[0284] Therefore, in the case of this comparative example using the gate signal having substantially three values, it is considered that in the low luminance display, in which the display unevenness is most conspicuous, the compensation effect for the display unevenness caused by electrode dimensional fluctuation according to the present invention is not exhibited.

[0285] When, as in the case of the first embodiment, the display surface of the LCD according to this first comparative example was picked up with a CDD camera to measure the contrast of the maximum luminance unevenness, the luminance unevenness reached as high a level as 12%, and display color unevenness resulting from fluctuation of the difference in thickness of the LC layer was conspicuous even in the visual inspection.

[0286] Also, even in the comparison in the measurements using a CCD camera, in the case where the all pixels TFT are caused to be normally on, and in the case of normal driving in which the TFT is temporally turned on/off, any difference was hardly recognized in the contrast between their maximum luminance unevenness.

[0287] The compensation effects in the above-described first and second embodiments and the first comparative example will be compared on the basis of the compensation condition equation (4) used in the description of the operation of the present invention.

[0288] Concretely, the compensation condition equation (4) will be evaluated with the following equation (transmission factor variation ΔT per unit one-side retreat amount Al standardized at an inclination α of luminance-voltage curve and video signal voltage V′_SIG) which has been deformed referring to the equations (1, 2).

[0289] {1/(αV′_sig)}(ΔT/Δ1=−(1/1{circumflex over ( )}2){1+(ΔC′gs/Ctot)+{1/(1Ctot)}(Cgsoff/1s+2Cgsoff/W+ΔC′gs/1tot)=A+B

[0290] Here, A and B are defined as follows:

[0291] A=−(1/1{circumflex over ( )}2)−{ΔC′gs/(1{circumflex over ( )}2Ctot)}

[0292] B={Cgsoff/1s1Ctot)}+{2Cgsoff/(W1Ctot)}+(ΔC′gs/(1tot1Ctot)}

[0293] where A and B are components which contribute to effects for inter-pixel electrode gap fluctuation and TFT channel dimensional fluctuation with respect to the transmission factor fluctuation, respectively.

[0294] As regards a compensation ratio R (R=1 means perfect compensation, and minus means that influences of each fluctuation between pixel electrodes are increased conversely), which is defined with A and B, and R=−B/A, those obtained by calculating the compensation ratio R using design parameters in the first and second embodiments and the first comparative example are shown in Table 1.

[0295] As regards video signal voltage V_SIGduring common AC driving, it is set to V_SIG=(⅓−½) (V_MAX−V_TH) which substantially corresponds to the relative transmission factor of 10%, at which it is said that the luminance unevenness is most conspicuous, and ΔC′gs=−(¼)Cgson−Cgsoff is used.

[0296] From the above-described Table 1, it can be seen that as described in detail in the operation of the present invention, the compensation ratios in the first embodiment using dot inversion driving with common fixed, and in the second embodiment using full common AC driving in which a 4-value gate pulse is used are 0.29 and 0.35, respectively, that about 30% of luminance fluctuation resulting from pixel electrode interval fluctuation is estimated to be compensated for by effective driving voltage fluctuation caused by dimensional fluctuations in TFT and the stored capacity formation portion which simultaneously occur, and that they considerably meet the evaluation result for each of the above-described embodiments.

[0297] On the other hand, in the case of the first comparative example using the common AC driving based on the 3-value gate pulse which is normally used in most cases, the effective driving voltage fluctuation has a negative value, although slightly, and the effects of dimensional fluctuations in the TFT and the storage capacity formation portion are exhibited in a direction to increase the luminance fluctuation caused by the pixel electrode interval fluctuation. Therefore, it can be seen that the electrode dimensional fluctuation appears as display luminance unevenness as it is.

[0298] As described above in detail, according to the present invention, it is possible to provide an active matrix type LCD using a horizontal electric field system, which hardly generates display unevenness incident to electrode dimensional fluctuation caused by variations resulting from the electrode formation process, and is excellent in mass producibility in high image quality.