DC gain enhancement for operational amplifiers

[0002] The present invention relates, in general, to operational amplifiers and, more particularly, to a method and structure for enhancing the gain while reducing the input offset voltage of typical operational amplifiers.

[0003] Operational amplifiers generally comprise a first gain stage followed by an output stage the latter of which drives a load coupled to the output of the operational amplifier. The first gain stage includes at least an input differential amplifier stage the differential outputs of which drive a current mirror. The current mirror converts the differential outputs of the input differential amplifier to a single-ended output that drives the output stage.

[0004] The direct current (DC) gain of the aforesaid operational amplifier is typically limited by the voltage swing developed at the output of the first gain stage. Usually this voltage swing occurs at the output of the current mirror. This voltage swing causes a small current to be reflected back to the input differential amplifier due to the finite output impedance of the current mirror. This effect causes the input differential amplifier to correct for this imbalance which reduces the DC gain of the amplifier. CMOS transistor operational amplifiers are especially prone to this gain reduction due to the higher voltage swings necessary at the output of the first gain stage because of the low Gm of MOS transistors. Further, the output impedance of CMOS current mirrors is typically lower than for bipolar transistor current mirrors which will cause a greater current to be reflected to the input of the operational amplifier.

[0005] In view of the above, it would be advantageous to provide circuitry and a method for enhancing the DC gain and reducing the input offset voltage for operational amplifiers.

[0006] FIG. 1 is a block diagram of the operational amplifier of the present invention;

[0007] FIG. 2 is a schematic diagram of the differential amplifier input stage of FIG. 1;

[0008] FIG. 3 is a schematic diagram of the current mirror of the input stage of the operational amplifier of FIG. 1;

[0009] FIG. 4 is a schematic diagram of the output stage of the operational amplifier of FIG. 1; and

[0010] FIG. 5 is a schematic diagram of the feedback amplifier of the present invention.

[0011] FIG. 1 is a block diagram of a self-compensating amplifier 10 of one embodiment of the disclosure shown as having two gain stages, i.e., an input stage 16 and an output stage 30. Self-compensating amplifier 10 receives differential signals V_IN− and V_IN+ at respective terminals 12 and 14 and generates an amplified output signal VOUT at terminal 32. Input stage 16 includes a differential amplifier 18 and a current mirror 24. Differential amplifier 18 receives the differential signals VIN+ and VIN− and connections are made to the input and output of current mirror 24 through terminals 20 and 22 respectively.

[0012] Self-compensating amplifier 10 includes a feedback amplifier 28 having a non-inverting input connected to terminal 20 and an inverting input connected to terminal 22. The output of feedback amplifier 28 is connected to an input terminal 26 of current mirror 24. Output stage 30 has an input connected to terminal 22 and an output connected to terminal 32.

[0013] FIG. 2 is a schematic diagram of differential amplifier 18 of FIG. 1 that includes N-channel MOS depletion mode transistors 36 and 38 that have gate terminals coupled to respective terminals 12 and 14 for receiving differential signals. It should be noted that the same reference numbers are used in the figures to denote the same elements. Transistors 36 and 38 have commonly connected source terminals that are also connected through a current source 40 to a first power conductor, to which a first operating potential is supplied,.

[0014] P-channel MOS transistors 42 and 46 have source terminals that are connected to each other to a second power conductor and receive a second operating potential, the power supply voltage V_CC. The drain terminal of transistor 42 is connected to the source terminal of P-channel MOS transistor 44 and further connected to the drain terminal of transistor 36. The drain terminal of transistor 46 is connected to the source terminal of P-channel MOS transistor 48 and further connected to the drain terminal of transistor 38. The commonly connected gate terminals of transistors 42, 44, 46, and 48 are coupled for receiving a bias voltage V_BIAS(p). The drain terminals of transistors 44 and 48 are connected to terminals 20 and 22, respectively. Transistors 42, 44, 46, and 48 provide a folded cascoded connection to current mirror 24 as generally understood.

[0015] FIG. 3 is a schematic diagram of current mirror 24 of FIG. 1 which establishes a signal at terminal 22 to the input of output gain stage 30. N-channel MOS transistors 52 and 56 have drain terminals that are connected to respective terminals 20 and 22. The source terminal of transistor 52 is connected to the drain terminal of N-channel transistor 54 and the source terminal of transistor 56 is connected to the drain terminal of N-channel transistor 58. The commonly connected source terminals of N-channel transistors 54 and 58 are coupled to the first power conductor. Transistors 52 and 56 are cascode transistors which increases the impedance at respective terminals 20 and 22. An N-channel MOS depletion mode transistor 50 has a gate terminal connected to terminal 20 and a drain terminal coupled for receiving a second source of operating potential V_CC. A source terminal of transistor 50 and a drain terminal of N-channel transistor 60 are commonly connected to the gate terminals of transistors 5254, 56, and 58. The gate terminal of transistor 60 is connected to terminal 26, while the source terminal is coupled for receiving the operating potential V_EE.

[0016] FIG. 4 is a schematic diagram of output stage 30 of FIG. 1. The signal arising at the output of current mirror 24, at terminal 22, is received at the input of output stage 30 (the gate of N-channel transistor 64) and is amplified for providing the signal V_OUTat terminal 32. The gate terminal of N-channel depletion mode transistor 64 is connected to terminal 22, while the drain terminal receives the operating potential V_CC. An N-channel depletion mode transistor 66 has a gate terminal and a source terminal commonly connected to a power conductor that receives the operating potential V_EE. The drain terminal of transistor 66 is connected to the source terminal of transistor 64.

[0017] The gate terminal of transistor 68 is connected to the source terminal of transistor 64. The commonly connected gate and drain terminals of N-channel transistor 74 are connected to the drain terminal of transistor 68. The source terminal of transistor 74 is coupled to the operating potential V_EE. A P-channel transistor 70 has a gate terminal coupled for receiving the bias voltage V_BIAS(p), a source terminal that receives the operating potential V_CC, and a drain terminal that connects to the drain terminal of transistor 68.

[0018] The gate terminal of transistor 78 is connected to the drain terminal of transistor 68 and the source terminal receives the operating voltage V_EE. A P-channel transistor 72 forms a current source as does P-channel transistor 70. In particular, the gate terminal or electrode of transistor 72 is coupled to the bias voltage V_BIAS(P) while its drain is coupled both to the gate of transistor 80 and the drain of transistor 78. The source terminals of transistors 72 and 80 receive the operating potential V_CC. The gate terminal of N-channel transistor 82 is connected to the source terminal of transistor 64. The source terminal of transistor 82 receives the operating voltage V_EE. The drain terminals of transistors 80 and 82 are connected to terminal 32 and supply the signal V_OUTby either sourcing or sinking current at terminal 32 responsive to the differential input signals applied to inputs 12 and 14 of the operational amplifier 10.

[0019] FIG. 5 is a schematic diagram of amplifier 28 of FIG. 1. Amplifier 28 has a non-inverting input and an inverting input which receive signals from terminals 20 and 22, respectively. N-channel depletion mode transistors 86 and 88 have gate terminals coupled for receiving the differential signals from respective terminals 20 and 22.

[0020] Transistors 86 and 88 have commonly connected source terminals that are connected to a power conductor V_EEthrough a N-channel transistor 90. The gate terminal of transistor 90 receives a bias voltage V_BIAS(N).

[0021] P-channel transistors 92 and 98 have source terminals that receive the power supply voltage V_CC. The drain terminal of transistor 92 is connected to the source terminal of P-channel transistor 94 and further connected to the drain terminal of transistor 86. The drain terminal of transistor 98 is connected to the source terminal of P-channel transistor 100 and further connected to the drain terminal of transistor 88. The commonly connected gate terminals of transistors 92, 94, 98, and 100 are coupled for receiving a bias voltage V_BIAS(P).

[0022] N-channel transistors 96 and 102 form a current mirror. The gate and drain terminals of transistor 96 are commonly connected to the gate terminal of transistor 102 and further connected to the drain terminal of transistor 94. The drain terminal of transistor 102 is connected to the drain terminal of transistor 100. The source terminals of transistors 96 and 102 are connected to the power a conductor V_EE. A P-channel transistor 104 has a gate terminal coupled for receiving the bias voltage V_BIAS(P). The source terminal of transistor 104 is connected to the power supply conductor and receives the voltage V_CC. An N-channel transistor 106 has a gate terminal coupled to the drain terminal of transistor 102. The source terminal of transistor 106 is connected to the power supply conductor and receives the voltage V_EE. The drain terminals of transistors 104 and 106 are connected to terminal 26 and supply the feedback signal that is generated by amplifier 28.

[0023] In operation, referring to FIG. 1, self-compensating amplifier 10 provides two gain stages. Input stage 16 provides gain by generating a signal at terminal 22 based on the differential signals supplied at inputs 12 and 14.

[0024] Output stage 30 also provides gain by generating the signal V_OUTbased on the signal at terminal 22. When the magnitude of the signal at terminal 22 is greater than a particular voltage, output stage 30 sinks a current at terminal 32. On the other hand, when the magnitude of the signal at terminal 22 is less than the particular voltage, output stage 30 sources a current at terminal 32. Thus, output stage 30 sinks or sources current based on the magnitude of the signal at terminal 22 varying above and below a predetermined value. The general operation of amplifier 10, as above described, is well known to those skilled in the art.

[0025] The finite impedance at terminal 22 limits the gain of amplifier 10. As shown in FIGS. 2, 3 and 4, transistors 46, 48, 56, 58, and 64 have connections to terminal 22. Transistor 64, configured as a source follower, has its gate terminal connected to terminal 22 and produces a high impedance thereat relative to ground. However, a first current conduction path from terminal 22 to the power conductor that receives the voltage V_CCis provided through the drain-to-source resistance of transistors 46 and 48. A second current conduction path from terminal 22 to the power conductor that receives the voltage V_EEis provided through the output impedance set by transistors 56 and 58. As input stage 16 generates a voltage swing at terminal 22, currents are conducted through the first and second current conduction paths and if not compensated, limit the voltage gain of amplifier 10 while producing an input voltage offset due to the change in current through transistors 48 and 56.

[0026] The following will provide a brief explanation of the above-disclosed undesirable effects. Briefly, during operation of the operational amplifier, the voltage at node 20, if not compensated, remains substantially fixed due to the biasing of transistors 50, 54 and 58. Hence, this voltage does not track the variations in the voltage appearing at node 22. As the voltage V_GS(gate-to-source) of transistor 82 changes in response to the input differential signals, thereby causing a current to be either sourced or sank at output 32, this voltage change is translated through source follower transistor 64 since its V_GSdoesn't substantially change. Therefore, as transistors 48 and 56 present a finite impedance, a delta current is created as the voltage at node 22 varies. This delta current has to be supplied by a change in the bias of transistor 36 and 38 of differential amplifier 18. Thus, the delta current created produces a large gain error of operational amplifier 10 while an input offset voltage is created between input transistors 36 and 38.

[0027] In order to overcome the imbalance of the voltages generated at nodes 20 and 22 as described above creating a delta current, feedback amplifier 28 is provided in accordance with the present invention. Briefly referring to FIG. 1, amplifier 28 detects voltage imbalances that exist at terminal 20 with respect to terminal 22. Amplifier 28 generates a feedback signal at input 26 of current mirror 24 that compensates for the voltage imbalances and adjusts the voltage at terminal 20 to substantially match the voltage at terminal 22. By matching the voltages at terminals 20 and 22, the delta currents are equal on both sides of current mirror 24, i.e., the delta currents flowing at terminals 20 and 22 are equal. In other words, the currents being conducted from terminal 22 through the first and second current conduction paths are matched by currents being conducted from terminal 20. For instance, briefly referring to FIG. 2, amplifier 28 causes the voltages at terminals 20 and 22 to be matched, and the current conducted from terminal 20 through transistors 42 and 44 compensates for the current being conducted from terminal 22 through transistors 46 and 48. Briefly referring to FIG. 3, by matching the voltages at terminals 20 and 22, the current conducted from terminal 20 through transistors 52 and 54 compensates for the current being conducted from terminal 22 through transistors 56 and 58. Since the delta currents are substantially equal, no differential signal is applied across the input of the amplifier resulting in a very high voltage gain.

[0028] Amplifier 28 generates the feedback signal at input 26 of current mirror 24 to adjust the voltage at terminal 20 to substantially match the voltage at terminal 22. Briefly referring to FIG. 1, when the voltage at terminal 22 is greater than the voltage at terminal 20, the feedback signal increases in voltage. Briefly referring to FIG. 3, the feedback signal at terminal 26 having an increased voltage causes transistor 60 to conduct more current through transistor 50.

[0029] By now it should be appreciated that the present invention provides a circuit and method for self-correcting an operational amplifier for extending the linear operating range of the amplifier. By providing a feedback signal responsive to a change in voltage at the output (22) of current mirror 24, the voltage at the input (20) of current mirror 24 is made to track and match the former. This matching of voltages enhances the DC gain of the operational amplifier. The static input voltage offset of amplifier 10 is also improved because the feedback signal from amplifier 28 causes the voltages at nodes 20 and 22 to match and track each other even if process variations exists and temperature varies.