US 6,300,219 B1Grant
Method of forming trench isolation regions
Issue Date:2001-10-09
•39 Claims
•6 Drawing Sheets
Abstract
In accordance with an aspect of the invention, a method of forming a trench isolation region includes forming a trench within a substrate. A silanol layer is formed to partially fill the trench and then converted, at least some of the silanol, to a compound including at least one of SiOnand RSiOn, where R includes an organic group. An electrically insulative material is formed over the converted silanol to fill the trench. In another aspect of the invention, a method of forming a trench isolation region includes forming a trench within a substrate. A first layer of at least one of Si(OH)xand (CH3)ySi(OH)4−yis formed to partially fill the trench. At least some of the Si(OH)xif present is converted to SiO2and at least some of (CH3)ySi(OH)4−yif present is converted to (CH3)xSiO2−x. Next, a layer of an electrically insulative material is formed to fill the trench.
Metadata
Assignee
- Micron Technology, Inc.
Inventors
- Trung Tri Doan
- Gurtej S. Sandhu
Application Information
Application Number:US 09/385,915
Filing Date:1999-08-30
Priority Date:1999-08-30
Art Unit:7
Classifications
IPC:
H01L 2176
Field of Search:
438424438224438427438431
Patent Drawings (6 sheets)
Description
Technical Field
[0002] This invention relates to methods of forming trench isolation regions in semiconductive substrates.
Background of the Invention
[0003] In modern semiconductor device applications, numerous devices are packed onto a single small area of a semiconductor substrate to create an integrated circuit. For the circuit to function, many of these individual devices may need to be electrically isolated from one another. Accordingly, electrical isolation is an important and integral part of semiconductor device design for preventing the unwanted electrical coupling between adjacent components and devices.
[0004] As the size of integrated circuits is reduced, the devices that make up the circuits must be positioned closer together in order to comply with the limited space available on a typical semiconductor substrate. As the industry strives towards a greater density of active components per unit area of semiconductor substrate, effective isolation between circuits becomes all the more important.
[0005] The conventional method of isolating circuit components in modern integrated circuit technology takes the form of trench isolation regions etched into a semiconductor substrate. Trench isolation regions are commonly divided into three categories: shallow trenches (STI) (trenches less than about 1 micron deep); moderate depth trenches (trenches of from about 1 to about 3 microns deep); and deep trenches (trenches greater than about 3 microns deep). Once the trench isolation regions are etched in the semiconductor substrate, a dielectric material is deposited to fill the trenches. As the density of components on the semiconductor substrate increased, the widths of the trenches decreased until the process of flowing dielectric material into the trenches developed problems.
[0006] Trench isolation regions, particularly STI regions, can develop undesirable voids in the dielectric material during the process to fill the trenches. As the dielectric material flows to an edge between a substrate surface and a sidewall of the trench, constrictions develop at the top of trenches due to the narrow opening in the trench. As the dielectric material flows into the trench, the constrictions can develop into voids moving into the trench with the dielectric material. Voids lower the dielectric characteristics of the dielectric material used and introduce structural instabilities in subsequent processes. Accordingly, voids in the dielectric material filling an isolation trench region are highly undesirable.
Summary of the Invention
[0007] In accordance with an aspect of the invention, a method of forming a trench isolation region includes forming a trench within a substrate. A silanol layer is formed to partially fill the trench and then at least some of the silanol is converted to a compound comprising at least one of SiOnand RSiONn, where R comprises an organic group. An electrically insulative material is formed over the converted silanol to fill the trench.
[0008] In another aspect of the invention, a method of forming a trench isolation region includes forming a trench within a substrate. A first layer of at least one of Si(OH)xand (CH3)ySi(OH)4−yis formed to partially fill the trench. At least some of the Si(OH)xif present is converted to SiO2and at least some of (CH3)ySi(OH)4−yif present is converted to (CH3)xSiO)2−x. Next, a layer of an electrically insulative material is formed to fill the trench.
[0009] In yet another aspect of the invention, a method of forming a trench isolation region includes forming a trench within a substrate. The trench has sidewalls comprising silicon and a base comprising silicon. A first electrically insulative layer is formed over the sidewalls and base. The first electrically insulative layer is anisotropically etched to expose silicon of the base while leaving silicon of the sidewalls covered. A is second electrically insulative layer is substantially selectively chemical vapor deposited over the exposed trench base. A third electrically insulative layer is formed over the first and second insulative layers to within the trench.
[0010] In still another aspect of the invention, a method of forming a trench isolation region includes forming a trench having sidewalls within a substrate. The sidewalls arc thermally oxidized in an oxidizing environment which includes oxygen and hydrogen with a greater molar concentration of hydrogen than oxygen. A layer of silanol is formed to within the trench and at least some of the silanol is converted to a compound of at least one of SiOnand RSiOn, where R includes an organic group.
Brief Description of the Drawings
[0011] Preferred embodiments of the invention are described below with reference to the following accompanying drawings.
[0012] FIG. 1 is a fragmentary sectional view of a semiconductor substrate at one processing step in accordance with a first embodiment of the invention.
[0013] FIG. 2 is a view of the FIG. 1 substrate fragment at a processing step subsequent to that shown in FIG. 1.
[0014] FIG. 3 is a view of the FIG. 1 substrate fragment at a processing step subsequent to that shown in of FIG. 2.
[0015] FIG. 4 is a view of the FIG. 1 substrate fragment at a processing step subsequent to that shown in of FIG. 3.
[0016] FIG. 5 is a fragmentary sectional view of a semiconductor substrate at one processing step in accordance with a second embodiment of the invention.
[0017] FIG. 6 is a view of the FIG. 5 substrate fragment at a processing step subsequent to that of FIG. 5.
[0018] FIG. 7 is a view of the FIG. 5 substrate fragment at a processing step subsequent to that of FIG. 6.
[0019] FIG. 8 is a fragmentary sectional view of a semiconductor substrate at one processing step in accordance with a third embodiment of the invention.
[0020] FIG. 9 is a view of the FIG. 8 substrate fragment at a processing step subsequent to that of FIG. 8.
[0021] FIG. 10 is a view of the FIG. 8 substrate fragment at a processing step subsequent to that of FIG. 9.
[0022] FIG. 11 is a view of the FIG. 8 substrate fragment at a processing step subsequent to that of FIG. 10.
[0023] FIG. 12 is a view of the FIG. 8 substrate fragment at a processing step subsequent to that of FIG. 11.
[0024] FIG. 13 is a fragmentary sectional view of a semiconductor substrate at one processing step in accordance with a fourth embodiment of the invention.
[0025] FIG. 14 is a view of the FIG. 13 substrate fragment at a processing step subsequent to that of FIG. 13.
[0026] FIG. 15 is a view of the FIG. 13 substrate fragment at a processing step subsequent to that of FIG. 14.
Detailed Description of the Preferred Embodiments
[0027] This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).
[0028] With reference to FIGS. 1-4, a method of forming a trench isolation region is illustrated. Referring to FIG. 1, a semiconductor substrate fragment in process is indicated generally with reference numeral 10. Preferably, the semiconductor substrate fragment 10 comprises the following layers shown in elevationally ascending order: a semiconductor substrate 12, preferably a bulk monocrystalline silicon substrate; an oxide layer 20; and a silicon nitrite layer 22. A series of trenches 14 are formed, preferably by an etching process, through layers 20 and 22 and within semiconductor substrate 12. Trench isolation regions 14 have sidewalls 16 and base walls 18.
[0029] Referring to FIG. 2, a first layer 26 is formed, and initially comprises a silanol which partially fills trenches 14. An exemplary method of forming the first layer 26 is as follows. SiH4and H2O2are separately introduced into a chemical vapor deposition (CVD) chamber, such as a parallel plate reaction chamber (not shown). The reaction rate between SiH4and H2O2can be moderated by the introduction of nitrogen into the reaction chamber. Semiconductive substrate 12 within the chamber is preferably maintained at a suitably low temperature, such as 0° C., at an exemplary pressure of 1 Torr to achieve formation of a silanol-type material of the formula Si(OH)x, which is predominately Si(OH)4. The Si(OH)4condenses onto the semiconductor substrate 12 surface to form layer 26.
[0030] Alternatively, first layer 26 is formed to comprise (CH3)ySi(OH)4−yat least initially to partially fill the trench. The formation of (CH3)ySi(OH)4−ycan be accomplished similarly to that described above for forming silanol, with the exception that (CH3)zSiH4−z, wherein z is at least 1 and no greater than 4, is combined with the hydrogen peroxide (H2O2). For example, CH3SiH3can be combined with H2O2to produce CH3Si(OH)3.
[0031] Although either reaction occurs in the gas phase, the initially deposited first layer 26 (Si(OH)yor (CH3)ySi(OH)4−y) is preferably in the form of a viscous liquid which preferably flows very conformably, ideally depositing over trench base 18 faster and thicker than over sidewalls 16. A preferred thickness for first layer 26 is at least 25% of the trench depth, and more preferably at least 35%, while preferably adding only 200 angstroms or less to sidewalls 16.
[0032] After forming first layer 26 over semiconductor substrate 12, at least some of it is converted to a compound comprising at least one of SiOnand RSiOn, where R comprises an organic group. An exemplary process for doing so is to treat first layer 26 with energy to drive water therefrom and convert to a silicon oxide comprising structure. A specific exemplary method of converting first layer 26 comprises exposing the first layer 26 to ultraviolet light, with other examples of energy being electron beam energy or plasma, and RF energy. Preferably, a two-step process is employed. First, polymerization of the liquid film is promoted by increasing the temperature to above 100° C., while maintaining the pressure of about 1 Torr, to result in solidification and formation of a polymer layer. Thereafter, the temperature is raised to above 300° C., preferably above 400° C., while maintaining a pressure of about 1 Torr, preferably at least 10 atmospheres.
[0033] Referring to FIG. 3, a second layer 30 is formed comprising an electrically insulative material, preferably silicon dioxide, over converted silanol layer 26 to within the trenches 14. Preferably as shown, second layer 30 is formed to fill remaining volume of trenches 14. An exemplary process for forming second layer 30 comprises chemical vapor deposition, preferably plasma-enhanced chemical vapor deposition. For example, conventional high density plasma deposited SiO2can be formed. In the context of this document, “high density” refers to a plasma having at least 1010ions/cm3plasma density. An optional gettering process may be performed at this stage of the process.
[0034] Referring to FIG. 4, planarization can be conducted (i.e., chemical-mechanical polishing) to remove layers 30, 22 and 20 from over the substrate outside of trenches 14.
[0035] With reference to FIGS. 5-7, another embodiment in accordance with the invention is described. Like numerals from the first described embodiment are employed where appropriate, with differences being indicated with a suffix (a) or with different numerals.
[0036] Referring to FIG. 5, a semiconductor substrate fragment in process is indicated generally with reference numeral 10a. An electrically insulating first layer 40 is chemical vapor deposited to within trenches 14 to partially fill the trenches. Preferably, first layer 40 comprises silicon dioxide (SiO2) and fills at least 25% of the trench 14 depth. First layer 40 is preferably deposited by plasma-enhanced chemical vapor deposition, preferably by high density plasma or subatmospheric chemical vapor deposition.
[0037] Referring to FIG. 6, a second layer 44 comprising a silanol is formed over first layer 40 to within trenches 14. Preferably, the method to form second layer 44 is by the same method previously discussed and disclosed for forming first layer 26 of the FIGS. 1-4 embodiment. Consequently, as with the previous method, second layer 44 preferably fills trenches 14, preferably is maintained at a temperature of at least about 300° C., and at a pressure of at least about 10 atmospheres effective to drive water from second layer 44, and preferably is converted to a silicon oxide comprising structure by exposure to energy, for example ultraviolet light.
[0038] Referring to FIG. 7, planarization can be conducted (i.e., chemical-mechanical polishing) to remove layers 44, 40, 22 and 20 from over the substrate outside of trenches 14.
[0039] With reference to FIGS. 8-12, yet another embodiment in accordance with the invention is described. Like numerals from the previously described embodiments are employed where appropriate, with differences being indicated with a suffix (b) or with different numerals.
[0040] Referring to FIG. 8, a semiconductor substrate fragment in process is indicated generally with reference numeral 10b. An electrically insulative layer 21 is formed over silicon trench sidewalls 16 and trench base 18. An example thickness for layer 21 is 150 angstroms. A preferred material for layer 21 is silicon dioxide. An exemplary method of forming layer 21 comprises chemical vapor deposition, and alternatively thermal oxidation. An example thermal oxidation comprises flowing an oxidizing gas (i.e., O2, O3, N2O, NOxor any mixture combination thereof) over substrate 12 within trenches 14 while substrate 12 is maintained at from 85° C. to 115° C. for from 5 to 30 minutes. An example chemical vapor deposition process comprises injecting tetraethylorthosilicate (TEOS) into a reactor chamber at 500 mg/min while flowing O3, preferably as a mixture of 12% O3and 88% O2, at 4000 sccm and helium at from 0-200 sccm and maintaining the substrate 12 at 550° C., and reactor pressure at 200 Torr.
[0041] Referring to FIG. 9, insulative layer 21 is anisotropically etched to expose silicon of the base walls 18 while leaving silicon of the sidewalls 16 covered. An exemplary anisotropic etch comprises a conventional oxide spacer etch.
[0042] Referring to FIG. 10, a second electrically insulative layer 50 is substantially selectively deposited over the exposed base walls 18 to partially fill the trenches 14. Preferably, layer 50 comprises an oxide deposited by chemical vapor deposition, and more preferably silicon dioxide. An exemplary chemical vapor deposition to form layer 50 comprises liquid injecting TEOS into a reactor chamber at 350 mg/min while flowing O3, preferably as a mixture of 12% O3and 88% O2, at 5000 sccm and helium at from 0-200 sccm and maintaining the substrate 12 at 400° C., and reactor pressure at 600 Torr.
[0043] Referring to FIG. 11, a layer 30 is formed comprising an electrically insulative material, preferably silicon dioxide, over layers 21, 22 and 50 to within trenches 14. Preferably as shown, layer 30 is formed to fill remaining volume of trenches 14. An exemplary process for forming second layer 30 comprises chemical vapor deposition, preferably high density plasma-enhanced chemical vapor deposition as described above. An alternative method of forming layer 30 comprises flowing a silanol layer to fill within trenches 14. The method to form layer 30 is preferably by the same method previously discussed and disclosed for forming first layer 26 of the first embodiment shown in FIGS. 1-4 and second layer 44 of the second embodiment shown in FIGS. 5-7.
[0044] Referring to FIG. 12, planarization can be conducted (i.e., chemical-mechanical polishing) to remove layers 30, 22, 21 and 20 from over substrate 12 outside of trenches 14.
[0045] With reference to FIGS. 13-15, still another embodiment in accordance with the invention is described. Like numerals from the first described embodiment are employed where appropriate, with differences being indicated with a suffix (c) or with different numerals. Referring to FIG. 13, an electrically insulative layer 21 is formed over silicon trench sidewalls 16 and trench base 18 by a thermal oxidization process. An exemplary method of forming layer 21 comprises thermally oxidizing the sidewalls of the trench in an oxidizing environment comprising oxygen and hydrogen and having a greater molar concentration of hydrogen than oxygen. An example thermal oxidation comprises flowing an oxidizing as at 200 sccm (i.e., O2, O3, N2O, NOxor any mixture combination thereof) and hydrogen source at 1 slm (i.e., H2, NH3or any mixture combination thereof) over substrate 12 within trenches 14. Preferably, substrate 12 is maintained at from 800° C., to 1100° C., and reactor pressure at from 10 Torr to 760 Torr for from 1 to 20 minutes.
[0046] Referring to FIG. 14, a silanol layer 44 is formed over layers 21 and 22 to within trenches 14. At least some of the silanol is converted to a compound comprising at least one of SiOnand RSiOn, where R comprises an organic group. The method to form layer 44 is preferably by the same method previously discussed and disclosed for forming first layer 26 of the first embodiment shown in FIGS. 1-4 and second layer 44 of the second embodiment shown in FIGS. 5-7.
[0047] Referring to FIG. 15, planarization can be conducted (i.e., 41 chemical-mechanical polishing) to remove layers 44, 22, 21 and 20 from over substrate 12 outside of trenches 14.
[0048] Alternatively, the silanol 44 could be formed within trenches 14 and converted before a sidewall oxidation. Preferably in such instance, the thermal oxidation conditions comprise flowing an oxidizing gas at 200 sccm (i.e., O2, O3, N2O, NOxor any mixture combination thereof) over substrate 12 within trenches 14 while substrate 12 is maintained at is from 850° C. to 1150° C., and reactor pressure at from 10 Torr to 760 Torr for from 5 to 30 minutes.
[0049] Further in accordance with the invention, sidewalls 16 might be oxidized prior to forming first layer 26 in the first embodiment, or prior to forming first layer 40 in the second embodiment. Alternately, sidewalls 16 might be oxidized after forming first layer 26 and before forming second layer 30 in the first embodiment, or after forming first layer 40 and before forming second layer 44 in the second embodiment or after forming layer 50 and before forming layer 30 in the third embodiment. Further alternately, sidewalls 16 might be oxidized after forming second layer 30 in the first embodiment, or after forming layer 44 in the second embodiment. Further alternately with respect to the third embodiment, and where layer 21 is not formed by thermal oxidation, the sidewalls might be oxidized after forming layer 50 and before forming layer 30, or after forming layer 50. Conventional thermal oxidations are preferably conducted in such instances.
[0050] In the preferred first embodiment, first layer 26 flows conformably into the trenches during deposition without forming any constrictions at the top of the trenches where voids begin. The first layer 26 effectively lowers the aspect ratio (defined as trench depth to width) of the trenches preferably by filling at least about a third of the depth while only adding at most 200 angstroms of layer on the sidewalls. As a result, any subsequent layer deposited to fill the layer will have a trench with a lower aspect ratio more conducive to filling without voids.
[0051] In the less preferred second and third embodiments, the first layer is formed by less preferred methods which may not lower the aspect ratio as significantly as in the first embodiment.
[0052] In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.
Claims
Post-issuance certificates present
The text shown below may not reflect later post-issuance changes.
What is claimed is:
1. A method of forming a trench isolation region comprising:
forming a trench within a semiconductor substrate;
partially filling the trench with a silanol aspect ratio lowering material; and
after the partial filling, depositing an electrically insulative material within the trench, the electrically insulative material essentially filling the trench.
2. The method of claim 1 wherein forming the trench comprises etching the semiconductor substrate to form the trench having sidewalls and a base that define a first depth and a first width and wherein a ratio of the first depth to the first width further define a first aspect ratio.
3. The method of claim 2 wherein the partial filling comprises forming a layer of the aspect ratio lowering material within the trench, the layer lowering the first aspect ratio to a second aspect ratio.
4. The method of claim 2 wherein forming the layer of aspect ratio lowering material reduces the first depth by at least about a third to define a second depth.
5. The method of claim 2 wherein forming the layer of aspect ratio lowering material reduces the first depth by at least about a third to a second depth and reduces the first width by no more than about 400 Angstroms to a second width.
6. The method of claim 1 wherein the silanol is selected from the group consisting of Si(OH)4, RSi(OH)3and mixtures thereof.
7. The method of claim 6, wherein RSi(OH)3is CH3(OH)3.
8. The method of claim 2 further comprising forming a layer of electrically insulative material adjacent the sidewalls and the base, the forming prior to the partial filling.
9. The method of claim 8 wherein the electrically insulative material comprises silicon dioxide.
10. The method of claim 8 wherein the forming comprises a thermal oxidation of the sidewalls and base to form a silicon oxide comprising layer.
11. The method of claim 10 wherein the thermal oxidation is prior to the partial filling.
12. The method of claim 10 wherein the thermal oxidation is after the partial filling.
13. The method of claim 1 wherein depositing an electrically insulative material after the partial filling comprises a chemical vapor deposition (CVD) process.
14. The method of claim 13 wherein the CVD process further comprises a plasma enhanced CVD process.
15. The method of claim 1 wherein depositing an electrically insulative material after the partial filling comprises depositing a material comprising silicon oxide.
16. The method of claim 1 wherein the partial filling comprises forming the layer of the aspect ratio lowering material comprising a silanol selected from the group consisting of Si(OH)4, RSi(OH)3and mixtures thereof, and further comprising, converting at least some of the silanol to its equivalent oxide.
17. The method of claim 16, wherein RSi(OH)3is CH3(OH)3.
18. The method of claim 16 wherein the converting comprises maintaining the layer of aspect ratio lowering material at a temperature and a pressure effective to drive water from the first layer.
19. The method of claim 16 wherein forming the trench comprises forming the trench having sidewalls and a base that define a first depth and a first width and wherein a ratio of the first depth to the first width further define a first aspect ratio.
20. The method of claim 19 wherein forming the layer of the aspect ratio lowering material within the trench lowers the first aspect ratio to a second aspect ratio.
21. The method of claim 19 wherein forming the layer of the aspect ratio lowering material within the trench reduces the first depth by at least about a third to define a second depth.
22. The method of claim 18 further comprising forming a silicon oxide comprising layer adjacent the sidewalls and the base, the forming prior to the partial filling.
23. The method of claim 22 wherein the forming comprises a thermal oxidation of the sidewalls and base.
24. The method of claim 23 wherein the thermal oxidation is prior to the partial filling.
25. The method of claim 23 wherein the thermal oxidation is after the partial filling.
26. A method of forming a trench isolation structure comprising:
etching a trench into a semiconductor substrate, the trench having a first depth and a first width, wherein the ratio of the first depth to the first width defines an aspect ratio;
forming a first layer of material within the trench, the first layer partially filling the trench and lowering the aspect ratio and having a first composition;
converting the first composition to a second composition; and
after the converting, forming a second layer material over the first layer, the second layer essentially filling the trench.
27. The method of claim 26 wherein etching into a substrate comprises etching to form the trench having sidewalls and a base that define a first depth and a first width and wherein a ratio of the first depth to the first width further define a first aspect ratio.
28. The method of claim 27 wherein forming the first layer comprises forming an aspect ratio lowering material within the trench, the first layer lowering the first aspect ratio to a second aspect ratio.
29. The method of claim 27 wherein forming the first layer reduces the first depth by at least about a third to define a second depth.
30. The method of claim 26 wherein forming the first layer having a first composition comprises forming a silanol comprising layer.
31. The method of claim 30 wherein the silanol of the silanol comprising layer is selected from the group consisting of Si(OH)4, RSi(OH)3and mixtures thereof.
32. The method of claim 31, wherein RSi(OH)3is CH3(OH)3.
33. The method of claim 30 wherein converting the first composition to a second composition comprises converting at least some of the silanol of the silanol comprising layer to its equivalent oxide.
34. The method of claim 33 wherein the converting comprises maintaining the first layer at a temperature and a pressure effective to drive water from the first layer.
35. The method of claim 26 further comprising forming a layer of electrically insulative material adjacent the sidewalls and the base, the forming prior to forming the first layer.
36. The method of claim 26 further comprising oxidizing the sidewalls and the base, the oxidizing subsequent to forming the first layer.
37. The method of claim 26 further comprising forming a silicon oxide comprising layer adjacent the sidewalls and the base, the forming prior to forming the first layer.
38. The method of claim 37 wherein the forming comprises a thermal oxidation of the sidewalls and base.
39. The method of claim 37 wherein the thermal oxidation is prior to forming the first layer.
Patent Citations (24)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3990927 | 1976-11-01 | Montier | Examiner |
| US4474975 | 1984-10-01 | Clemons et al. | Applicant |
| US5156881 | 1992-10-01 | Okano et al. | Examiner |
| US5182221 | 1993-01-01 | Sato | Examiner |
| US5410176 | 1995-04-01 | Liou et al. | Examiner |
| US5470798 | 1995-11-01 | Ouellet | Examiner |
| US5719085 | 1998-02-01 | Moon et al. | Examiner |
| US5741740 | 1998-04-01 | Jang et al. | Examiner |
| US5776557 | 1998-07-01 | Okano et al. | Examiner |
| US5786039 | 1998-07-01 | Brouquet | Examiner |
| US5801083 | 1998-09-01 | Yu et al. | Examiner |
| US5863827 | 1999-01-01 | Joyner | Examiner |
| US5888880 | 1999-03-01 | Gardner et al. | Examiner |
| US5895253 | 1999-04-01 | Akram | Examiner |
| US5904540 | 1999-05-01 | Sheng et al. | Examiner |
| US5930645 | 1999-07-01 | Lyons et al. | Examiner |
| US5943585 | 1999-08-01 | May et al. | Examiner |
| US5950094 | 1999-09-01 | Lin et al. | Examiner |
| US5960299 | 1998-10-01 | Yew et al. | Examiner |
| US5972773 | 1999-10-01 | Liu et al. | Examiner |
| US5998280 | 1999-12-01 | Bergemont et al. | Examiner |
| US6030881 | 2000-02-01 | Papasouliotis et al. | Examiner |
| US6051477 | 2000-04-01 | Nam | Examiner |
| US6156674 | 2000-12-01 | Li et al. | Examiner |
Non-Patent Literature (7)
- Matsuura, M., et al., “A Highly Reliable Self-planarizing Low-k Intermetal Dielectric for Sub-quarter Micron Interconnects”, IEEE Jul. 1997, pp. 785-788.Applicant
- Horie, O., et al., “Kinetics and Mechanism of the Reactions of O(3P) with SiH4,CH2SiH3, (CH3)2(CH3), and (CH3)3SiH”, J. Phys. Vhem. 1991, vol. 95, pp. 4393-4400.Applicant
- Withnall, R., et al., “Matrix Reactions of Methylsilanes and Oxygen Atoms”, J. Phys. Chem. 1988, vol. 92, pp. 594-602.Applicant
- Joshi, A., et al., “Plasma Deposited Organosilicon Hydride Network Polymers as Versatile Resists for Entirely Dry Mid-Deep UV Photolithography”, SPIE vol. 1925, Jan. 1993, pp. 709-720.Applicant
- S. McClatchie et al.; “Low Dielectric Constant Flowfill® Technology For IMD Applications”; undated; 7 pages.Applicant
- A. Kiermasz et al.; “Planarisation for Sub-Micron Devices Utilising a New Chemistry”; Feb. 1995; 2 pages.Applicant
- K. Beekmann et al.; “Sub-micron Gap Fill adn In-Situ Planarisation using Flowfill® Technology”; Oct. 1995; pp. 1-7.Applicant