Method for forming a semiconductor memory device with increased coupling ratio

[0002] This application is a division of Ser. No. 08/789,529 filed Jan. 27, 1997 now U.S. Pat. No. 5,886,379.

[0003] The present invention relates to a method for manufacturing a semiconductor memory device, and more particularly, to an electrically erasable programmable read-only memory (EEPROM) device for increasing the coupling ratio.

[0004] Memory devices are largely divided into volatile memory devices in which stored information can be erased and new information can be stored, and non-volatile memory devices in which the stored information can generally be retained permanently.

[0005] As the volatile memory devices, there are random-access memories (RAMs) that allow information writing as well as information reading. As the non-volatile memory devices, there are read-only memories (ROMs), erasable programmable ROMs (EPROMs) and electrically erasable programmable ROMs (EEPROMs).

[0006] Among the non-volatile memory devices, the ROMs are devices in which programming cannot be performed again if information is stored therewith once. The EPROMs and EEPROMs are devices which can erase the stored information and be programmed again to store new information.

[0007] In the EPROMs and EEPROMs, the operation of programming an information is the same, but the methods for erasing the stored information are different from each other.

[0008] In other words, the EPROMs erase the stored information with ultraviolet (UV) light, while the EEPROMs erase the stored information electrically.

[0009] Among these memory devices, the EEPROMs will be described below.

[0010] A conventional EEPROM semiconductor memory device having an “ETOX” (EPROM Tunneling Oxide) will be described below with reference to the attached drawings.

[0011] FIGS. 1ato 1care cross-sectional views illustrating a method for manufacturing a conventional EEPROM memory device. FIGS. 2aand 2bare schematic view illustrating operations for programming and erasing data in the conventional EEPROM memory device.

[0012] As shown in FIG. 1c, a floating gate 3aand a control gate 5aare stacked on a P-type silicon substrate 1. As a source region and a drain region, first and second impurity regions 7 and 8 are formed in the P-type silicon substrate 1 on both sides of the floating gate 3a.

[0013] Here, between the P-type silicon substrate 1 and the floating gate 3a, and between the floating gate 3aand the control gate 5a, insulating films are formed.

[0014] Between the floating gate 3aand the control gate 5a, an insulating film 4 is formed with a thickness corresponding to a gate insulating film of a general transistor. Between the floating gate 3aand the P-type silicon substrate 1, a thin tunnel oxide film 2 is formed.

[0015] A method for manufacturing such a conventional EEPROM device will be described below.

[0016] As shown in FIG. 1a, on a P-type silicon substrate 1, a tunnel oxide film 2, a first polysilicon 3, an insulating film 4 and a second polysilicon 5 are deposited sequentially.

[0017] As shown in FIG. 1b, a photoresist film 6 is deposited on the second polysilicon 5. Then, through exposure and development process, a control gate region and a floating gate region are defined.

[0018] As shown in FIG. 1c, using the defined photoresist film 6 as a mask, the second polysilicon 5, insulating film 4, first polysilicon 3 and tunnel oxide film 2 are selectively removed to form a control gate 5aand a floating gate 3a.

[0019] Then, using the control gate 5aand floating gate 3aas a mask, n-type impurity ions of high concentration are implanted into the P-type silicon substrate 1, thereby forming first and second impurity regions 7 and 8.

[0020] The operation of the conventional EEPROM device having the ETOX is as follows.

[0021] In order to write data into one cell, as shown in FIG. 2a, a voltage of 7˜8V is applied to the second impurity region 8. A voltage pulse of 12˜13V is applied to the control gate 5a, and the first impurity region 7 and P-type silicon substrate 1 are grounded. Then, a high energy is created from the PN junction formed between the n-type second impurity region 8 and the P-type silicon substrate 1, thereby causing a breakdown. Due to the breakdown, hot electrons are generated.

[0022] Some of the hot electrons have energy higher than the energy barrier height (about 2.3V) between the P-type silicon substrate 1 and the tunnel oxide film 2. Thus, some of the hot electrons are injected into the floating gate 3afrom the P-type silicon substrate 1 through the tunnel oxide film 2, and stored therein. Such a method is called the channel hot electron injection method. This results in a cell having a logic “1” state in the binary system.

[0023] Referring to FIG. 2b, in order to erase the data written in the cell by the above described method, the P-type silicon substrate 1 and control gate 5aare grounded. A voltage pulse of 12˜13V is applied to the first impurity region 7. Then, through the portion of the thin tunnel oxide film 2 where the floating gate 3aoverlaps the first impurity region 7, the electrons are discharged from the floating gate 3ainto the first impurity region 7 by Fowler-Nordheim tunneling. Fowler-Nordheim tunneling dominantly occurs when the thickness of a tunneling oxide (e.g. tunnel oxide film 2) is below about 4-5 nm and the applied voltage is high. Fowler-Nordheim tunneling allows the electrons to be injected into the conduction band of the tunneling oxide by tunneling and thus into the impurity region.

[0024] At this time, as the quantity of electrons discharging from the floating gate 3ais increased gradually, the threshold voltage of the cell becomes low gradually. In general, erasing of the stored data is carried out so that the threshold voltage of the cell is maintained at 3V or less.

[0025] Accordingly, a logic “0” state is provided in the binary system.

[0026] In the EEPROM device having the conventional ETOX, a random access is possible when reading a data. Thus, the time required for reading the data can be relatively short.

[0027] The EEPROM device having the conventional ETOX has the coupling ratio (KW) as follows. The coupling ratio represents a voltage in the floating gate induced by an external voltage applied to the control gate. Therefore, the greater the capacitance between the control gate and the floating gate, the greater the coupling ratio will be. $KW=\frac{\mathrm{C1}}{\mathrm{C1}+\mathrm{C2}+\mathrm{C3}+\mathrm{C4}}$

[0028] Here, C1 represents the capacitance between the control gate 5aand the floating gate 3a,

[0029] C2 represents the capacitance between the source and the floating gate 3a,

[0030] C3 represents the capacitance between the substrate 1 and the floating gate 3a, and

[0031] C4 represents the capacitance between the drain and the floating gate 3a. During erasing, the coupling ratio is as follows. $KW=1-\frac{\mathrm{C4}}{\mathrm{C1}+\mathrm{C2}+\mathrm{C3}+\mathrm{C4}}$

[0032] Further, a program voltage Vp for the EEPROM is as follows. $\mathrm{Vp}=\frac{Qfg}{Cr}+\frac{Vcg\mathrm{C1}+Vb\mathrm{C4}+Vsub\mathrm{C3}+Vs\mathrm{C2}}{Cr}$

[0033] Here, Qfg represents the charge of the floating gate 3a,

[0034] Cr=C1+C2+C3+C4,

[0035] Vcg represents the control gate voltage,

[0036] Vb represents the drain voltage,

[0037] Vsub represents the substrate voltage, and

[0038] Vs represents the source voltage.

[0039] According to the above equations, it is desirable to have a high coupling ratio so that effective programming can be carried out. To obtain the high coupling ratio, the capacitance between the control gate and the floating gate should be increased. By increasing the cell size, the capacitance between the control gate and the floating gate can be increased. But, increasing the cell size causes a great difficulty in high density device packing.

[0040] Therefore, in the conventional EEPROMs, a high voltage must be applied to the drain in an attempt to compensate for the low coupling ratio. As a result, the conventional EEPROMs have problems in that they consume high power and are less reliable for effective programming.

[0041] In order to solve the aforementioned and other problems, the present invention provides a semiconductor memory device and a method for manufacturing the same, in which the coupling ratio for a floating gate and a control gate is increased so that writing is possible even if a low voltage is applied to the drain/source.

[0042] In accordance with the present invention a semiconductor memory device includes a semiconductor substrate, a tunneling insulating film formed on the semiconductor substrate, a floating gate formed on the tunneling insulating film and having a bent on one side thereof, a dielectric layer formed on the surface of the floating gate, a control gate formed on the dielectric layer, and first and second impurity regions formed in the substrate on both sides of the floating gate.

[0043] Further, in accordance with the present invention a method for manufacturing a semiconductor memory device including the steps of preparing a semiconductor substrate; sequentially forming a tunneling insulating film, a first conductor layer, and an insulating film; selectively removing the tunneling insulating film to form a contact hole; forming a second conductor layer on the entire surface so that the second conductor layer is connected to the first conductor layer through the contact hole; defining a unit cell region by centering around the contact hole to selectively remove the second and first conductor layers and to remove the insulating film to form a floating gate; forming a dielectric layer on the exposed surface of the floating gate; forming a control gate on the dielectric layer; and forming first and second impurity regions in the semiconductor substrate on both sides of the floating gate.

[0044] Further scope of applicability of the present invention will become apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.

[0045] Briefly described, the present invention is directed to a semiconductor memory device including a semiconductor substrate, a tunneling film formed on the semiconductor substrate, first and second gates formed on the tunneling film, a dielectric layer formed between the first and second gates, and first and second impurity regions formed in the semiconductor substrate adjacent the tunneling film, wherein one of the first gate and the second gate has a projecting portion.

[0046] Further, the present invention is directed to a semiconductor memory device including a semiconductor substrate, a tunneling insulating film formed on the semiconductor substrate, a first gate formed on the tunneling insulating film and having a substantially jar shape, a second gate formed on the tunneling insulating film and having a substantially I-shape, a dielectric layer formed between the first and second gates, and first and second impurity regions formed in the semiconductor substrate adjacent the first gate.

[0047] The present invention is also directed to a method for manufacturing a semiconductor memory device, including the steps of forming a tunneling film and a first conductor layer on a semiconductor substrate; forming a second conductor layer connected to the first conductor through a contact hole so as to form a floating gate; forming a dielectric layer on the floating gate; forming a control gate on the dielectric layer; and forming first and second impurity regions in the semiconductor substrate adjacent the floating gate.

[0048] The present invention is further directed to a method for manufacturing a semiconductor memory device, including the steps of forming a tunneling insulating film and a first conductor layer on a semiconductor substrate; forming a second conductor layer having a contact hole therethrough on the first conductor layer so as to form a floating gate; forming a dielectric layer on a surface of the floating gate; forming a control gate on the dielectric layer; and forming first and second impurity regions in the semiconductor substrate adjacent the floating gate.

[0049] The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and, thus, are not limitative of the present invention, and wherein:

[0050] FIGS. 1ato 1care cross-sectional views illustrating a method for manufacturing a conventional flash memory device;

[0051] FIGS. 2aand 2bare schematic views for illustrating operations for writing and erasing data in the conventional flash memory device;

[0052] FIGS. 3ato 3jare cross-sectional views for illustrating a method for manufacturing an EEPROM device, according to a first embodiment of the present invention;

[0053] FIGS. 4ato 4hare cross-sectional views for illustrating a method for manufacturing an EEPROM device, according to a second embodiment of the present invention;

[0054] FIGS. 5aand 5bare schematic views for illustrating operations for writing and erasing data in the first embodiment of the present invention; and

[0055] FIGS. 6aand 6bare schematic views for illustrating operations for writing and erasing data in the second embodiment of the present invention.

[0056] Hereinafter, a semiconductor memory device and a method for manufacturing the same according to the present invention will be described with reference to the attached drawings.

[0057] FIGS. 3ato 3jare cross-sectional views for illustrating a method for manufacturing an EEPROM device according to a first embodiment of the present invention.

[0058] As shown in FIG. 3a, a thin tunnel oxide film 32, a first polysilicon layer 33aand a nitride film 34 are sequentially deposited on a semiconductor substrate 31.

[0059] A first photoresist film 35 is deposited on the nitride film 34. Then, the first photoresist film 35 is exposed and developed to thereby expose a predetermined portion of the nitride film 34.

[0060] As shown in FIG. 3b, using the first photoresist film 35 as a mask, the exposed nitride film 34 is selectively removed to form a contact hole 34athrough the nitride film 34. The first photoresist film 35 is removed.

[0061] As shown in FIG. 3c, a second polysilicon layer 33bis deposited on the entire surface so that the first and second polysilicon layers 33aand 33bare connected through the contact hole 34a. After depositing a second photoresist film 36 on the second polysilicon layer 33b, the second photoresist film 36 is exposed and developed to define a unit cell region.

[0062] As shown in FIG. 3d, using the patterned second photoresist film 36 as a mask, the first and second polysilicon layers 33aand 33band the nitride film 34 are etched selectively. Then the second photoresist film 36 is removed.

[0063] As shown in FIG. 3e, after depositing a third photoresist film 37 on the second polysilicon layer 33b, the third photoresist film 37 is exposed and developed to thereby form a third photoresist film 37 pattern.

[0064] At this time, the third photoresist film 37 pattern is formed to have a width narrower than that of the pattern of second photoresist film 36.

[0065] As shown in FIG. 3f, using the third photoresist film 37 pattern as a mask, the exposed second polysilicon layer 33bis selectively removed and the nitride film 34 is completely removed, thereby forming a floating gate 33 having a predetermined shape.

[0066] As shown in FIG. 3g, a high temperature and low pressure dielectric (HLD) layer 38 is formed over the exposed surface of floating gate 33.

[0067] As shown in FIG. 3h, a third polysilicon layer 39ais deposited on the entire surface of tunnel oxide film 32 and over the high temperature and low pressure dielectric (HLD) layer 38.

[0068] After depositing a fourth photoresist film 40 on the third polysilicon layer 39a, the fourth photoresist film 40 is exposed and developed to define a unit cell region having the size same as the patterned second photoresist film 36. For example, the width of the fourth photoresist film 40 is same as the width of the patterned second photoresist film 36.

[0069] As shown in FIG. 3i, using the patterned fourth photoresist film 40 as a mask, the exposed third polysilicon layer 39aand tunnel oxide film 32 are selectively etched to form a control gate 39 having a predetermined shape embracing the shape of the floating gate 33.

[0070] As shown in FIG. 3j, using the control gate 39 and floating gate 33 as a mask, n-type impurity ions of high concentration are implanted into the substrate 31 to form first and second impurity regions 41 and 42 as source and drain regions. Here, although the first impurity region 41 is shown as the source region, it can also be designated as the drain region. As a result, an EEPROM device having an increased contact area between the control gate and the floating gate is formed. The increased contact area increases the capacitance between the control gate and floating gate and thus the coupling ratio is increased without increasing the cell size.

[0071] Meanwhile, FIGS. 4ato 4hare cross-sectional views for illustrating a method for manufacturing an EEPROM device, according to a second embodiment of the present invention.

[0072] As shown in FIG. 4a, a thin tunnel oxide film 52, a first polysilicon layer 53aand a nitride film 54 are sequentially deposited on a semiconductor substrate 51.

[0073] A first photoresist film 55 is deposited on the nitride film 54. The first photoresist film 55 is exposed and developed to thereby expose predetermined portions of the nitride film 54.

[0074] As shown in FIG. 4b, using the patterned first photoresist film 55 as a mask, the exposed nitride film 54 is selectively removed to form a nitride film pattern 54a. Then the first photoresist film 55 is removed.

[0075] As shown in FIG. 4c, a second polysilicon layer 53bis deposited on the first polysilicon layer 53aand the nitride film pattern 54aso that the first and second polysilicon layers 53aand 53bare directly connected to each other. After depositing a second photoresist film 56 on the second polysilicon layer 53b, the second photoresist film 56 is exposed and developed to form a pattern which exposes a portion of the second polysilicon layer 53b.

[0076] As shown in FIG. 4d, using the second photoresist film 56 pattern as a mask, the exposed second polysilicon layer 53bis selectively removed and all of the nitride film pattern 54ais removed. Then the second photoresist film 56 is removed. As a result, a hole region 53′ is formed in the middle of the polysilicon layers 53aand 53b.

[0077] As shown in FIG. 4e, a high temperature and low pressure dielectric (HLD) layer 57 is formed on the exposed surface of first and second polysilicon layers 53aand 53bincluding the hole region 53′.

[0078] As shown in FIG. 4f, a third polysilicon layer 58ais deposited on the entire surface of high temperature and low pressure dielectric (HLD) layer 57. After depositing a third photoresist film 59 on the entire third polysilicon layer 58a, the third photoresist film 59 is exposed and developed to thereby define a unit cell region.

[0079] As shown in FIG. 4g, using the patterned third photoresist film 59 as a mask, the first, second and third polysilicon layers 53a, 53band 58a, the high temperature and low pressure dielectric (HDL) layer 57 and the tunnel oxide film 52 are selectively removed to form a control gate 58 and a floating gate 53.

[0080] As shown in FIG. 4h, using the control gate 58 and the floating gate 53 as a mask, n-type impurity ions of high concentration are implanted into the substrate 51 to form first and second impurity regions 60 and 61 as source and drain regions. Although the first impurity region 60 is shown as the source region, it is possible to have the first impurity region 60 as the drain region. As a result, a semiconductor memory device having an increased contact area and an increased coupling ratio is formed.

[0081] FIGS. 5aand 5band FIGS. 6aand 6bare cross-sectional views of a unit cell of a memory device of the present invention for illustrating operational principles of the present invention.

[0082] In the semiconductor memory device according to the first embodiment of the present invention, as shown in FIGS. 5aand 5b, the tunnel oxide film 32 is formed on a predetermined portion of the semiconductor substrate 31 overlapping portions of the impurity regions 41 and 42. The floating gate 33 is formed with an “I” shape on the tunnel oxide film 32. The dielectric layer 38 is formed on surfaces of the floating gate 33.

[0083] The control gate 39 having an “inverse jar” shape is formed on the dielectric layer 38. The first and second impurity regions 41 and 42 of source/drain regions are formed in the semiconductor substrate 31 on both sides of the floating gate 33 and control gate 39.

[0084] The floating gate 33 has a structure which can be divided into three floating gates. That is, the first floating gate is formed on the tunnel oxide film 32, the second floating gate is formed on the center of the first floating gate, and the third floating gate is formed so that its center is connected to the second floating gate. The third floating gate is positioned parallel to the first floating gate. The first, second and third floating gates of the gate 33 are electrically connected to one another.

[0085] The control gate 39 is formed on the dielectric layer 38 and partially surrounds the floating gate 33. Further, the floating gate 33 overlaps the first and second impurity regions 41 and 42 at the edges thereof.

[0086] Meanwhile, in the semiconductor memory device according to the second embodiment of the present invention, as shown in FIGS. 6aand 6b, the tunnel oxide film 52 is formed on a predetermined portion of the semiconductor substrate 51. The floating gate 53 has the shape of a “jar” and is formed on the tunnel oxide film 52. The dielectric layer 57 is formed on the surfaces of floating gate 53.

[0087] The control gate 58 having an “I” shape is formed on the dielectric layer 57. The first and second impurity regions 60 and 61 of source/drain regions are formed in the semiconductor substrate 51 on both sides of the floating gate 53 and control gate 58.

[0088] The floating gate 53 can be divided into a plurality of floating gates. That is, the first floating gate of the gate 53 is formed on the tunnel oxide film 52. The second and third floating gates are formed on the upper side of the ends of the first floating gate, respectively, so that the second and third floating gates are connected to the first floating gate. On the second floating gate, the fourth floating gate is formed such that one side of the fourth floating gate is connected to the second floating gate and the other side thereof extends towards the fifth floating gate, parallel to the first floating gate. On the third floating gate, the fifth floating gate is formed such that one side of the fifth floating gate is connected to the third floating gate and the other side thereof extends toward the fourth floating gate, parallel to the first floating gate. The fifth floating gate does not directly contact the fourth floating gate. The first through fifth floating gates together as a whole define a “jar” shape of the floating gate 53.

[0089] The control gate 58 has the following structure and can be divided into first through third control gates. The first control gate is formed on the dielectric layer 57 so as to fill a space region defined by the first, second, third, fourth and fifth floating gates. The second control gate is formed between the fourth and fifth floating gates and extends from the center of the first control gate. The third control gate is formed over the upper sides of the fourth and fifth floating gates and on the second control gate so as to be connected with the second control gate. The first through third control gates together as a whole define an “I” shape of control gate 58.

[0090] The operation method of the semiconductor memory device constructed according to the first and second embodiments of the present invention is described below.

[0091] In order to write a data into one cell of the memory device, as shown in FIG. 5aand FIG. 6a, a proper voltage of V_CG>Vp is applied to the control gates 39 and 58. The first impurity regions 41 and 60 and the substrates 31 and 51 are grounded. A voltage of V_D≠0 is applied to the second impurity regions 42 and 61.

[0092] At this time, the voltage applied to the control gates 39 and 58 and the voltage applied to the second impurity regions 42 and 61 are lower than those of the prior art.

[0093] Then, hot electrons are generated between the second impurity regions 42 and 61 and the substrates 31 and 51. Some of the hot electrons are injected into the floating gates 33 and 53 from the substrates 31 and 51 through the tunnel oxide films 32 and 52, and are stored therein. As a result, the writing operation is completed without applying high external voltages.

[0094] In order to erase the data written in one cell by the above described method, the substrates 31 and 51 and the control gates 39 and 58 are grounded, as shown in FIGS. 5band 6b. With the second impurity regions 42 and 61 in floating states, a pulse voltage V is applied to the first impurity regions 41 and 60.

[0095] At this time, the pulse voltage V applied to the first impurity regions 41 and 60 is lower than that of the prior art.

[0096] Then, through the portion of the tunnel oxide films 32 and 52 where the floating gates 33 and 53 overlap the first impurity regions 41 and 60, respectively, the electrons stored in the floating gates 33 and 53 are respectively discharged into the first impurity regions 41 and 60 by Fowler-Nordheim tunneling.

[0097] At this time, as the quantity of electrons discharging from floating gates 33 and 53 is gradually increased, the threshold voltage of the cell becomes low gradually. In general, erasing is carried out so as to maintain the threshold voltage of the cell at or less than 3V.

[0098] As described above, the semiconductor memory device of the present invention offers the following advantages.

[0099] First, the capacitance between the floating gate and the control gate is increased, enlarging the coupling ratio. Thus, the efficiency of writing is improved.

[0100] Second, since the coupling ratio is increased, the voltage applied to the control gate and the first and second impurity regions during writing/erasing can be decreased. Thus, power consumption is reduced.

[0101] Third, since the coupling ratio is increased, in case that the same gate voltage is applied, the read current is increased to thereby decrease the access time.

[0102] The invention being thus described, it will be obvious that the same may be varied in many ways. Such variations are not to be regarded as a departure from the spirit and scope of the invention, and all such modifications as would be obvious to one skilled in the art are intended to be included within the scope of the following claims.