Self-aligned contact for closely spaced transistors

[0002] The field of the invention is integrated circuit processing, in particular, forming self-aligned contacts.

[0003] In arrays of closely spaced transistors, such as in DRAM memory arrays, it is known to form a self-aligned contact as illustrated in FIG. 1, in which two closely spaced transistors have an aperture formed in the area between them, which is also the location of a bitline buried in the substrate.

[0004] Sidewall spacers 35 (preferably oxide) isolate the contact from the two gates. It should be noted that there is a thick nitride cover 50 (illustratively 200 nm thick) over the gate stack that protects the gate during the etching process that forms the aperture for the contact. Unfortunately, this thick layer produces variation in linewidth across the chip that is unacceptable for high performance logic applications. The term high performance logic chips as used here means the transistor generation with very short gate length (on the order of 0.1 um Leff). These short gate length features on a logic chip require extremely precise control of physical dimensions and can tolerate only very small ACLV (across chip linewidth variation) to provide high performance, since the gate length has a direct effect on the current output of the transistor. The use of standard DRAM processing such as a thick nitride cap gate stack does not produce acceptable ACLV. In order to fulfill the ACLV requirement, standard logic process typically uses a simpler and thinner gate stack as seen in FIG. 2. With such a thinner gate stack, the variation on final gate length associated with processing is significantly smaller and able to satisfy the ACLV requirements.

[0005] The invention relates to forming a self-aligned contact that is compatible with high performance logic processing. A feature of the invention is the use of a pair of transistors with standard logic gate stack containing only doped polysilicon 30 (illustratively 100 nm thick) on gate oxide where self-aligned contacts to be formed in the space between the transistor pair. The polysilicon is pre-doped to obtain low resistance for the gate contact. In the conventional DRAM thick gate stack, this low resistance is achieved by building a composite stack with silicide metal over polysilicon.

[0006] Once the gates are completed with sidewall spacer 35, followed by the use of a conventional logic process to deposit the etch stop nitride layer 55 and BPSG dielectric layer 60 over the gates, a photo process defines the contact opening in the dielectric which is self-aligned between the transistor pair as depicted in FIG. 2. As in standard processing, a cap nitride liner 55 is used as a first etch stop in the initial partial BPSG dielectric etch removal (FIG. 2). A feature of the present invention is the deliberate removal of that nitride liner in a shoulder region of the gate adjacent to the contact (FIG. 3); followed by removal of the remaining BSPG dielectric film in the contact area (FIG. 4). With nitride liner protecting the contact area at the bottom of the aperture, the exposed polysilicon gate shoulder is then oxidized (FIG. 5). The remaining nitride liner is then removed to open up the contact (FIG. 6).

[0007] FIG. 1 illustrates a prior-art self-aligned contact.

[0008] FIGS. 2-7 illustrate steps in the inventive process.

[0009] Referring now to FIG. 2, there is shown a pair of transistors separated by a common node 15, also referred to as the contact region. One common example of such an arrangement is a DRAM array in which the transistors share a bitline. SRAM arrays have the same configuration. Another example is that of an inverter in which the transistors are separated by the output node.

[0010] In the prior art example shown in FIG. 1, the thick nitride etch stop layer 50 protected the transistor gates during the contact etch, but the entire thickness of the nitride cap DRAM gate stack on order of 350 nm results in critical dimension variation typically 70-100 nm across the circuit that may exceed the tight requirements of the logic applications which are on the order of 10-20 nm for ACLV. This is because a thicker and composite film gate stack requires more complicated and longer etching processes that often produce larger variation at the final gate dimension. While this is acceptable for DRAMS, it is not acceptable for logic processing for applications with gate widths requirements of less than about 0.1 μm for advanced generations of logic chips. On the other hand, a logic gate stack is much thinner and simpler, hence processing these stacks provides the means to obtain acceptable ACLV requirements for logic chips.

[0011] According to the invention, the transistors do not use the silicide layer and thick etch stop layer of the prior art. Instead, the poly gate layer is is doped and capped only by the barrier nitride (cap or liner layer) 55 (illustratively 20 nm thick), omitting the silicide and thick nitride layers. FIG. 2 illustrates the result of a partial timed etch through a BPSG dielectric using standard Flourine dry etch chemistry , with the barrier nitride protecting the transistor gate. It will be noted that there is a remaining amount of BPSG 61 at the bottom of the contact aperture, in contrast to the prior art method.

[0012] Next, as shown in FIG. 3, the etch is continued with Bromine chemistry that attacks nitride 55, removing it in the areas denoted with brackets 132. The nitride etch process should be selective to the poly film and the sidewall oxide. The cap nitride 55 is etched back along the top of poly gate layer 30 and behind BPSG remainder 62. The conventional oxide sidewall 35 of gate 30 serves to protect the side of the poly gate during this step, but the poly of the gate is exposed on its top surface, so that the chemistry must be chosen such that gate 30 is not attacked. This deliberate removal of the nitride on the shoulder portion of the gate is in contrast to the prior art, in which care is taken to preserve the shoulder portion of the cap nitride layer.

[0013] Referring to FIG. 4, BPSG remainder 61 is removed in an etch step using selective Fluorine chemistry that does not attack poly, oxide or the liner nitride at the contact.

[0014] Next, as shown in FIG. 5, a rapid thermal oxide step (illustratively 700° C. for 10 minutes) forms a thin shoulder layer of oxide 135 on the exposed top of poly gate layer 30. A thin layer of only 20 nm is sufficient for the purposes of the invention.

[0015] The remainder of cap nitride 55 and gate oxide 20 is removed in a final etch that etches nitride faster than oxide. Since gate oxide is very thin (on order of 5 nm), the sidewall oxide will be preserved. Illustratively, both Fluorine and Bromine chemistry can achieve this goal.

[0016] Thus, the same layers have been removed as in the prior art, but instead of a single integrated etch to remove all the BPSG and the liner nitride to open the contact, there is now a first BPSG removal, followed by a nitride strip, a second BPSG removal, and an oxidation followed by the nitride liner opening step.

[0017] The benefit of this extra effort is the ability to maintain logic process integration schemes to meet ACLV requirements while allowing the formation of self-aligned contacts which would be necessary for cell size reduction in logic based embedded DRAM applications. After this point, conventional steps are used to fill in the aperture with conductive material and to complete the back end processing. These steps are referred to as “completing the integrated circuit” for purposes of the following claims.

[0018] The resulting structure shown in FIG. 7 is that of two CMOS transistors having transistor gates disposed above a substrate and along a transverse axis with a common contact area in said substrate and between said transistor gates, each of said transistor gates having an oxide sidewall adjacent a nitride barrier layer on an outer side thereof and said nitride barrier layer adjacent an outer portion of a top surface thereof, each of said transistor gates having a first oxide sidewall adjacent a lower portion of an inner side thereof and a thermally grown oxide adjacent an upper portion of said inner side thereof and on an inner portion of said top surface thereof, with the contact material 110 filling the space between the two adjacent oxides and extending vertically to connection member.

[0019] Contacts that are not closely spaced may also use this process or they can be made with the standard logic process for contact formation which does not involve the nitride liner removal and shoulder oxidation steps. This is simply achieved by a separate masking step. The choice of method will be subject to the usual tradeoffs. If a “non-close” space contact aperture does not expose the cap nitride, then the nitride shoulder strip step will have no effect.

[0020] The invention includes the deliberate removal of nitride, oxidation via RTO, or ozone-ambient RTO to allow thicker oxide growth at lower temperature compared with standard RTO. While a thicker oxide provides a more robust contact to gate isolation, it is important to minimize processing temperature during the oxide growth to avoid redistribution of the junction and well dopants. This described invention uses RTO as an example for this new self-aligned contact formation method. Other oxidation methods of polysilicon/silicon using oxygen radicals generated either by heat and or by ozone high pressure deposition process could also be applied. Another alternative is the formation of insulating materials such as SiO₂through surface reaction processes for self-aligned contacts. In summary, any selective oxide growth on exposed polysilicon region via surface reaction mechanism such as by either low temperature oxidation or ozone deposition would applied.

[0021] While the invention has been described in terms of a single preferred embodiment, those skilled in the art will recognize that the invention can be practiced in various versions within the spirit and scope of the following claims.