Data storage system having a host computer coupled to bank of disk drives through interface comprising plurality of directors, two pairs of buses, and memory sections

[0002] This invention relates generally to data storage systems, and more particularly to data storage systems having redundancy arrangements to protect against total system failure in the event of a failure in a component or subassembly of the storage system.

[0003] As is known in the art, large mainframe computer systems require large capacity data storage systems. These large main frame computer systems generally includes data processors which perform many operations on data introduced to the computer system through peripherals including the data storage system. The results of these operations are output to peripherals, including the storage system.

[0004] One type of data storage system is a magnetic disk storage system. Here a bank of disk drives and the main frame computer system are coupled together through an interface. The interface includes CPU, or “front end”, controllers (or directors) and “back end” disk controllers (or directors). The interface operates the controllers (or directors) in such a way that they are transparent to the computer. That is, data is stored in, and retrieved from, the bank of disk drives in such a way that the mainframe computer system merely thinks it is operating with one mainframe memory. One such system is described in U.S. Pat. No. 5,206,939, entitled “System and Method for Disk Mapping and Data Retrieval”, inventors Moshe Yanai, Natan Vishlitzky, Bruno Alterescu and Daniel Castel, issued Apr. 27, 1993, and assigned to the same assignee as the present invention.

[0005] As described in such U.S. Patent, the interface may also include, in addition to the CPU controllers (or directors) and disk controllers (or directors), addressable cache memories. The cache memory is a semiconductor memory and is provided to rapidly store data from the main frame computer system before storage in the disk drives, and, on the other hand, store data from the disk drives prior to being sent to the main frame computer. The cache memory being a semiconductor memory, as distinguished from a magnetic memory as in the case of the disk drives, is much faster than the disk drives in reading and writing data.

[0006] The CPU controllers, disk controllers and cache memory are interconnected through a backplane printed circuit board. More particularly, disk controllers are mounted on disk controller printed circuit boards. CPU controllers are mounted on CPU controller printed circuit boards. And, cache memories are mounted on cache memory printed circuit boards. The disk controller, CPU controller and cache memory printed circuit boards plug into the backplane printed circuit board. In order to provide data integrity in case of a failure in a controller, the backplane printed circuit board has a pair of buses. One set the disk controllers is connected to one bus and another set of the disk controllers is connected to the other bus. Likewise, one set the CPU controllers is connected to one bus and another set of the CPU controllers is connected to the other bus. The cache memories are connected to both buses. Each one of the buses provides data, address and control information.

[0007] Thus, the use of two buses provides a degree of redundancy to protect against a total system failure in the event that the controllers, or disk drives connected to one bus fail. Further, the use of two buses increases the data transfer bandwidth of the system compared to a system having a single bus.

[0008] In accordance with the present invention, a data storage system is provided wherein a host computer is coupled to a bank of disk drives through a system interface. The system interface includes a memory having a high address memory section and a low address memory section. A plurality of directors controls data transfer between the host computer and the bank of disk drives as such data passes through the memory. A pair of high address busses is in communication with the high address memory section and a pair of low address busses is in communication with the low address memory section. Each one of the directors is in communication with one of the pair of high address busses and one of the pair of low address busses.

[0009] In accordance with another feature of the invention, the system interface includes a printed circuit board having a plurality of electrical connectors arranged in a linear array and electrically connected to the busses. The electrical connectors are adapted to receive the directors and the memory and electrically interconnect the directors and memory received therein to the busses. A first set of the directors is electrically connected to a first pair of the busses and a second set of directors interleaved with the first set is electrically connected to a second pair of the busses.

[0010] In accordance with still another feature of the invention, each one of the electrical connectors has three sections. For the electrical connectors which receive the first set of directors, such electrical connectors have a first one of the three section connected to a first one of the busses in the first pair of busses and a second one of the three sections connected to a second one of the busses in the first pair of busses. For the second set of directors, the electrical connectors have the first one of the three section connected to a first one of the busses in the second pair of busses and the second one of the three sections connected to a second one of the busses in the second pair of busses.

[0011] In accordance with another feature of the invention, for the electrical connectors which receive memory sections, one such electrical connector has the first one of the three section connected to the first one of the busses in the first pair of busses and a third one of the three sections connected to the second one of the busses in the second pair of busses. Another one of the electrical connectors connected to a memory section has the first one of the three section connected to the second one of the busses in the first pair of busses and the third one of the three sections connected to the second one of the busses in the second pair of busses.

[0012] In accordance with still another feature of the invention, the printed circuit board includes a universal electrical connector adapted to receive either a director or a memory. The universal electrical connector has the three section. The first section of the connector is connected to either the first one of the busses in the first pair thereof or to the first one of the busses in the second pair thereof. The second section of the connector is connected to either the second one of the busses in the first pair thereof or to the second one of the busses in the second pair thereof. The third section of the connector is connected to the second one of the busses in the second pair thereof or to the second one of the busses in the first pair thereof.

[0013] These and other features of the invention will become more readily apparent from the following detailed description when read together with the accompanying drawings, in

[0014] FIG. 1 shows the relationship between FIGS. 1A and 1B which when taken together is a block diagram of a data storage system according to the invention;

[0015] FIG. 2 shows the relationship between FIGS. 2A and 2B which when taken together is a diagram showing a layout of the data storage system of FIG. 1;

[0016] FIG. 3 is an isometric sketch of a system interface used in the system of FIG. 1;

[0017] FIGS. 4A-4C are front, top, and side diagrammatical sketches, respectively, of a backplane printed circuit board and electrical connectors therein used in the system interface of FIG. 3;

[0018] FIG. 5 is a schematic diagram of an exemplary one of a plurality of rear-end directors used in the system of FIG. 1;

[0019] FIG. 5A is a schematic diagram of a reference voltage generator used in the director of FIG. 5;

[0020] FIG. 6 is a schematic diagram of an exemplary one of a plurality of front-end directors used in the system of FIG. 1;

[0021] FIG. 7 is a schematic diagram of a memory section used in the system of FIG. 1;

[0022] FIG. 8 is a schematic diagram of a pair of adjacent I/O adapter cards, their associated rear-end directors and SCSI I/O interface of the directors interconnected through the backplane printed circuit board of FIG. 3 in accordance with the invention;

[0023] FIG. 9 shows the relationship between FIGS. 9A and 9B which when taken together is a diagram showing a layout of the data storage system of FIG. 1 and the backplane interconnections made between the SCSI I/O interfaces of adjacent ones of the directors;

[0024] FIG. 10 is a schematic diagram showing Vref generators used in the system of FIG. 1 and interconnected in accordance with the invention;

[0025] FIG. 11 is a schematic diagram of the Vref generator of FIG. 1, such generator being on one of the I/O adapter cards used in the system of FIG. 1;

[0026] FIG. 11A is a schematic diagram of an alternative Vref generator of FIG. 1; such generator being on one of the I/O adapter cards used in the system of FIG. 1;

[0027] FIG. 12 shows the relationship between FIGS. 12A and 12B which when taken together is a diagram showing a layout of the data storage system of FIG. 1 and the Vref generators of FIG. 11;

[0028] FIG. 13 is a schematic diagram showing connections between directors system of FIG. 1 and bus arbiters in such system according to the invention;

[0029] FIG. 14 is a schematic diagram of a master and slave arbiter connected to one of a plurality of busses used in the system of FIG. 1 and connected to a plurality of directors used in such system, such arbiters being adapted to arbitrate between requests for access to the bus by such directors;

[0030] FIG. 15 is a diagrammatical sketch of a portion of the backplane of FIG. 3, such sketch showing pin connections to configure one of the arbiters in FIG. 14 as the master arbiter and the other one of the arbiters as the slave arbiter;

[0031] FIG. 16 is a block diagram of an exemplary of one of the arbiters of FIG. 14 according to the invention;

[0032] FIG. 17 is a schematic diagram of a priority request synchronizer and decoder used in the arbiter of FIG. 16;

[0033] FIG. 18 is a schematic diagram of a section of the arbiter of FIG. 16 used to generate, for each one of a plurality of priority request types issued by the directors, a director grant;

[0034] FIG. 19 is a schematic diagram of a low priority and high priority toggle section of the arbiter of FIG. 17 to insure that a low priory request is granted at least after a predetermined grants of a high priority requests and to toggle between a pair of such high priority requests;

[0035] FIG. 20 is a schematic diagram of a logic section used in the toggle section of FIG. 19.

[0036] Referring now to FIG. 1, a data storage system 10 is shown wherein a host computer 12 is coupled to a bank 14 of disk drives through a system interface 16. The system interface 16 includes a cache memory 18, having high address memory sections 18H and low address memory sections 18L. A plurality of directors 20₀-20₁₅is provided for controlling data transfer between the host computer 12 and the bank 14 of disk drives as such data passes through the cache memory 18. A pair of high address busses TH, BH is electrically connected to the high address memory sections 18H. A pair of low address busses TL, BL electrically connected to the low address memory sections 18L. The cache memory 18 has a plurality of storage location addresses. Here, the storage locations having the higher addresses are in the high address memory sections 18H and the storage locations having the lower addresses are in the low address memory sections 18L. It should be noted that each one of the directors 20₀-20₁₅is electrically connected to one of the pair of high address busses TH, BH and one of the pair of low address busses TL, BL. Thus, each one of the directors 20₀-20₁₅is able to address all locations in the entire cache memory 18 (i.e., to both the high address memory sections 18H and the low address memory sections 18L) and is therefore able to store data in and retrieve data from any storage location in the entire cache memory 18.

[0037] More particularly, a rear-end portion of the directors, here directors 20₀-20₃and 20₁₂-20₁₅, is electrically connected to the bank 14 of disk drives through I/O adapter cards 22₀-22₃and 22₁₂-22₁₅and a front-end portion of the directors, here directors 20₄-20₁₁, is electrically connected to the host computer 12 through I/O adapter cards 22₄-22₁₁. It should also be noted that each end of the busses TH, TL, BH, BL terminates in a pair of master and slave arbiters bus arbiters 24_AmTH, 24_ASTH; 24_AMTL, 24_ASTL, 24_AMBH, 24_ASBH; 24_AMBL, 24_ASBL, respectively; and a pair of a pair of reference voltage (Vref) generator 28TH1, 28TH2; 28TL1, 28TL2; 28BH1, 28BH2; 28BL1, 28BL2, respectively.

[0038] In operation, when the host computer 12 wishes to store data, the host computer 12 issues a write request to one of the front-end directors 20₄-20₁₁to perform a write command. One of the front-end directors 20₄-20₁₁replies to the request and asks the host computer 12 for the data. After the request has passed to the requesting one of the front-end directors 20₄-20₁₁, the director determines the size of the data and reserves space in the cache memory 18 to store the request. The front-end director then produces control signals on either a high address memory bus (TH or BH) or a low address memory bus (TL, BL) connected to such front-end director depending on the location in the cache memory 18 allocated to store the data and enable the transfer to the cache memory 18. The host computer 12 then transfers the data to the front-end director. The front-end director then advises the host computer 12 that the transfer is complete. The front-end director looks up in a Table, not shown, stored in the cache memory 18 to determine which one of the rear-end directors 20₀-20₃and 20₁₂-20₁₅is to handle this request. The Table maps the host computer 12 address into an address in the bank 14 of disk drives. The front-end director then puts a notification in a “mail box” (not shown and stored in the cache memory 18) for the rear-end director which is to handle the request, the amount of the data and the disk address for the data. Other rear-end directors poll the cache memory 18 when they are idle to check their “mail boxes”. If the polled “mail box” indicates a transfer is to be made, the rear-end director processes the request, addresses the disk drive in the bank, reads the data from the cache memory and writes it into the addresses of a disk drive in the bank 14. When data is to be read from the disk drive to the host computer 12 the system operates in a reciprocal manner.

[0039] More particularly, and referring also to FIGS. 2 and 3, the system interface 16 includes a backplane printed circuit board 30 having a plurality of, here 20, electrical connectors 32₀-32₁₉, or slots, arranged successively and uniformly spaced in a linear array. The electrical connectors 32₀-32₁₉are connected selectively to the busses TH, TL, BH, BL, such selective electrical connections being indicated by the “dot” (•) in FIG. 2. Each one of the electrical connectors 32₄-32₁₅is adapted to receive a corresponding one of the directors 20₄-20₁₅, respectively, electrical connectors 32₂and 32₃are adapted to receive high address memory 18H and low address memory 18L of memory section 18₁, and electrical connectors 32₁₆and 32₁₇are adapted to receive high address memory 18H and low address memory 18L of memory section 18₂, as indicated. It is first noted that electrical connectors 32₀, 32₁, 32₁₈and 32₁₉are adapted to receive either a director or a memory. Here the electrical connectors 32₀, 32₁, 32₁₈and 32₁₉are described as having received directors 20₀, 20₁, 20₁₄, and 20₁₅, respectively.

[0040] It is noted that alternating ones of the directors, (i.e, directors 20₀, 20₂, 20₄, 20₆, 20₈, 20₁₀, 20₁₂, and 20₁₄), are electrically connected to one of the high address memory busses, here bus TH and to one of the low address memory busses, here bus BL, while the directors interleaved with such alternating ones of the directors (i.e., directors 20₁, 20₃, 20₅, 20₇, 20₉, 20₁₁, 20₁₃, and 20₁₅), are electrically connected to the other one of the high address memory busses, here bus BH and to the other one of the low address memory busses, here bus TL. It is noted that each one of the busses TH, TL, BH, BL extends along the length of the backplane printed circuit board 30.

[0041] Each one of the electrical connectors 32₀-32₁₉is identical in construction. An exemplary one thereof, here connector 30₀is shown in FIGS. 4A-4C mounted to the backplane printed circuit board 30. (It is noted that because directors 20₀-20₁₅are received in one side of the backplane 30 and input/output I/O adapter cards 22₀-22₁₅are received on the other side of the backplane 30, the “backplane” may be regarded as a “midplane” printed circuit board. That is, the “backplane” has printed circuit boards (i.e, an I/O adapter cards 22₀-22₁₅and director cards 20₀-20₁₅(or memory card 18H, 18L) plugged into opposite sides of it, as shown in FIG. 3).

[0042] Here, the exemplary electrical connector 32₀(FIGS. 4A-4C) is a model VHDM manufactured by Teradyne, Boston, Mass., and has a plurality of electrically conductive pins 36 therein which pass through the backplane 30 for electrical connection to the I/O adapter cards 22₀-22₁₅and a director cards 20₀-20₁₅(or memory card 18) plugged into opposite ends of the pins 36. It is also noted that the electrical connector 32₀is separated into four sections 38₁-38₄, (i.e., a top left section 38₁, a bottom left section 38₂, a bottom right section 38₃and a top right section 38₄, as indicated.) It is next noted that the upper portion of both top sections 38₁and 38₃provide an upper input/output pin section 40_Ufor the received directors 20₀-20₁₅and I/O adapter cards 22₀-22₁, and the lower portion of both bottom sections 38₂and 38₄provide a lower input/output pin section 40_Lfor the received directors 20 and I/O adapter cards 22. It is next noted that the lower portion of both top sections 38₁and 38₃provide two quadrants Q₁, Q₃of pins for the received directors 20 (or memory 18) and that the upper portion of both bottom sections 38₂and 38₄provide two quadrants Q₂, Q₄of pins for the received directors 20 (or memory 18). Next, it should be noted that an arbiter pin section 42_Tis provided between input/output section 40_Uand quadrant Q₁and an arbiter pin section 42_Bis provided between input/output section 40_Land quadrant Q₂for receiving the arbiters 24_AM-TM, 24_AM-BL, respectively, (FIGS. 1 and 2).

[0043] The backplane printed circuit board 30 is a multi-layer printed circuit board having a ground plane conductor 50, as shown in FIG. 4C. It is noted that the four busses TH, TL, BH, BL, are disposed on different electrically isolated layers of the backplane. It is further noted that the busses TH, and TL are disposed on the top (T) portion of the backplane 30; bus TH being electrically connected to the high (H) address memories 18H and bus TL being electrically connected to the low (L) address memories 18L. The busses BH, and BL are disposed on the bottom (B) portion of the backplane 30; bus BH being electrically connected to the high (H) address memories 18H and bus BL being electrically connected to the low (L) address memories 18L. It is noted that, referring to FIG. 2, for the electrical connectors 32₄, 32₆, 32₈, 32₁₀, 32₁₂, and 32₁₄, (i.e., here electrical connector which receive only directors) the pins in quadrant Q₁are connected to bus TH and the pins in quadrant Q₂are connected to bus BL. For the electrical connectors 32₅, 32₇, 32₉, 32₁₁, 32₁₃, and 32₁₅, (i.e. electrical connectors which receive only directors) the pins in quadrant Q₁are connected to bus TL and the pins in quadrant Q₂are connected to bus BH. For the electrical connectors 32₂and 32₃, 32₁₆, and 32₁₇(i.e. electrical connectors which receive only memories 18H or 18L) the pins in quadrant Q₁are connected to busses TH or TL, as indicated and the pins in quadrant Q₄are connected to busses BH or BL, as indicated. Thus, directors 20 are connected to pins in quadrants Q₁and Q₂while memories 18 are connected to quadrants Q₁and Q₄. It is noted that electrical connectors 32₀, 32₁, 32₁₈and 32₁₉are wired to the quadrants Q₁, Q₂and Q₄to provide universal slots adapted to receive either a memory 18 or a director 20,. Thus, here in FIG. 2, electrical connectors 32, and 32₁₈are connected to busses TH, BL and BH to receive either a director or a high address memory. Electrical connectors 32₁and 32₁₉are connected to busses TL, BH and BL to receive either a director or a low address memory.

[0044] Each one of the rear-end portion of the directors 20₀-20₃is identical in construction, an exemplary one therefor, here rear-end director 20₀being shown in FIG. 5 to include a pair of central processing sections, CPU X and CPU Y, a dual port random access memory (RAM), and shared resources (Flash memories, etc,) arranged as shown, coupled to the bank 14 of disk drives (FIG. 1) through I/O adapter card 22₀(FIG.1) via an I/O upper backplane section interface 52 (FIG. 5) and I/O lower backplane section interface 54, as indicated and to a high address memory bus, here TH, and low address memory bus, here BL, via a Q₁and Q₂backplane interface sections 56, 58 respectively. The rear-end director 20₀includes a pair of Vref receivers 60, 62 for receiving a Vref voltage generated on the memory busses TH and BL, in a manner to be described in detail in connection with FIGS. 10, 11, and 12. Suffice it to say here, however, that the Vref generated on the memory busses is transmitted on such memory busses to the receivers 60, 62 and that the receivers 60, 62 distribute such received reference voltage Vref locally to the interface sections 56 and 58. An exemplary one of the receivers 60, 62, here receiver 62, is shown in FIG. 5A to include a high input impedance operational amplifier 64 having the non-inverting input thereof fed by the Vref voltage on the memory buss. The output of the amplifier 64 is coupled to the inverting input thereof and provides the local reference voltage Vref for the interfaces 56 and 58. It is noted that the Vref generated on the high address memory bus, i.e., here, TH, is fed to Vref receiver 60 and that receiver 60 provides the reference voltage to the Q₁backplane section interface section 56. The Vref generated on the low address memory bus, i.e., here, BL, is fed to Vref receiver 62 and that receiver 62 provides the reference voltage to the Q₂backplane section interface section 58. Finally, it should be noted that the director has a primary output port, P, and a secondary output port, S. As will be described in detail in connection with FIG. 8, the primary port P is connected to both I/O backplane interface 52 and I/O backplane interface 54. Likewise, the secondary port S is connected to both I/O backplane interface 52 and I/O backplane interface 54.

[0045] Each one of the front-end portion of the directors 20₄-20₁₁is identical in construction. An exemplary one thereof, here director 20₄is shown in detail in FIG. 6 to include a pair of central processing sections, CPU X and CPU Y, a dual port random access memory (RAM), and shared resources (Flash memories, etc,) arranged as shown, coupled to the host computer (through an adapter, not shown), as indicated and to a high address memory bus, here TH, and low address memory bus, here BL, via a Q₁and Q₂backplane interface sections 56, 58, respectively. The front-end directors include a pair of the Vref receivers 60 for receiving generated Vref voltage transmitted to the receivers on the high and low address memory busses as described above in connection with FIG. 5. It is noted that here the interfaces 52, 54 are connected to the host computer as described above in connection with FIGS. 1 and 2.

[0046] An exemplary one of the memories is shown in FIG. 7 to include a plurality of here four DRAM sections coupled to the top and bottom busses though bus interfaces and ASIC control logics, as indicated.

[0047] As noted above in connection with FIGS. 1 and 2, a front-end portion of the directors 20₄-20₁₁is coupled to the host computer 12 and rear-end portion of the directors 20₀-20₃and 20₁₂-20₁₅is coupled to the disk drive bank 14. As described in connection with FIG. 5, each one of the rear-end directors 20₀-20₃and 20₁₂-20₁₅has upper and lower input/output interface 52, 54 coupled to bank 14 of disk drives. The bank 14 of disk drives has a plurality of sets 80₀-80₃and 80₁₂-80₁₅(FIG. 1) of electrically connected disk drives. Each one of the rear-end directors 20₀-20₃and 20₁₂-20₁₅has a pair of input/output terminals; i.e. a primary input/output terminals P and a secondary input/output terminals S. Each one of the sets 80₀-80₃and 80₁₂-80₁₅of disk drives is connected to the primary input/output terminals P and to the secondary input/output terminals S of an adjacent pair of the rear-end directors through an adapter card 22, as indicated in FIG. 1, and in FIGS. 6 and 7, for an exemplary pair of directors, here the pair of adjacent rear-end directors 20₀and 20₁. Thus, for redundancy, two different rear-end directors are able to communicate with any one set of disk drives, as shown in FIG. 8. Thus, for example, set 80₀is coupled to the primary terminal P of rear-end director 20₀and, for redundancy in case there is a failure in director 20₀, set 80₀is connected to the secondary terminal S of director 20₁. Further, directors 20₀and 20₁are on different sets of busses (i.e., busses TH and BL for director 20₀and busses TL and BH for director 20₁) for additional redundancy.

[0048] More particularly, the primary input/output terminals P of director 20₀are connected to: (1) the disk drive set 80₀through the backplane 30 and to the I/O adapter card 22₀; and (2) the secondary input/output S of the adjacent director 20₁through the backplane 30, as shown in FIG. 5. Reciprocally, the primary input/output terminals P of director 20₁are connected to: (1) the disk drive set 80₁through the backplane 30 and the I/O adapter card 22₁; and (2) the secondary input/output pins S of the adjacent director 20₀through the backplane 30.

[0049] With a SCSI interface, as shown in FIGS. 8 and 9, each one of the input/output interfaces 52, 54 includes a primary SCSI initiator section and a secondary, or redundant (i.e. “back-up”) SCSI initiator section. The primary SCSI initiator section includes four identical SCSI initiator chips: LDP, LCP, UDP, and UCP, as indicated, each adapted to initiate, or start, a transfer to a target, or destination, according to SCSI protocol. The secondary SCSI initiator section also includes four identical SCSI initiator chips: LDS, LCS, UDS, and UCS, as indicated, each adapted to initiate, or start, a transfer to a target, or destination, according to the SCSI protocol.

[0050] Here, a SCSI transfer uses a of SCSI initiator. Thus, the CPU Y of a director is coupled to the primary LDP and LCP chips of the director and the primary UDP and UCP chips of the director are coupled to the X CPU section of such director. For redundancy, the CPU X of a director is coupled to the secondary UDS and UCS chips of the director, and the secondary LDS and LCS chips of the director are coupled to the Y CPU section of such director. As noted in connection with FIG. 5, the X and Y CPU sections are coupled to busses TH and BL or to the busses BH and TL depending on the slot used by the director.

[0051] Thus, referring to FIG. 9, for an exemplary pair of adjacent electrical connectors 32₀, 32₁, as noted above, the UCP pins of electrical connector 32₀are connected the UCS pins of electrical connector 32₁through printed wires in the layers of the backplane printed circuit board 30. The UCS pins of electrical connector 32₀are connected the UCP pins of electrical connector 32₁through printed wires in the layers of the backplane printed circuit board 30. The LCP pins of electrical connector 32₀are connected the LCS pins of electrical connector 32₁through printed wires in the layers of the backplane printed circuit board 30. The LCS pins of electrical connector 32₀are connected the LCP pins of electrical connector 32₁through printed wires in the layers of the backplane printed circuit board 30. As noted particularly from FIG. 9, this arrangement is used for the rear-end directors connected to the bank 14 of disk drives and to the universal connectors 32₀, 32₁, 32₁₄and 32₁₅which, as noted above, are adapted to receive directors 20₁, 20₂, 20₁₄and 20₁₅, respectively. It is noted that these pins LDP, LCP, UDP, UCP, LDS, LCS, UDS, UCS, are interconnected between adjacent directors other that for those in the universal connectors for enabling a degree of freedom in configuration, i.e., the electrical connectors for directors 20₄, 20₅, enables such directors to be connected to the bank of disk drives instead of to the host computer.

[0052] The system 10 (FIG. 1) has a plurality of reference voltage (Vref) generators 28TH1, 28TH2; 28TL1, 28TL2; 28BH1, 28BH2; 28BL1, 28BL2, arranged as shown in FIGS. 10 and 12. These reference voltage generators are used to supply a reference voltage, Vref=1.0 volts, for Gunning Transistor A Logic Plus (GTLP) used in interfaces 56 and 58 (FIG. 5) used in the directors and GTLP circuitry in the memories 18H, 18L. Each bus couples the generated reference voltage to each one of the directors electrically connected to such bus, as shown in FIG. 10. Each one of the directors electrically connected to the bus includes, as described above in connection with FIGS. 5, 5A and 6, a reference voltage receiver response to the generated reference voltage for distributing the generated reference voltage among electrical components in such director. Thus, as noted above, the rear-end directors include a Vref receiver 60 for receiving generated Vref voltage transmitted to the receivers 60 on the high and low address memory busses, e.g., TH and BL, and for distributing such received voltages to the interface sections 56 and 58. As noted above, an exemplary one of the receivers 60 is shown in FIG. 5A to include a high input impedance operation amplifier 64 having the non-inverting input thereof fed by the Vref voltages on the memory busses. The output of the amplifier 64 is coupled to the inverting input thereof and provides the local reference voltage Vref for the interfaces 56 and 58.

[0053] It is noted that Vref receiver 60 is also in the front-end directors and the high address memories 18H and the low address memories 18L. Thus, rather that merely transmit Vref voltages on the busses and having resistor dividers in the directors and memories, receiver 60 is used with high input impedance operational amplifier 64 (FIG. 5A) to minimize the amount of current on the bus, and therefore the associated voltage drop along the bus, and to reduce the effect of change in the value of the resistors in the resistor divider network and its associated adverse effect on the accuracy of the Vref used by the GTLP circuits in the directors and memories.

[0054] Referring also to FIGS. 11 and 12, it is noted that the generators 28TH1, 28TH2; 28TL1, 28TL2; 28BH1, 28BH2; 28BL1, 28BL2 are connected to the terminating ends of the bus and are disposed on the adapter cards 20₀, 20₁, 20₁₄and 20₁₅in the electrical connectors 32₀, 32₁, 32₁₈and 32₁₉, respectively. It is also noted that both directors and memories include a Vref receiver 60. Each one of the reference voltage generators is identical in construction. An exemplary pair of the reference voltage generators (28TH1 and 28BL1) is shown in FIG. 11. A Vtt generator includes a pair of reference supply voltage sources 60, 62, here a +2.5 voltage supply, and four linear voltage regulators 64, 66, 68 and 69, one pair of the four linear voltage regulators 64, 68 being supplied by one of the two reference voltage sources 60 and the other pair of the four linear voltage regulators 66, 69 being supplied by the other one of the two reference voltage sources 62, as shown. The outputs of a pair of the linear regulators 64, 66 are connected together (through resistors, as shown) for redundancy to provide a Vtt generated voltage which is coupled to the Vref generator 28TH1, as shown. The outputs of other pair of the linear regulators 68, 69 are connected together (through resistors, as shown) for redundancy to provide a Vtt generated voltage which is coupled to the Vref generator 28TH2, as shown. An exemplary pair of the Vref generators 28TH1. 28BL1 are shown to include a pair of digital to analog converters (DACs) coupled via switches 70 to inputs of a high input impedance operational amplifier 72, as shown. The output of the amplifiers 72 is coupled to the input thereof in a negative feedback relationship and produces the generated Vref for the top high address memory bus, TH, as shown in FIG. 11.

[0055] The DACs enable one to vary the level of the reference voltage to, for example, determine the margin allowable by the system and/or to choose an optimum Vref level for the system. This is enabled by placing a digital word to the DAC and coupling the corresponding analog voltage level through an activated switch to the non-inverting input of the operational amplifier.

[0056] It is noted that diodes 81 are isolation diodes. Thus, the one of the Vref generators 28TH1, 28TH2 which produces the higher voltage supplies the bus with such voltage. It both Vref generators 28TH1, 28TH2 produce the same voltage, they current share. Further, the diodes 81 provide isolation if one of the Vref generators 28TH1, 28TH2 fails.

[0057] Alternatively, the reference voltage generators may include 2.5 volt fixed reference voltage sources arranged as shown in FIG. 11A to provide the Vtt generator.

[0058] Referring again to FIG. 1, as noted above, a plurality of pairs of master and slave bus arbiters 24_AMTH, 24_ASTH; 24_AMTL, 24_ASTL, 24_AMBH, 24_ASBH; 24_AM, 24_ASis provided. Referring also to FIG. 13, requests for one of the busses TH, TL, BH, BL are made by the eight directors connected to such one of the busses. Thus, for exemplary bus BL, requests for bus BL may be made by the eight directors 20₀, 20₂, 20₄, 20₆, 20₈, 20₁₀, 20₁₂and 20₁₄connected to such bus BL. A pair of arbiters 24_ASBLand 24_AMBLis connected to the ends of bus BL. One of each of the pairs of bus arbiters is a master arbiter, here arbiter 24_AMBLand the other one of the pair of arbiters is a slave arbiter, here 24_ASBL. The master arbiter 24_AMBLprovides arbitration between directors connected to the bus BL and, if one of the directors connected to such bus BL indicates a fault, the master arbiter 24_AMBLis disabled and the slave arbiter 24_ASBLis enable to provide such arbitration. More particularly, the I/O adapter cards 22₀, 22₁₄connected to the terminating ends of the bus BL received in end ones of the electrical connectors 32₀, 32₁₉, respectively, have thereon the slave arbiter 24_ASBLand master arbiter 24_AMBL, respectively, electrically connected to bus BL. (Referring to FIG. 2, it is noted that I/O adapter card 22₀has slave arbiters 24_ASTHand 24_ASBL; I/O adapter card 22₁has slave arbiters 24_ASBHand 24_ASTL; I/O adapter card 22₁₄has master arbiters 24_AMTHand 24_AMBL; and, I/O adapter card 22₁₅has master arbiters 24_AMBHand 24_AMTL) . Each one of the arbiters 24_AMBLor 24_ASBLis identical in construction and is adapted to respond to the priority codes of the directors coupled thereto and assign access to such bus in accordance with a predetermined criteria, to be described.

[0059] Referring to FIG. 15, it is noted that electrical pins P1 have the same physical location in each one of the electrical connectors 32₀, 32₁, 32₁₈and 32₁₉. Further, it is noted that the pins P₁in electrical connectors 32₀and 32₁are connected to ground via the ground plane of the backplane printed circuit board while the pins P₁in the electrical connector 32₁₄and 32₁₅are not connected; i.e., are open circuit, that is, are terminated in a high impedance. Thus, one of the electrical connectors 32₀, 32₁₈at one end of the bus BL, here connector 32₁₈has a reference electrical potential on pin P₁thereof, here ground, and the one of the electrical connectors 32₀at the other end of the bus has a high impedance on pin P₁thereof, here an open circuit (i.e, no connection, NC). The, mating pins P₁in the I/O adapter card received in electrical connectors 32₀, 32₁are therefore connected to the grounded pins, while the mating pins P₁in the I/O adapter card received in electrical connectors 32₁₈, 32₁₉are therefore connected to an open circuit. Plugging an adapter card in electrical connectors 32₀and 32₁configures the arbiter thereon into a slave arbiter while plugging the same adapter card into electrical connector 32₁₈, 22₁₉configures the same arbiter as a slave arbiter.

[0060] More particularly, referring also to FIG. 14, it is noted that, and considering the exemplary master and slave arbiters connected to the ends of bus BL, the master arbiter 24_AMBLhas identical circuitry as the slave arbiter 24_ASBL. Thus, each includes identical master/slave arbiter enable circuits 90 and identical master and slave arbiter control circuitry 25_AMBL, 25_ASBL, respectively. The master/slave arbiter enable circuits 90 each include an exclusive OR gate 92 having a pair of inputs 94, 96. One of the pair of inputs, here input 94, is connected to a supply voltage, Vcc, through a resistor R₁and to the directors connected to the bus BL via a one bit line MS_ARB, while the other input 96 is connected to pin P₁and to Vcc through resistor R₂to the directors connected to the bus BL. As noted above, when pin P₁is connected to ground, as when the adapter card is plugged into electrical connector 32₀, the arbiter will be configured as a slave arbiter 24_ASBLwhile when the same adapter card is plugged into electrical connector 32₁₈, the arbiter will be configured as a master arbiter 24_AMBL. The resulting configuration for an exemplary one of the busses, here bus BL, is shown in FIG. 14.

[0061] At power-up, a high logic signal is produced on the one bit MS_ARB line (FIG. 14). The high logic level signal on the one bit MS_ARB line is fed to inputs 94 of both master/slave arbiter enable circuits 90. In response to the high logic level, the exclusive OR gate 92 of master arbiter 24_AMBLproduces a low enable signal to thereby enable the master arbiter control 25_AMBLand exclusive OR gate 92 of slave arbiter 24_ASBLproduces a high enable signal to thereby disable slave arbiter 25_ASBL. If a director issues a two bit priority code and no response is received by the arbiter after a predetermined time, the same director which issued the priority code for the bus produces a low logic signal to inputs 94 of both master/slave arbiter enable circuits 90. More particularly, if a director requests the bus, and a bus grant is not received within a predetermined time, for example, 150 milliseconds, the director detects an arbitration timeout error, assumes that the master arbiter has failed, and produces a low logic level on the one bit MS_ARB line (FIG. 14). In response to the low logic level, the exclusive OR gate 92 in the slave arbiter 24_ASBLproduces a low enable signal to thereby enable the slave arbiter control 25_ASBLand the exclusive OR gate 92 in the master arbiter 24_AMBLproduces a high enable signal to thereby disable the master arbiter control 25_AMBL.

[0062] As noted above, each one of the directors is adapted to produce on the bus BL coupled thereto a plural, here two-bit priority code REQCD. The bus arbiter 24_AMBL, for example, is responsive to the priority codes of the directors coupled thereto and assigns access to such bus in accordance with a predetermined criteria. Here, the two-bit priority code REQCD provides one of three levels of priority: a low priority and two types of high priority; i.e., a DMA high priority and a DSA high priority. (A DMA high priority is used for a read/write multiple data word transfer while a DSA high priority is used for a read/write single data word transfer). The arbiter assigns the lowest priority to the directors issuing the low priority code and toggles alternatively between directors issuing either one of the two high priority requests in a manner to be described. In any event, a low priority request is granted by the arbiter to a director which has been issuing such request for a predetermined number of director requests.

[0063] Referring now to FIG. 16, an exemplary one of the arbiter controls 25_AMBL, 25_ASBL, here arbiter control 25_AMBL, is shown in detail. (As noted above, each of the arbiter controls 25_AMBL, 25_AMBLis identical in construction.) The arbiter control 25_AMBLis shown to include a request synchronizer and decoder section 100, shown in more detail in FIG. 17, a director granter 102 for each of the three types of priorities, shown in more detail in FIG. 18, and a low priority/high priority toggle selector 104, shown in more detail in FIG. 19.

[0064] Referring to FIG. 17, the request synchronizer and decoder section 100 is used to first synchronize the asynchronous two-bit priority requests (REQCDs) from the eight directors 20₀, 20₂, 20₄, 20₆, 20₈, 20₁₀, 20₁₂, to a clock, CLK. The request synchronizer and decoder section 100 includes a plurality of here eight synchronization latching sections 106₁-106₈, each one thereof being fed by the two-bit priority code of a corresponding one of the eight directors 20₀, 20₂, 20₄, 20₆, 20₈, 20₁₀, 20₁₂coupled to the arbiter control 25_AMBL. Here, the two-bit priority codes REQCDs (i.e., one bit being REQCD_0 and the other bit being REQCD_1) are represented by binary logic signals as follows:

[0065] Each one of eight synchronization latching sections 106₁-106₈is identical in construction. An exemplary one thereof, here section 106₁, is shown to include an NAND gate 110 fed by the two-bit priority code of the one of the eight directors, here director 20₀fed thereto. Also provided are three flip/flop (F/F) sections 112, 114, 116 arranged as shown having their clock terminals fed by the CLK. Thus, after a clock pulse CLK, the two-bit priority code of the director issuing such code since the last clock CLK are stored in the flip/flop 116. The flip/flop 114 produces a logic signal on line REQ DIR0 to indicate that a valid code has been detected.

[0066] The outputs of the here eight synchronization latching sections 106₀-106₇are fed to a corresponding one of here eight decoders 120₀-120₇to decode the two-bit word fed thereto to one of the three priority levels; i.e., low priority, high priority_DMA; or high priority_DSA in response to the logic signal on line REQ DIR0 indicating that a valid code has been detected. Here, a request is represented by a logic 1 and the absence of a request is represented by a logic 0. Each one of the eight decoders 120₀-120₇produces the decoded priority request for a corresponding one of the eight directors 20₀-20₇, as indicated. Thus, for example, decoder 120₀produces decoded priority requests LP_0, DMA_0, and DSA_0 for director 20₀and decoder 120₇produces decoded priority requests LP_7, DMA_7, and DSA_7 for director 20₇. The three priority requests are grouped as indicated for each of the eight directors 20₀, 20₂, 20₄, 20₆, 20₈, 20₁₀, 20₁₂, 20₁₄into a low priority set of eight LP_REQS request (i.e., LP_0 through LP_7, respectively, provided by decoders 120₀-120₇); a set of eight first high priority set of HP_DMA_REQS requests (i.e., DMA_0 through DMA_7, respectively, provided by decoders 120₀-120₇); and a set of eight second high priority set of HP_DSA_REQS requests (i.e., DSA_0 through DSA_7, respectively, provided by decoders 120₀-120₇), as shown. Here, as noted above, a request is a logic 1 and the absence of a request is a logic 0. Thus, if the director 20₀issues a DSA request when there is a CLK, line DSA_0 is a logic 1; whereas if the director 20₀does not issues a DSA request when there is a CLK, line DSA_0 is a logic 0. In like manner, if the director 20₁₄issues a DSA request when there is a CLK, line DSA_7 is a logic 1; whereas if the director 20₁₄does not issues a DSA request when there is a CLK, line DSA_7 is a logic 0.

[0067] The three sets of priority requests (i.e., a set of eight LP_REQS request, a set of eight HP_DMA_REQS requests; and a set of eight HP_DSA_REQS requests) are fed by the request synchronizer and decoder 100 to the director granter 102 (FIG. 18) for each of the three types of priorities. The director granter 102, for each of the three types of priorities, includes three sections 122₁, 122₂and 122₃, each of identical construction and fed by a corresponding one of the three sets of requests (i.e., the set of eight low priority requests, LP_REQS requests, the set of eight first type high priority requests, HP_DMA_REQS requests; and the set of eight second type high priority requests, HP_DSA_REQS requests). An exemplary one of the identical sections 122₁, 122₂and 122₃, here the section 122₁coupled to the set of eight LP-REQS, is shown to include an 8:1 multiplexer 124 fed by each of the eight low priority request lines LP_0 through LP_7, a three bit counter 126 incremented by the clock CLK and enabled by the output of an NAND gate 128. The NAND gate 128 is fed by the output of the multiplexer 124. An inverted input of NAND gate 128 is fed by a low priority feedback signal, LP_FB, which indicates an active request has been granted in a manner to be described in more detail hereinafter thus releasing the polling operation of the multiplexer 124 in searching for the next active low priority request without loss of processing time. Suffice it to say here, however, that the counter 126 is enabled, (i.e., when there is a low priory request from a director and the request is not being processed), the counter 126, which is initially reset to 0, increments in response to each CLK. Thus, each time the contents of the three bit counter 116 increments, a different one of the low priority requests from the eight directors 20₀, 20₂, 20₄, 20₆, 20₈, 20₁₀, 20₁₂, 20₁₄polled (i.e., is coupled to the output of the multiplexer 124) to provide an indication of whether the polled director produces a low priority signal on a line in the set LP_REQ. The count of the counter 126, (i.e., a three bit code on bus LP_REQCD, low priority director request code) thus indicates which one of the directors is producing the low priority request. It is noted that the low priority signal on line LP_REQ is produced when one of the eight directors 20₀, 20₂, 20₄, 20₆, 20₈, 20₁₀, 20₁₂, 20₁₄is selected by the contents of the counter 126 only if such selected director produces a low priority request. Thus, when enable to increment eight times, the director granter 102, for each of the three types of priorities, has indicated the type of priority request for each of the eight directors 20₀, 20₂, 20₄, 20₆, 20₈, 20₁₀, 20₁₂, 20₁₄. That is, after eight CLKs all requests from each of the eight directors have been polled.

[0068] The low priority/high priority toggle selector 104 is shown in more detail in FIG. 19 to include AND gates 130 through 140, a two-bit counter 142, OR gates 144 through 152, a logic section 154 (shown in detail in FIG. 20), and gates 156 through 160, all arranged as shown. The logic section 154, shown in detail in FIG. 20, is fed by logic signals on lines DMA_FB, DSA_FB, and DSA/{overscore (DMA)} (i.e., Previous Grant), to be described, and is arranged to implement the following priority arbitration Rules with regard to the two types of high priorities, i.e., DMA and DSA:

[0069] Thus, the logic network 154 implements the following logic truth Table:

[0070] In operation, if there is a low priority request and there had been three high priority type requests, as counted by two-bit counter 142, AND gate 130 produces a logic 1 on line LP_FB which passes through OR gates 144, 150 to indicate on resume strobe line RES_STRB (FIGS. 14 and 19) to all the directors to indicate that a director has been given access to the bus, BL. It is noted that the output of AND gate 130 is fed to an inverting input of AND gates 132-140 thereby causing AND gates 132-140 to produce a logic 0 when AND gate 130 produces a logic 1. Further, if there is neither a DMA or DSA request, as indicated by a logic 1 and a low priority request, a the output of AND gate 132 produces a logic 1 which passes through OR gates 144, 150 to indicate on resume strobe line RES_STRB (FIGS. 14 and 19) to all directors that a director has been given access to the bus, BL.

[0071] If there is a DMA request and no DSA request, AND gate 134 produces a logic 1 on line DMA_FB which passes through OR gates 146, 150 to indicate on the resume strobe line RES_STRB to the directors that a director has been given access to the bus. If there is a DSA request and no DMA request, AND gate 140 produces a logic 1 on line DSA_FB which passes through OR gates 148, 150 to indicate on the resume strobe line RES_STRB to the directors that a director has been given access to the bus. If there is a DMA request and a DSA request either AND gate 134 or AND gate 136 produces a logic 1 depending on the previous DSA or DMA request (i.e., as established by Tables II and III above).

[0072] Further, a logic 1 signal on one of the lines LP_FB, DMA_FB or DSA_FB enables gates 156, 158, 160, respectively, which are fed the three-bit signals LP_REQCD, DMA_REQCD and DSA_REQCD, to pass the three-bit director designation code on bus RES_CD. Thus, the signal on bus RES_CD provides an indication of the one of the eight directors coupled to bus BL which is being granted access to the bus BL and bus RES_CD provides such indication to such eight directors 20₀, 20₂, 20₄, 20₆, 20₈, 20₁₀, 20₁₂, 20₁₄.

[0073] It is noted that a director granted access to the bus after the arbitration, maintains the access to the bus as long as its request code REQCD is asserted on the bus. When the request code is removed from the bus by the director, the arbiter control 25_AMBL, for example, produces a logic 0 on the resume strobe bus RES_STRB (which indicates that one of the directors has access to the bus) and the arbitration process is allowed to repeat in the manner described above. Further, as noted above, the NAND gate 128 is fed by the output of the multiplexer 124. An inverted input of NAND gate 128 is fed by a low priority feedback signal, LP_FB, which indicates an active request has been granted thus releasing the polling operation of the multiplexer 124 in searching for the next active low priority request without loss of processing time.

[0074] Other embodiments are within the spirit and scope of the appended claims. For example, backplanes may be used with a different larger or smaller number of electrical connectors than shown in FIG. 1. Further, the universal slots may located in other positions than those shown in FIG. 1.