US 6,288,561 B1Grant
Method and apparatus for probing, testing, burn-in, repairing and programming of integrated circuits in a closed environment using a single apparatus
Issue Date:2001-09-11
•86 Claims
•5 Drawing Sheets
Abstract
A single gas tight system which performs multi-functions including reducing the thickness of oxides on contact pads and probing, testing, burn-in, repairing, programming and binning of integrated circuits. A system according to one embodiment of the present invention includes: (a) a gas tight chamber having (1) a plurality of modules each having a holding fixture, a wafer, a probing device, an electronic circuit board, and a temperature control device, (2) a gas source for supplying non-oxidizing gases such as nitrogen and hydrogen into the chamber, (3) a handler for moving the wafers and the probing devices, and (b) a computer coupled to the chamber for controlling and communicating with the handler, the temperature control devices, the holding fixtures and the probing devices. A holding fixture holds a wafer having integrated circuits and aligns the wafer to a probing device. An integrated circuit has a plurality of conductive contact portions that are able to be connected to probe points of the probing device. A temperature control device is used to heat the wafer during an oxide reduction process or during burn-in of the wafer. During the oxide reduction process, hydrogen is introduced into the chamber, and the wafer is heated so that the oxides on the contact pads can combine with hydrogen to form water vapor, thus reducing the thickness of the oxides. The computer analyzes the test and/or burn-in data and provides control signals for repairing or programming the integrated circuits. The computer system also generates a database that contains the performance data of all the integrated circuits on the wafer that are tested and allows for immediate feedback of the quality of the integrated circuits.
Metadata
Assignee
- Elm Technology Corporation
Inventor
- Glenn Leedy
Application Information
Application Number:US 08/474,489
Filing Date:1995-06-07
Priority Date:1988-05-16
Art Unit:7
Classifications
IPC:
G01R 3102
Field of Search:
324760324757324754324755324758324765
Patent Drawings (5 sheets)
Description
[0002] This is a continuation-in-part of application Ser. No. 08/055,439 filed Apr. 30, 1993, now U.S. Pat. No. 5,451,489, which is a division of application Ser. No. 07/775,324 filed Oct. 11, 1991, now U.S. Pat. No. 5,225,771, which is a division of application Ser. No. 07/482,135 filed Feb. 16, 1990, now U.S. Pat. No. 5,103,557, which is a continuation-in-part of application Ser. No. 07/194,596 filed May 16, 1988, now U.S. Pat. No. 4,924,589; and is also a continuation-in-part of application Ser. No. 08/315,905 filed Sept. 30, 1994, now U.S. Pat. No. 5,869,354 which is a division of application Ser. No. 07/865,412 filed Apr. 8, 1992, now U.S. Pat. No. 5,354,695 and is also a continuation-in-part of application Ser. No. 08/217,410, filed Mar. 24, 1994, now U.S. Pat. No. 5,453,404, which is a continuation of application Ser. No. 07/960,588, filed Oct. 13, 1992, now U.S. Pat. No. 5,323,035.
Background of the Invention
[0003] 1. Field of the Invention:
[0004] The present invention relates to test equipment and more particularly to equipment for probing, testing, burn-in, repairing, programming and binning of integrated circuits.
[0005] 2. Description of the Related Art:
[0006] In conventional semiconductor equipment technologies, separate pieces of equipment are required to test, burn-in, repair, program and bin integrated circuits (ICs). Integrated circuits that are in wafer form are tested or screened for packaging using a tungsten needle probe card, wafer positioning equipment called a prober and automatic test equipment (ATE) which supplies test signals to the probe card and determines the validity of any output signals. A probe card is a connector that provides a mechanical means for making a temporary contact to the contact pads on an IC for the purpose of testing the IC. The probe card may contact only a single die, but it may typically contact as many as eight or more dice if the dice consist of memory ICs. A die typically consists of one IC; however, it may include a plurality of ICs. Conventional probe cards do not provide the capability of contacting all the dice on a wafer at once.
[0007] An IC is typically burned-in and speed-graded prior to its use or sale. Burn-in of circuit devices requires many hours of testing the devices under stressing temperature and electrical conditions. An IC is burned-in to lower the possibility that it will fail after it is inserted into an electronic assembly such as a Multi-Chip Module (MCM) or printed circuit board (PCB) of other ICs. Burn-in of an IC is performed typically after the IC is in packaged form. Burn-in fixtures for processing a die before packaging, so called bare die burn-in, are beginning to become available. Whether an IC is in packaged form or in die form, a separate piece of equipment is used to burn-in an IC. After an IC has been burned-in, it is speed-graded or binned using automatic test equipment. Binning is a process that sorts ICs according to their performance characteristics.
[0008] When an IC is in wafer form, and it contains shorts that disrupt the functionality of the IC, it may be repaired by removing portions of a deposited layer (e.g., a polysilicon layer or an aluminum metal layer). A laser cutting machine is typically used to perform the circuit repair. If an IC is a memory circuit array, yet another machine is required to program the memory circuit array by fusing or anti-fusing circuits within the memory circuit array. Subsequent to repair of an IC, the IC must be tested again.
[0009] It would be advantageous, and is therefore an object of the present invention to provide a single piece of equipment that can perform all of the functions mentioned above that are previously done by separate pieces of equipment to reduce capital equipment expense and the number of steps required for IC burn-in, testing, repairing and/or programming.
Summary of the Invention
[0010] The present invention provides a single gas tight system that can perform multi-functions including reducing the thickness of oxides on contact pads and probing, testing, burn-in, repairing, programming, marking and binning of integrated circuits. A system according to one embodiment of the present invention includes: (a) a gas tight chamber having (1) one or a plurality of modules each having a holding fixture, a wafer, a probing device, other processing device such as a die inking or repairing device, an electronic circuit board, and a thermal control device, (2) a gas source for supplying non-oxidizing gases such as nitrogen and hydrogen into the chamber, (3) a handler for moving the wafers and the probing or other processing devices, and (b) a computer coupled to the chamber for controlling and communicating with the handler, the temperature control devices, the holding fixtures, the probing and other processing devices.
[0011] A holding fixture holds a wafer having integrated circuits and aligns the wafer to a probing device or other processing device. An integrated circuit has a plurality of conductive contact portions, typically referred to as contact, I/O or bond pads, that are couplable to probe points of the probing device. A temperature control device is used to heat the wafer during an oxide reduction process. When hydrogen is present in the chamber and the wafer is heated, the oxides on the wafer combine with hydrogen to form water vapor, thus reducing the thickness of the oxides. The temperature control device may also be used to heat or cool the wafer during burn-in of the wafer.
[0012] A probing device can have multiple probe points or a single probe point. the probing device can be a full-wafer probing device having active switching logic circuits to allow controlled access to each of the integrated circuits on a after, and optionally, generate some or all of the test signals required for testing the die.
[0013] The computer can generate a computer database with the various status information for every circuit processed by wafer and on-wafer site location. The database can provide timely performance distribution statistics and physical distribution statistics to the circuit manufacturing engineers or process engineers to allow adjustments to be made to the manufacturing process. By using the database, processing steps that are slowly going out of specification and affecting product quality can be corrected. Thus, the capability of near-real time adjustments to the manufacturing process will allow savings by reducing the number of products that do not satisfy specifications.
[0014] The present invention allows a single semiconductor test and circuit configuration machine to perform any or all of the following: (a) reducing the thickness of oxides on contact pads of integrated circuits on a wafer by supplying a first non-oxidizing gas such as nitrogen into the chamber, heating the contact pads, and supplying a second non-oxidizing gas such as hydrogen into the chamber so that the oxides can combine with hydrogen to form water vapor, (b) probing the contact pads using a probing device, (c) testing the functionality of the integrated circuits, (d) burning-in the integrated circuits for a predetermined period of time over a predetermined range of temperature with predetermined temperature rate of change and electrical conditions, (e) generating test vector data and analyzing data collected from the integrated circuits, (f) repairing the integrated circuits, (g) programming the integrated circuits by fusing or antifusing specific circuits within the integrated circuits, (h) marking or printing on the wafer, (i) binning the integrated circuits according to their performance characteristics, and (j) collection of a database for immediate feedback to the manufacturing process.
Brief Description of the Drawings
[0015] The objects, features and advantage of the present invention will be apparent from the following detailed description in which:
[0016] FIG. 1 is a multi-functional semiconductor test and circuit configuration system according to the present invention.
[0017] FIG. 2 is one of the modules shown in FIG. 1.
[0018] FIG. 3 is a wafer having a plurality of integrated circuits.
[0019] FIG. 4 is a flow chart illustrating the steps of reducing the thickness of oxide films on the contact pads of the integrated circuits and the steps of testing, burning-in, configuring and binning the integrated circuits according to the present invention.
[0020] FIG. 5 is a detailed block diagram of the computer shown in FIG. 1 according to one embodiment of the present invention.
Detailed Description of the Invention
[0021] The present invention provides methods and apparatus for performing testing, burn-in, repairing, programming, and binning of integrated circuits in a closed environment using a single piece of equipment. In the following detailed description, numerous specific details are set forth such as particular hardware configurations and a flow chart to provide a thorough understanding of the present invention. It will be appreciated, however, by one having ordinary skill in the art that the present invention may be practiced without such specific details. In other instances, well-known structures and methods are not described to avoid obscuring the present invention unnecessarily.
[0022] Now referring to FIG. 1, a semiconductor test and circuit configuration system 5, which is a cluster tool, is presented according to one embodiment of the present invention. System 5 includes a chamber 10 and a computer 30. Chamber 10 includes a plurality of modules 14a-14efor processing wafers, a handler 12 for moving wafers and probing devices, and a wafer cassette 22 for holding a plurality of wafers.
[0023] It will be appreciated that the present invention may be used to process other substrates even though the specific details set forth the processing of a semiconductor wafer. Other substrates, circuit substrate types, or substrate assemblies that the present invention can process are Multi-Chip Module and flat panel display substrates which may be made from various materials such as AlN, SiC, quartz, glass or diamond.
[0024] Chamber 10 shown in FIG. 1 includes a plurality of modules. Although five modules are shown in FIG. 1, chamber 10 may include more modules or fewer modules. Since a wafer cassette usually holds twenty-five wafers, a chamber can be made to include twenty-five modules for processing twenty-five wafers simultaneously. It should be noted that each of the modules may perform the same function (or functions). For instance, all of the modules may perform functional testing, burn-in and repairing of ICs in the same sequence and at the same time. On the other hand, the modules may perform different functions. For example, while module 14aperforms a functional test, module 14bmay perform programming of ICs. Moreover, the modules can also perform each function independently and in any order, such as performing a test function without burn-in processing or performing a test function both before and after other processing steps.
[0025] Chamber 10 may be a closed system or an open system. When chamber 10 is a closed system, chamber 10 is a gas tight system, not allowing gas molecules to move across the chamber boundary 24. The pressure inside chamber 10 may be more than, at, or less than atmospheric pressure. In one embodiment, chamber 10 includes a gas source 20 wherein gas source 20 can introduce non-oxidizing gases such as nitrogen and hydrogen into chamber 10. As will be described later, having a non-oxidizing environment is beneficial in forming good contacts between probing devices and the contact pads of integrated circuits.
[0026] It will be appreciated that in another embodiment, each module in chamber 10 can be in a separate gas-tight closed environment. In such a case, each module would have doors to close off and isolate the atmosphere and temperature of the module and each module could contain a separate gas source. For example, one module can contain nitrogen and hydrogen to reduce the thickness of metal oxide films, while another module may contain only nitrogen to perform another function such as a functionality test on an IC.
[0027] Handler 12 in FIG. 1 can be a robotic system that moves wafers between wafer cassette 22 and the holding fixtures or between the holding fixtures and changes the probing devices when the type of wafer is changed. Handler 12 has the capability to move multiple wafers simultaneously. It should be noted that a module can be manually loaded with a wafer instead of using the handler 12.
[0028] FIG. 2 presents a module 14a1. Module 14a1is identical to module 14aof FIG. 1 except that module 14a1contains a gas source 50. Since modules 14a-14eare identical, no separate description is provided for modules 14a-14e. Module 14a1in FIG. 2 includes a probing device 42 having probe points 44 for probing contact pads on wafer 40 and circuitry 50 which is coupled to an electronic circuit board 18a. A holding fixture 16ahas a plurality of vacuum holes for pulling down wafer 40 onto holding fixture 16aand a thermal control device 48 for controlling the temperature of the substrate 40. Module 14a1also includes a gas source 50 for introducing non-oxidizing gases into module 14a1.
[0029] Wafer 40 includes a plurality of integrated circuits (ICs) 64a-64las shown in FIG. 3. Each IC includes a plurality of conductive contact portions such as contact pads 66 (not all are shown in FIG. 3). Conductive contact portions are not limited to contact pads, and they may include various types of metal portions that are exposed on a wafer. Conductive contact portions are usually made of aluminum. However, they may be made from various other types of metal. ICs on wafer 40 may be of different sizes, and the contact pads may be also of different sizes. Wafer 40 in FIG. 2 may represent a full wafer as shown in FIG. 3 or a partial wafer. In the preferred embodiment, wafer 40 is a whole wafer. Wafer 40 may be a silicon wafer, GaAs wafer, or any other semiconductor wafer. It should be noted that wafer 40 may include only simple circuits wherein the circuits may be passive circuits, active circuits or metal lines.
[0030] Continuing to refer to FIG. 2, probing device 42 may contain a single probe point, a small number of probe points (5-40) or a large number of probe points (approximately 100,000 to 500,000 or more). In the preferred embodiment, probing device 42 is a full-wafer probing device. U.S. Pat. Nos. 5,103,557 and 5,323,035 issued to this inventor disclose how a full-wafer probing device can be fabricated. A full-wafer probing device has the capability to contact all of the contact pads on a wafer at once. The number of probe contact points that may be required in such wafer probing device can exceed 100,000 points. As shown in U.S. Pat. No. 5,103,557, a full-wafer probing device can also include a circuitry that allows each die of a wafer to be individually tested and/or isolated if it is faulty. This is shown as circuitry 50 in FIG. 2. Also, U.S. Pat. No. 5,354,695 discloses a fabrication process for making an intelligent probing device through the use of membrane circuits. IC circuitry 50 also provides the means to reduce the number of electronic signal connections to and from the probing device to a number that is approximately the same as the number of signals associated with each die and not the number of connections equal the number of dice on a wafer times the signals per die. When IC circuitry 50 incorporates active circuit switching logic, it provides a controlled access to each die on a wafer.
[0031] IC circuitry 50 of probing device 42 is connected to electronic circuit board 18awhich is coupled to computer 30 in FIG. 1. Electronic circuit board 18ais used as a common mechanical and an electrical interface between probing device 42 and computer 30 so that probing device 42 can receive control signals from computer 30 and send data signals to computer 30. In another embodiment, chamber 10 of FIG. 1 can contain one electronic circuit board for all the probing devices instead of having one electronic circuit board for each probing device as shown in FIG. 2.
[0032] Probing device 42 has probe points 44 and IC circuitry 50 that are specific for a wafer being tested. A probing device can be changed with another by handler 12 in FIG. 1 when the type of wafer is changed. Although probing device 42 can incorporate active device switching circuitry such as transistors on the electronic circuit boards, probing device 42 could also only incorporate passive circuit elements such as resistors, inductors, and capacitors. In the latter embodiment, there would be a reduction in the complexity of fabrication of probing devices but an increase in the number of I/O interconnections from probing devices to the supporting control circuitry. With the former embodiment of the probing devices, higher at-speed tests can be performed as there is no concern for degradation of signal integrity due to the constraints of path propagation and signal bandwidth. The incorporation of active device switching circuitry into probing devices would create intelligent and programmable probing devices.
[0033] Still continuing to refer to FIG. 2, holding fixture 16ais used to hold wafer 40 and align wafer 40 to probing device 42. Holding fixture 16aincludes a vacuum source 46 having a plurality of vacuum holes to hold wafer 40 firmly against holding fixture 16aand temperature control device 48 for heating or cooling wafer 40. Holding fixture 16ais controlled by computer 30 in FIG. 1. When wafer 40 is placed on holding fixture 16a, computer 30 sends control signals to vacuum source 46 to apply vacuum to pull down wafer 40 against holding fixture 16a, and at the completion of testing, repairing or programming of the ICs on wafer 40, vacuum source 46 may be turned off so that wafer 40 can be released from holding fixture 16a.
[0034] Temperature control device 48 is also controlled by computer 30. To burning wafer 40 or to remove oxide from the contact pads of wafer 40, computer 30 sends control signals to temperature control device 48 to control the temperature of the wafer 40. Computer 30 controls and monitors the temperature of wafer 40 so that it is changed to predetermined temperatures for a predetermined period of time. The rate at which the temperature of wafer 40 is changed can also be controlled by computer 30 through the use of temperature control device 48. In FIG. 2, temperature control device 48 is embedded in holding fixture 16ato control the temperature of wafer 40. However, wafer 40 can be heated by radiation or by some type of ion beams. Focused ion beams can be used to heat only a portion of wafer 40 or only a specific contact pad on wafer 40. Temperature control device 48 can also be used to reduce the temperature of wafer 40 for cases where the operation of all the circuits on a substrate may have a combined thermal energy generation exceeding the desired burn-in temperature or for situations where simulation of a low temperature environment is desired. For temperatures lower than 25° C., where moisture condensation can result on substrates, the use of a gas tight system as described above would be preferred such that most of the water content is removed. The common methods and apparatus used to control the temperature of a substrate is well-known in the art and thus is not discussed further.
[0035] Computer 30 also controls the movement of holding fixture 16aso that it can be aligned to probing device 42. The detailed description of alignment of wafer 40 to probing device 42 is disclosed in U.S. Pat. Nos. 5,103,557 and 5,354,695, describing optical and electronic sensors, respectively. It should be noted that instead of moving holding fixture 16a, probing device 42 can be moved to align probing device 42 to wafer 40. Although, in the preferred embodiment, computer 30 controls turning on and off vacuum source 46, the movement of holding fixture 16aand the temperature of temperature control device 48, such functions can be performed manually.
[0036] During functional circuit testing, computer 30 sends control signals to probe points 44 of probing device 42 through electronic circuit board 18aand IC circuitry 50. ICs on wafer 40 generate data signals in response to the control signals, and the data signals are sent back to computer 30 so that computer 30 can analyze the data signals and determine the functionality of each IC on wafer 40.
[0037] During burn-in, computer 30 sends control signals to heat or cool wafer 40 to specific temperatures for a predetermined period of time and electrical signals to probe points 44 of probing device 42 so that the ICs on wafer 40 can be tested while they are stressed under certain temperature and electrical conditions. The ICs on wafer 40 generate data signals which are sent to computer 30 to analyze and determine which ICs pass the burn-in test.
[0038] After a functional test or a burn-in test, computer 30 analyzes the data obtained from the ICs on wafer 40 and provides new control signals to probe points 44 either to repair the ICs on wafer 40 and/or to program the ICs by fusing or anti-fusing circuits within the ICs as is done with memory circuits. For example, to repair a circuit, computer 30 can provide control signals to probing device 42 so that high voltage or current can be provided between the appropriate probe points to open up a conducting path or conducting paths. This repairing scheme is used in many areas including, but not limited to, removing shorts created by manufacturing defects, disabling or enabling a portion of a circuit, isolating a portion of a circuit, and attaching a spare or redundant sub-circuit replacing a sub-circuit that has been detached from a main circuit. To program a memory circuit array, computer 30 sends control signals based on the data collected from each IC on wafer 40. IC circuitry 50 of probing device 42 configures the probe points to enable direct programming of fuses or anti-fuses through the probe points. A Read Only memory circuit array is typically a programmable read only memory (PROM) or a programmable logic array (PLA).
[0039] The present invention allows a single semiconductor test and circuit configuration system to perform any or all of the following functions: (a) reducing the thickness of oxide films, (b) performing functionality tests on integrated circuits, (c) performing burn-in tests on ICs, (d) repairing the circuits, (e) programming fuses or anti-fuses, (f) binning the ICs that have been tested, and (g) collection of a database for immediate feedback to the manufacturing process.
[0040] First, the present invention can be used to reduce the thickness of oxide films on contact pads of ICs. A typical IC contact pad is made of aluminum, and it naturally forms a 25 Å to 40 Å oxide film on the surface of the contact pad soon after the contact pad is exposed to oxygen. This oxide film optionally can be penetrated by a piercing probe point as described in U.S. Pat. No. 5,323,035 in order to achieve a low resistance contact between a probing point and the contact pad. In operation, when a wafer is moved from wafer cassette 22 onto a holding fixture 16ain module 14a, a non-oxidizing gas such as nitrogen is introduced to flood chamber 10 and to purge the chamber of oxygen. Then the temperature of the wafer is changed to a specific temperature appropriate for the metal of the contact pads, and a few percent by volume of hydrogen is introduced over the surface of the wafer so that the oxide films can be converted into water vapor when they are combined with hydrogen. The oxide films may be completely removed from the contact pads, or at least the thickness of the oxide films will be reduced by this process. By maintaining a nitrogen environment in chamber 10, no further oxide is formed on the surface of the metal contact pads, thus providing better contacts between the contact pads and the probing points. Nitrogen is a preferred non-oxidizing gas, and there may be other gases such as argon that may be used in chamber 10.
[0041] Second, the present invention can be used for functional testing of integrated circuits. After the oxide films on the contact pads have been removed or reduced in thickness, or subsequently are to be pierced, the probing points of the probing device come into contact with the contact pads on the wafer. Computer 30 controls the functional testing of the ICs on the wafer. Computer 30 supplies the control signals, receives data signals back from the probing points, and analyzes the data to determine which ICs are functional on the wafer.
[0042] Third, the present invention can also perform burn-in of integrated circuits. During burn-in, the integrated circuits on the wafers are tested for a predetermined period of time over a range of predetermined temperature and electrical conditions to produce burn-in data which is transmitted to computer 30 for analysis.
[0043] Fourth, after obtaining data from the ICs, computer 30 can analyze the data and bin or speed-grade the integrated circuits according to their individually determined maximum performance.
[0044] Fifth, the present invention can also be used to repair the circuits. Computer 30 can supply appropriate control signals to the probe points of the probing device so that appropriate voltage or current can be applied between the probe points to electrically isolate defective portion of an IC or electrically connect spare circuit portions of an IC with the use of fuse and anti-fuse circuit devices. Under appropriate circumstance, arbitrary shorts in a circuit may be opened if probe points are positioned anticipating such short failure condition.
[0045] Sixth, the present invention provides a means for programming PROM, EEPROM or PLA circuits. The programming done is typically to pre-set or store binary values in non-volatile memories such as PROM or EEPROM. Small non-volatile memories in microprocessor circuits may also be programmed with serial numbers or version numbers, and configuration or operational parameters that have been generated by test/burn-in processing. Logic products with non-volatile memory may also be programmed such as PLA's or FPLA's. The present invention can also verify and test the capabilities of the circuits after it has been programmed. Thus, if the wafers in chamber 10 contain memory circuits, computer 30 can supply control signals to the probe points so that the probe points can apply appropriate charges to the circuits within the memory circuits. The ICs can be re-tested for their functionality or burned-in after the circuits are repaired and/or programmed. Also, the binning process can be performed after a functionality test, burn-in or circuit configuration.
[0046] Seventh, the present invention provides a means for generating a computer database with the various status information for every circuit processed. This database can be used in subsequent processing steps by the present invention, such as in the repairing or programming steps. One important aspect of the database is that it can provide timely performance distribution statistics and physical distribution statistics to the circuit manufacturing engineers or process engineers. Presently, such information is only partially available after packaging is completed, typically several weeks later. The present invention would make the availability of this information timely enough to allow adjustments to be made to the manufacturing process so that processing steps that are slowly going out of specification and affecting product quality can be corrected. The capability of near-real time adjustments to the manufacturing process will allow savings by reducing the number of products that do not satisfy specifications.
[0047] FIG. 4 presents a flow chart illustrating a typical process flow of the present invention. At step 82, a wafer cassette having a plurality of wafers is inserted into the chamber. At step 84, the chamber is closed. At step 86, the wafers are loaded into the individual modules using handler 12 in FIG. 1. At step 88, a non-oxidizing gas such as nitrogen is introduced into chamber 10 to flood the chamber and purge the chamber of oxygen and moisture. At step 90, the wafers are heated. At step 92, a few percent by volume of hydrogen is introduced over the surfaces of the wafers. At step 94, the oxide films on the contact pads of the wafers are removed or reduced in thickness when the oxides combine with hydrogen. At step 96, hydrogen is stopped from flowing into chamber 10, but nitrogen continues to be supplied to chamber 10 to maintain a nitrogen environment in chamber 10. At step 98, the ICs are probed for a functionality test and/or electrical burn-in. At step 100, circuit configuration can be performed to either repair the circuits and/or to program the circuits if the circuits are non-volatile memory circuits. At step 102, the ICs on the wafers can be re-tested for their functionality. At step 104, computer 30 in FIG. 1 can analyze the data obtained from the ICs and bin the ICs according to their performance characteristics. At step 106, the wafers are unloaded from the holding fixtures and placed into the wafer cassette. At step 108, the chamber is opened to take the wafer cassette out from the chamber.
[0048] FIG. 5 shows a computer system that may be utilized as computer 30 in FIG. 1 in accordance with the present invention. A computer host 1000 includes a memory 1008 and a central processor 1002. Memory 1008 and central processor 1002 are those typically found in most general purpose computers and almost all special purpose computers. In fact, these devices contained within computer host 1000 are intended to be representative of the broad category of data processors and memory. Many commercially available computers having different capabilities may be utilized in the present invention. It will be appreciated that although computer 30 may include various other components described below, it may only need computer host 1000 to control the elements in chamber 10.
[0049] A system bus 1016 is provided for communicating information to and from computer host 1000 and the electronics in chamber 10 to allow control and the transfer of data. System bus 1016 can also be used to connect computer host 1000 to other components. For example, a display device 1010 utilized with the computer system of the present invention may be a liquid crystal device, cathode ray tube or other display device suitable for creating graphic images and/or alphanumeric characters recognizable to a user. The computer system may also include an alphanumeric input device 1012 including alphanumeric and function keys coupled to bus 1016 for communicating information and command selections to central processor 1002, and a cursor control device 1018 coupled to bus 1016 for communicating user input information and command selections to central processor 1002 based on a user's hand movement. Cursor control device 1018 allows the user to dynamically signal the two-dimensional movement of the visual symbol (or cursor) on a display screen of display device 1010. Many implementations of cursor control device 1018 are known in the art, including a track ball, mouse, pen, joystick or special keys on the alphanumeric input device 1012, all capable of signaling movement in a given direction or manner of displacement.
[0050] The computer system of FIG. 5 also includes an interface device 1019 coupled to bus 1016 for communicating information to and from the computer system. Interface device 1019 may be coupled to a microphone, a speaker, a network system, other memory devices, other computers, etc. Also available for interface with the computer system of the present invention is a data storage device 1017 such as a magnetic disk or optical disk drive, which may be communicatively coupled with bus 1016, for storing data and instructions. The computer system of FIG. 5 may also include a printer for outputting data.
[0051] Although functional testing is the typical testing capability of the preferred environment, parametric testing can also be done for circuit characterization. The software that controls the mechanics of the present invention, the data preparation for testing, test processing, and test result analyzing complements the circuitry contained in the probing devices contained in the modules.
[0052] While the present invention has been particularly described with reference to the various figures, it should be understood that the figures are for illustration only and should not be taken as limiting the scope of the invention. Many changes and modifications may be made to the invention, by one having ordinary skill in the art, without departing from the spirit and scope of the invention.
Claims
What is claimed is:
1. A system for performing processing of a multiplicity of yet-undiced integrated circuits formed on a first substrate, each of said integrated circuits having a plurality of conductive contact portions, said system using a first full-substrate probing device for simultaneously contacting and for processing substantially all integrated circuits formed on said first substrate including a first integrated circuit on said first substrate to be processed and a last integrated circuit on said first substrate to be processed, said full-substrate probing device being formed from a semiconductor substrate having integrated processing electronics formed thereon for generating a preponderance of test signals required for performing at least one of functional testing, at-speed functional testing and burn-in processing, said integrated processing electronics being controlled by a programmed computer including a random access memory, said system comprising:
a first module having:
a first holding fixture for holding said first substrate, wherein maximum travel, in a plane parallel to said first substrate, between said holding fixture and said full-substrate probing device, is a distance across a limited central portion of said first substrate, and said holding fixture holds said first substrate in a fixed position from a time at which said first one of said integrated circuits is processed to a time at which said last one of said integrated circuits is processed; and
means for electrically coupling said computer to said integrated processing electronics formed on said first full-substrate probing device, said means for coupling providing substantially fewer signal lines to said integrated processing electronics of the full-substrate probing device than said full-substrate probing device has probe points;
wherein said first module causes electrical coupling of said plurality of conductive contact portions to probe points of said first full-substrate probing device.
2. The system according to claim 1, wherein at least one module of said first and second modules further comprises:
a temperature control device for modifying the temperature of at least one of said first and second substrates.
3. The system according to claim 1 wherein at least one said first and second modules further comprises:
a gas source for supplying at least a non-oxidizing gas into said at least one module.
4. The system according to claim 3 wherein, to reduce the thickness of the oxides on said plurality of conductive contact portions of said at least one substrate, said temperature control device modifies the temperature of said at least one substrate, and said gas source provides hydrogen over said oxides.
5. The system according to claim 1 comprising a handler for moving said first and second substrates.
6. The system according to claim 5 further comprising a computer coupled to said chamber for controlling and communicating with said handler, said temperature control device, said first and second holding fixtures and said first and second probing devices, said computer including a processor and a data storage device
wherein at least one of the functions listed below is performed while at least one of said first and second substrates is in said chamber:
(a) reducing the thickness of oxides on said plurality of conductive contact portions of said at least one substrate;
(b) testing functionality of said integrated circuits of said at least one substrate;
(c) burning-in said at least one substrate;
(d) repairing said integrated circuits of said at least one substrate;
(e) programming said integrated circuits of said at least one substrate;
(f) marking a symbol on said at least one substrate; and,
(g) collection of data corresponding to performance data of said integrated circuits for a database to provide manufacturing process control feedback.
7. The system according to claim 1 wherein at least one of said modules comprises an electronic circuit board coupled to a computer.
8. The system according to claim 1 wherein said integrated circuits of said at least one substrate are functionally tested, burned-in and configured in said chamber.
9. The system according to claim 1 wherein said at least one module is gas tight.
10. The system according to claim 1 wherein said at least one substrate is a whole semiconductor wafer.
11. The system according to claim 10 farther including said computer coupled to said chamber for controlling and communicating with said handler, said temperature control device, said first and second holding fixtures and said first and second probing devices, said computer including a processor and a data storage device
wherein at least one of the functions listed below is performed while at least one of said first and second substrates is in said chamber:
(a) reducing the thickness of oxides on said plurality of conductive contact portions of said at least one substrate;
(b) concurrently testing functionality of substantially all of said integrated circuits of said at least one substrate;
(c) concurrently burning-in substantially all of said integrated circuits of said at least one substrate;
(d) concurrently repairing substantially all of said integrated circuits of said at least one substrate;
(e) concurrently programming substantially all of said integrated circuits of said at least one substrate;
(f) marking a symbol on said at least one substrate; and,
(g) collection of data corresponding to performance data of said integrated circuits for a database to provide manufacturing process control feedback.
12. The system according to claim 1 further including a second temperature control device for modifying the temperature of said second substrate, wherein said first module and said second module perform same functions simultaneously.
13. The system of claim 1 further comprising said first probing device, wherein said first probing device includes integrated test electronics for performing both functional testing and burn-in testing of integrated circuits.
14. The system of claim 13, wherein said first probing device is a full-substrate probing device.
15. The system of claim 14, further comprising:
a second module having:
a second holding fixture, said holding fixture for holding a second substrate having integrated circuits, each of said integrated circuits having a plurality of conductive contact portions; and
means for coupling a computer to a second probing device of a type having integrated test electronics for performing testing of integrated circuits;
wherein said second module causes coupling of said plurality of conductive contact portions to probe points of said second probing device.
16. The system of claim 1, further comprising said first probing device, including a plurality of probe points for simultaneously contacting substantially all of the contact pads on an integrated circuit wafer;
wherein said integrated test electronics allow each circuit to be individually electrically tested.
17. The system according to claim 16 further comprising:
a gas source for supplying at least a first gas into said system; and
a first temperature control device for modifying the temperature in an area of said circuit having at least a conductive contact portion and oxide, said oxide disposed on said conductive contact portion wherein when said first gas is present in said system and when said area is heated, the thickness of said oxide is reduced.
18. The system according to claim 17 wherein said gas source provides a second gas that is non-oxidizing, and said first gas is hydrogen.
19. The system according to claim 17 wherein said system is a gas tight system.
20. The system according to claim 16 including a plurality of internal modules wherein:
a first one of said internal modules includes said first probing device and the first holding fixture for holding a first wafer; and
a second one of said internal modules includes
a second probing device having integrated test electronics and having a plurality of probe points for simultaneously contacting substantially all of a plurality of contact pads on a second wafer,
means for coupling a computer to the second probing device to allow each of a plurality of circuits on the second wafer to be individually electronically tested, and,
a second holding fixture for holding the second wafer.
21. The system according to claim 20 further including a handler for moving said first and second wafers and for moving said first and second probing devices;
wherein said means for coupling a computer to the first probing device includes a first electronic circuit board for interfacing with integral test electronics of said first probing device;
wherein said means for coupling a computer to the second probing device includes a second electronic circuit board for interfacing with integral test electronics of said second probing device; and
wherein said computer sends signals to and receives signals from said handler, said first and second electronic circuit boards, and said first and second holding fixtures.
22. The system according to claim 16 wherein said integral test electronics comprises integrated circuitry.
23. The system according to claim 22 wherein said integrated circuitry comprises active switching circuits.
24. The system according to claim 16 wherein said plurality of probe points comprises a number of probe points exceeding 10,000.
25. The system according to claim 16 wherein the probing device comprises a membrane including said plurality of probe points.
26. The system according to claim 25 wherein said first control electronics comprises integrated circuitry in the first probing device.
27. The system according to claim 26 wherein said integrated circuitry comprises active switching circuits.
28. The system according to claim 25 wherein said plurality of probe points comprises a number of probe points exceeding 10,000.
29. The system according to claim 25 further comprising:
a gas source for supplying at least a first gas into said system;
a first temperature control device for modifying the temperature in an area of said circuit having at least a conductive contact portion and oxide, said oxide disposed on said conductive contact portion wherein when said first gas is present in said system and when said area is heated, the thickness of said oxide is reduced.
30. The system according to claim 29 wherein said gas source provides a second gas that is non-oxidizing, and said first gas is hydrogen.
31. The system according to claim 29 wherein said system is a gas tight system.
32. The system according to claim 25 including a plurality of internal modules wherein
a first one of said internal modules includes said first probing device and the first holding fixture for holding a first wafer; and
a second one of said internal modules includes
a second probing device having integrated test electronics and having a plurality of probe points for simultaneously contacting substantially all of a plurality of contact pads on a second wafer,
means for coupling a computer to the second probing device to allow each of a plurality of circuits on the second wafer to be individually electronically tested and,
a second holding fixture for holding the second wafer.
33. The system according to claim 32 further including a handler for moving said first and second wafers and for moving said first and second probing devices;
wherein said means for coupling a computer to the first probing device includes a first electronic circuit board for interfacing with integral test electronics of said first probing device;
wherein said means for coupling a computer to the second probing device includes a second electronic circuit board for interfacing with integral test electronics of said second probing device; and
wherein said computer sends signals to and receives signals from said handler, said first and second electronic circuit boards, and said first and second holding fixtures.
34. The system according to claim 33 wherein said probe points of said first probing device are in contact with said conductive contact portions of said integrated circuits of said first substrate for functional circuit testing, electrical burn-in, repair, or programming wherein
for said functional circuit testing, said computer sends first electrical signals to said first electronic circuit board, said first electronic circuit board sends second electrical signals to said circuits of said first probing device so that third electrical signals are applied to said conductive contact portions of said integrated circuits of said first substrate through said probe points of said first probing device, and fourth electrical signals produced in response to said third electrical signals are transmitted to said computer;
for said electrical burn-in, each of said integrated circuits of said first substrate is tested for a predetermined time period over a range of predetermined temperature and electrical conditions to produce burn-in data;
for said repair, said computer sends electrical signals causing an electrical stimulus to be applied via selected ones of said probe points to cause one of a fuse circuit device and an anti-fuse circuit device to change state; and
for said programming, said computer sends electrical signals causing electrical stimuli to be applied via selected ones of said probe points to cause binary values to be stored non-volatiley in said circuits.
35. The system according to claim 34 wherein
said computer analyzes data corresponding to said fourth electrical signals or said burn-in data and produces circuit repair or circuit programming signals wherein said first probing device performs circuit repair using said circuit repair signals or programs said integrated circuits of said first substrate through said probe points of said first probing device.
36. The system according to claim 35 wherein said computer generates a database from performance data corresponding to each of said integrated circuits of said first substrate for manufacturing control immediately after completion of substrate fabrication.
37. The apparatus of claim 1 further comprising said first probing device.
38. The apparatus of claim 37 wherein said integrated test electronics are passive only.
39. The apparatus of claim 1 wherein said integrated test electronics include active switching circuitry.
40. The apparatus of claim 39, wherein said active switching circuitry causes a given signal line to be coupled to a first probe point at a first time and a second different probe point at a second different time.
41. The apparatus of claim 40 wherein said first and second probe points each correspond to an output pad of an integrated circuit.
42. A system for performing processing of a multiplicity of yet-undiced integrated circuits formed on a first substrate, each of said integrated circuits having a plurality of conductive contact portions, said system using a first full-substrate probing device for simultaneously contacting and for processing substantially all integrated circuits formed on said first substrate including a first integrated circuit on said first substrate to be processed and a last integrated circuit on said first substrate to be processed, said full-substrate probing device being formed from a semiconductor substrate having integrated processing electronics formed thereon for generating a preponderance of test signals required for performing at least one of functional testing, at-speed functional testing and burn-in processing, said system comprising:
a first module having:
a first holding fixture for holding said first substrate, wherein maximum travel, in a plane parallel to said first substrate, between said holding fixture and said full-substrate probing device, is a distance across a limited central portion of said first substrate, and said holding fixture holds said first substrate in a fixed position from a time at which said first one of said integrated circuits is processed to a time at which said last one of said integrated circuits is processed;
a programmed computer including a random access memory for controlling said integrated processing electronics formed on said first full-substrate probing device and for causing electrical coupling of said plurality of conductive contact portions to probe points of said first full-substrate probing device, wherein throughout processing of said first substrate each respective probe point is electrically coupled to conductive contacts of no more than a single respective integrated circuit; and
means for electrically coupling said computer to said integrated processing electronics formed on said first full-substrate probing device, said means for coupling providing substantially fewer signal lines to said integrated processing electronics of the full-substrate probing device than said full-substrate probing device has probe points.
43. A system for performing processing of a multiplicity of yet-undiced integrated circuits formed on a first substrate, integrated circuits to be processed including substantially all said integrated circuits, from a first integrated circuit on said first substrate to be processed to a last integrated circuit on said first substrate to be processed, said integrated circuits having a plurality of conductive contact portions, said system comprising:
a first module having:
a first holding fixture for holding said first substrate, wherein maximum travel, in a plane parallel to said first substrate, between said holding fixture and said full-substrate probing device, is a distance across a limited central portion of said first substrate, and said holding fixture holds said first substrate in a fixed position from a time at which said first one of said integrated circuits is processed to a time at which said last one of said integrated circuits is processed;
a first full-substrate probing device for simultaneously contacting and for processing substantially all integrated circuit die formed on said first substrate, said full-substrate probing device being formed from a semiconductor substrate having integrated processing electronics formed thereon for generating a preponderance of test signals required for performing at least one of functional testing, at-speed functional testing and burn-in processing;
a programmed computer including a random access memory for controlling said integrated processing electronics formed on said first full-substrate probing device and for causing electrical coupling of said plurality of conductive contact portions to probe points of said first full-substrate probing device, wherein throughout processing of said first substrate each respective probe point is electrically coupled to conductive contacts of no more than a single respective integrated circuit; and
means for electrically coupling said computer to said integrated processing electronics formed on said first full-substrate probing device, said means for coupling providing substantially fewer signal lines to said integrated processing electronics of the full-substrate probing device than said full-substrate probing device has probe points.
44. A system for performing processing of a multiplicity of yet-undiced integrated circuits formed on a first substrate, each of said integrated circuits having a plurality of conductive contact portions, said system using a first full-substrate probing device for simultaneously contacting and for processing substantially all integrated circuits formed on said first substrate including a first integrated circuit on said first substrate to be processed and a last integrated circuit on said first substrate to be processed, said full-substrate probing device being formed from a semiconductor substrate having integrated processing electronics formed thereon for generating a preponderance of test signals required for performing at least two different functions selected from the group consisting of functional testing, at-speed functional testing, burn-in, programming and repair processing, said integrated processing electronics being controlled by a programmed computer including a random access memory, said system comprising:
a first module having:
a first holding fixture for holding said first substrate, wherein maximum travel, in a plane parallel to said first substrate, between said holding fixture and said full-substrate probing device, is a distance across a limited central portion of said first substrate, and said holding fixture holds said first substrate in a fixed position from a time at which said first one of said integrated circuits is processed to a time at which said last one of said integrated circuits is processed; and
means for electrically coupling said computer to said integrated processing electronics formed on said first full-substrate probing device, said means for coupling providing substantially fewer signal lines to said integrated processing electronics than said first full-substrate probing device has probe points, signals carried by said signal lines including control signals controlling the type of processing to be performed;
wherein said first module causes electrical coupling of said plurality of conductive contact portions to probe points of said first full-substrate probing device.
45. A system for performing processing of a multiplicity of yet-undiced integrated circuits formed on a first substrate, each of said integrated circuits having a plurality of conductive contact portions, said system using a first full-substrate probing device for simultaneously contacting and for processing substantially all integrated circuits formed on said first substrate including a first integrated circuit on said first substrate to be processed and a last integrated circuit on said first substrate to be processed, said full-substrate probing device being formed from a semiconductor substrate having integrated processing electronics formed thereon for performing at least one of functional testing, at-speed functional testing and burn-in processing, said integrated processing electronics being controlled by a programmed computer including a random access memory, said system comprising:
a first module having:
a first holding fixture for holding said first substrate, including a thermal control unit for controlling temperature of the first substrate, wherein maximum travel, in a plane of said first substrate, between said holding fixture and said full-substrate probing device, is a distance across a limited central portion of said first substrate, and said holding fixture holds said first substrate in a fixed position from a time at which said first one of said integrated circuits is processed to a time at which said last one of said integrated circuits is processed;
a controlled-atmosphere chamber surrounding said holding fixture and including a gas source for, in cooperation with said thermal control unit, creating an atmosphere for reducing oxides on said conductive contact portions; and
means for electrically coupling said computer to said integrated processing electronics formed on said first full-substrate probing device, said means for coupling providing substantially fewer signal lines to said integrated processing electronics of the full-substrate probing device than said full-substrate probing device has probe points;
wherein said first module causes electrical coupling of said plurality of conductive contact portions to probe points of said first full-substrate probing device.
46. A system for performing processing of a multiplicity of yet-undiced integrated circuits formed on a first substrate, each of said integrated circuits having a plurality of conductive contact portions, said system using a first full-substrate probing device for simultaneously contacting and for processing substantially all integrated circuits formed on said first substrate including a first integrated circuit on said first substrate to be processed and a last integrated circuit on said first substrate to be processed, said full-substrate probing device being formed from a semiconductor substrate having integrated processing electronics formed thereon for performing at least one of functional testing, at-speed functional testing and bum-in processing, said integrated processing electronics being controlled by a general-purpose programmed computer including a random access memory, said system comprising:
a first module having:
a first holding fixture for holding said first substrate, wherein maximum travel, in a plane parallel to said first substrate, between said holding fixture and said full-substrate probing device, is a distance across a limited central portion of said first substrate, and said holding fixture holds said first substrate in a fixed position from a time at which said first one of said integrated circuits is processed to a time at which said last one of said integrated circuits is processed; and
means for electrically coupling said computer to said integrated processing electronics formed on said first full-substrate probing device, said means for coupling providing substantially fewer signal lines to said integrated processing electronics of the full-substrate probing device than said full-substrate probing device has probe points;
wherein said first module causes electrical coupling of said plurality of conductive contact portions to probe points of said first full-substrate probing device.
47. The system of claim 46 further comprising said first probing device, wherein said first probing device includes integrated test electronics for performing both functional testing and burn-in testing of integrated circuits.
48. The system of claim 47, further comprising:
a second module having:
a second holding fixture, said holding fixture for holding a second substrate having integrated circuits, each of said integrated circuits having a plurality of conductive contact portions; and
means for coupling a computer to a second probing device of a type having integrated test electronics for performing testing of integrated circuits;
wherein said second module causes coupling of said plurality of conductive contact portions to probe points of said second probing device.
49. The system of claim 46, wherein said first probing device is a full-substrate probing device.
50. The system according to claim 49, wherein at least one module of said first and second modules further comprises:
a temperature control device for modifying the temperature of at least one of said first and second substrates.
51. The system according to claim 49 wherein, to reduce the thickness of the oxides on said plurality of conductive contact portions of said at least one substrate, said temperature control device modifies the temperature of said at least one substrate, and said gas source provides hydrogen over said oxides.
52. The system according to claim 51 further comprising a computer coupled to said chamber for controlling and communicating with said handler, said temperature control device, said first and second holding fixtures and said first and second probing devices, said computer including a processor and a data storage device
wherein at least one of the functions listed below is performed while at least one of said first and second substrates is in said chamber:
(a) reducing the thickness of oxides on said plurality of conductive contact portions of said at least one substrate;
(b) testing functionality of said integrated circuits of said at least one substrate;
(c) burning-in said at least one substrate;
(d) repairing said integrated circuits of said at least one substrate;
(e) programming said integrated circuits of said at least one substrate;
(f) marking a symbol on said at least one substrate; and,
(g) collection of data corresponding to performance data of said integrated circuits for a database to provide manufacturing process control feedback.
53. The system according to claim 49 wherein at least one said first and second modules further comprises:
a gas source for supplying at least a non-oxidizing gas into said at least one module.
54. The system according to claim 49 comprising a handler for moving said first and second substrates.
55. The system according to claim 49 wherein at least one of said modules comprises an electronic circuit board coupled to a computer.
56. The system according to claim 49 wherein said integrated circuits of said at least one substrate are functionally tested, burned-in and configured in said chamber.
57. The system according to claim 49 wherein said at least one module is gas tight.
58. The system according to claim 57 further including said computer coupled to said chamber for controlling and communicating with said handler, said temperature control device, said first and second holding fixtures and said first and second probing devices, said computer including a processor and a data storage device
wherein at least one of the functions listed below is performed while at least one of said first and second substrates is in said chamber:
(a) reducing the thickness of oxides on said plurality of conductive contact portions of said at least one substrate;
(b) concurrently testing functionality of substantially all of said integrated circuits of said at least one substrate;
(c) concurrently burning-in substantially all of said integrated circuits of said at least one substrate;
(d) concurrently repairing substantially all of said integrated circuits of said at least one substrate,
(e) concurrently programming substantially all of said integrated circuits of said at least one substrate;
(f) marking a symbol on said at least one substrate; and,
(g) collection of data corresponding to performance data of said integrated circuits for a database to provide manufacturing process control feedback.
59. The system according to claim 49 wherein said at least one substrate is a whole semiconductor wafer.
60. The system according to claim 49 further including a second temperature control device for modifying the temperature of said second substrate, wherein said first module and said second module perform same functions simultaneously.
61. The system of claim 46, further comprising said first probing device, including a plurality of probe points for simultaneously contacting substantially all of the contact pads on an integrated circuit wafer;
wherein said integrated test electronics allow each circuit to be individually electrically tested.
62. The system according to claim 61 further comprising:
a gas source for supplying at least a first gas into said system; and
a first temperature control device for modifying the temperature in an area of said circuit having at least a conductive contact portion and oxide, said oxide disposed on said conductive contact portion wherein when said first gas is present in said system and when said area is heated, the thickness of said oxide is reduced.
63. The system according to claim 62 wherein said gas source provides a second gas that is non-oxidizing, and said first gas is hydrogen.
64. The system according to claim 62 wherein said system is a gas tight system.
65. The system according to claim 61 including a plurality of internal modules wherein:
a first one of said internal modules includes said first probing device and the first holding fixture for holding a first wafer; and
a second one of said internal modules includes
a second probing device having integrated test electronics and having a plurality of probe points for simultaneously contacting substantially all of a plurality of contact pads on a second wafer,
means for coupling a computer to the second probing device to allow each of a plurality of circuits on the second wafer to be individually electronically tested, and,
a second holding fixture for holding the second wafer.
66. The system according to claim 65 further including a handler for moving said first and second wafers and for moving said first and second probing devices;
wherein said means for coupling a computer to the first probing device includes a first electronic circuit board for interfacing with integral test electronics of said first probing device;
wherein said means for coupling a computer to the second probing device includes a second electronic circuit board for interfacing with integral test electronics of said second probing device; and
wherein said computer sends signals to and receives signals from said handler, said first and second electronic circuit boards, and said first and second holding fixtures.
67. The system according to claim 61 wherein said integral test electronics comprises integrated circuitry.
68. The system according to claim 67 wherein said integrated circuitry comprises active switching circuits.
69. The system according to claim 61 wherein said plurality of probe points comprises a number of probe points exceeding 10,000.
70. The system according to claim 61 wherein the probing device comprises a membrane including said plurality of probe points.
71. The system according to claim 70 wherein said first control electronics comprises integrated circuitry in the first probing device.
72. The system according to claim 71 wherein said integrated circuitry comprises active switching circuits.
73. The system according to claim 70 wherein said plurality of probe points comprises a number of probe points exceeding 10,000.
74. The system according to claim 70 further comprising.
a gas source for supplying at least a first gas into said system;
a first temperature control device for modifying the temperature in an area of said circuit having at least a conductive contact portion and oxide, said oxide disposed on said conductive contact portion wherein when said first gas is present in said system and when said area is heated, the thickness of said oxide is reduced.
75. The system according to claim 74 wherein said gas source provides a second gas that is non-oxidizing, and said first gas is hydrogen.
76. The system according to claim 74 wherein said system is a gas tight system.
77. The system according to claim 70 including a plurality of internal modules wherein
a first one of said internal modules includes said first probing device and the first holding fixture for holding a first wafer; and
a second one of said internal modules includes
a second probing device having integrated test electronics and having a plurality of probe points for simultaneously contacting substantially all of a plurality of contact pads on a second wafer,
means for coupling a computer to the second probing device to allow each of a plurality of circuits on the second wafer to be individually electronically tested and,
a second holding fixture for holding the second wafer.
78. The system according to claim 77 further including a handler for moving said first and second wafers and for moving said first and second probing devices;
wherein said means for coupling a computer to the first probing device includes a first electronic circuit board for interfacing with integral test electronics of said first probing device;
wherein said means for coupling a computer to the second probing device includes a second electronic circuit board for interfacing with integral test electronics of said second probing device; and
wherein said computer sends signals to and receives signals from said handler, said first and second electronic circuit boards, and said first and second holding fixtures.
79. The system according to claim 78 wherein said probe points of said first probing device are in contact with said conductive contact portions of said integrated circuits of said first substrate for functional circuit testing, electrical burn-in, repair, or programming wherein
for said functional circuit testing, said computer sends first electrical signals to said first electronic circuit board, said first electronic circuit board sends second electrical signals to said circuits of said first probing device so that third electrical signals are applied to said conductive contact portions of said integrated circuits of said first substrate through said probe points of said first probing device, and fourth electrical signals produced in response to said third electrical signals are transmitted to said computer;
for said electrical burn-in, each of said integrated circuits of said first substrate is tested for a predetermined time period over a range of predetermined temperature and electrical conditions to produce burn-in data;
for said repair, said computer sends electrical signals causing an electrical stimulus to be applied via selected ones of said probe points to cause one of a fuse circuit device and an anti-fuse circuit device to change state; and
for said programming, said computer sends electrical signals causing electrical stimuli to be applied via selected ones of said probe points to cause binary values to be stored non-volatiley in said circuits.
80. The system according to claim 79 wherein
said computer analyzes data corresponding to said fourth electrical signals or said burn-in data and produces circuit repair or circuit programming signals wherein said first probing device performs circuit repair using said circuit repair signals or programs said integrated circuits of said first substrate through said probe points of said first probing device.
81. The system according to claim 80 wherein said computer generates a database from performance data corresponding to each of said integrated circuits of said first substrate for manufacturing control immediately after completion of substrate fabrication.
82. The apparatus of claim 46 further comprising said first probing device.
83. The apparatus of claim 82 wherein said integrated test electronics are passive only.
84. The apparatus of claim 46, wherein said integrated test electronics include active switching circuitry.
85. The apparatus of claim 84, wherein said active switching circuitry causes a given signal line to be coupled to a first probe point at a first time and a second different probe point at a second different time.
86. The apparatus of claim 85, wherein said first and second probe points each correspond to an output pad of an integrated circuit.
Patent Citations (37)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US3108019 | 1963-10-01 | Davis | Examiner |
| US3710251 | 1973-01-01 | Hagge et al. | Examiner |
| US4038599 | 1977-07-01 | Bove et al. | Examiner |
| US4115736 | 1978-09-01 | Tracy | Examiner |
| US4465972 | 1984-08-01 | Sokolich | Examiner |
| US4504783 | 1985-03-01 | Zasio et al. | Examiner |
| US4585991 | 1986-04-01 | Reid et al. | Applicant |
| US4719411 | 1988-01-01 | Buehler | Examiner |
| US4746855 | 1988-05-01 | Wrinn | Examiner |
| US4776747 | 1988-10-01 | Swapp et al. | Examiner |
| US4791364 | 1988-12-01 | Kufis et al. | Examiner |
| US4926117 | 1990-05-01 | Nevill | Examiner |
| US4951601 | 1990-08-01 | Maydan et al. | Examiner |
| US5055780 | 1991-10-01 | Takagi et al. | Applicant |
| US5070297 | 1991-12-01 | Kwon et al. | Examiner |
| US5103557 | 1992-04-01 | Leedy | Applicant |
| US5148100 | 1992-09-01 | Sekiba | Examiner |
| US5310410 | 1994-05-01 | Begin et al. | Examiner |
| US5323035 | 1994-06-01 | Leedy | Applicant |
| US5323107 | 1994-06-01 | D'Souza | Examiner |
| US5325052 | 1994-06-01 | Yamashita | Applicant |
| US5336992 | 1994-08-01 | Saito et al. | Applicant |
| US5354695 | 1994-10-01 | Leedy | Applicant |
| US5434513 | 1995-07-01 | Fujii et al. | Examiner |
| US5453404 | 1995-09-01 | Leedy | Applicant |
| US5457380 | 1995-10-01 | Blumenau | Examiner |
| US5495179 | 1996-02-01 | Wood et al. | Examiner |
| US5510724 | 1996-04-01 | Itoyama et al. | Applicant |
| US5517126 | 1996-05-01 | Yamaguchi | Applicant |
| US5521522 | 1996-05-01 | Abe et al. | Examiner |
| US5532610 | 1996-07-01 | Tsujide et al. | Examiner |
| US5555422 | 1996-09-01 | Nakano | Examiner |
| WO89/11659 | 1989-11-01 | Applicant | |
| WO91/12706 | 1991-08-01 | Applicant | |
| WO93/16394 | 1993-08-01 | Applicant | |
| WO93/21748 | 1993-10-01 | Applicant | |
| WO94/09513 | 1994-04-01 | Applicant |
Non-Patent Literature (1)
- Microelectronics, Millman, Jacob and Grabel, Arvin, Programmable ROMs (PROMs), 2d, pp. 301-304, McGraw Hill, New York.Applicant