Inkjet head control system and method

[0002] 1. Field of the Invention

[0003] The present invention relates to an inkjet recording apparatus which is capable of ejecting ink droplets by making use of a piezoelectric element, and more particularly to a control system and method which controls a driving pulse applied to the piezoelectric element.

[0004] 2. Description of the Related Art

[0005] There has recently been a growing interest in non-impact recording methods, because noise while recording is extremely small to such a degree that it can be neglected. Particularly, inkjet recording methods are extremely effective in that they are structurally simple and in that they can perform high-speed recording directly onto ordinary medium. There has been proposed an inkjet recording method making use of a piezoelectric element.

[0006] In the inkjet recording method making use of a piezoelectric element, a driving pulse is applied to a selected piezoelectric element and thereby the piezoelectric element is deformed to eject an ink droplet. The waveform of the driving pulse is very important to stabilize the ink ejection and improve the quality of printing because the stable and proper waveform of the driving pulse produces the stable amount of ejected ink droplet and the optimal ejection velocity. However, a variation in waveform of the the driving pulse is cause by variations in capacitance of the piezoelectric element and characteristics of each circuit element, resulting in variations in amount and ejection velocity of ink droplet.

[0007] To stabilize the ink droplet ejection to improve the quality of printing, there has been proposed an inkjet head driver in Japanese Patent Unexamined Publication No. 6-182993. The inkjet head driver sets a driving pulse to a desired voltage by adjusting the time constant and the rising time of the driving pulse.

[0008] However, the rising time is adjusted by changing the variable resistor or replacing a resistor with another resistor. Therefore, it is necessary to do the resistor adjustment prior to shipments and such adjustment is a time-consuming step. Further, after shipments, it is very difficult to adjust the rising time to cancel out a variation in pulse waveform due to a change of ambient temperature, resulting in reduced stability of the quality of printing.

[0009] Another inkjet head driver has been proposed in Japanese Patent Unexamined Publication No. 8-112894. The inkjet head driver measures the slope of leading or trailing edge of a trapezoidal driving pulse and controls the output current of a variable current source depending on an error obtained by comparing the measured slope with a preset slope.

[0010] However, the conventional inkjet head driver needs the steps of slope measurement which is not simple, resulting in increased burden upon a control processor.

[0011] It is an objective of the present invention to provide control system and method for use in an inkjet recording apparatus which can achieve the reliable and stable ink droplet ejection with simplified control.

[0012] According to the present invention, a control system for controlling a driving pulse applied to a piezoelectric element of an inkjet head is comprised of a variable-voltage source for producing a control voltage depending on a control signal; a pulse generator for generating a driving pulse having a voltage waveform with a slope determine depending on the control voltage; a monitor for monitoring a peak voltage of the driving pulse; and a controller for adjusting the control signal so that the peak voltage reaches a predetermined voltage.

[0013] As described above, the control signal is adjusted so that the peak voltage reaches the predetermined voltage and the waveform of the driving pulse is automatically set to a desired trapezoidal waveform with a slope determined depending on the control voltage. Therefore, the piezoelectric element properly deforms with stability even in the case of a change in temperature, resulting in the stable quality of printing.

[0014] Further, only the control voltage causes the slope and the height of the voltage waveform to be determined. Therefore, the waveform control is simplified with improved stability.

[0015] The pulse generator may be comprised of a constant-current source for producing first and second constant currents determined by the first and second control voltages, respectively; a waveform forming circuit for producing a voltage pulse having the voltage waveform by charging a capacitor with the first constant current for a first predetermined time period and then discharging the capacitor with the second constant current for a second predetermined time period; and an amplifier for amplifying the voltage pulse to produce the driving pulse.

[0016] The waveform forming circuit may be comprised of a timing generator for generating a first timing pulse having a pulse width of the first predetermined time period and a second timing pulse having a pulse width of the second predetermined time period wherein there is a predetermined time interval between a trailing edge of the first timing pulse and a leading edge of the second timing pulse; and a waveform controller for producing the voltage pulse having a trapezoidal waveform where a leading-edge slope and a height of the trapezoidal waveform is determined by the first constant current, a trailing-edge slope is determined by the second constant current.

[0017] The above and other objects and advantages will become apparent from the following detailed description when read in conjunction with the accompanying drawing wherein:

[0018] FIG. 1 is a schematic block diagram showing the circuit configuration of an inkjet recording apparatus according to an embodiment according to the present invention;

[0019] FIG. 2 is a block diagram showing the more detailed circuit configuration of the embodiment as shown in FIG. 1;

[0020] FIG. 3 is a flow chart showing a control operation in the embodiment;

[0021] FIG. 4 is a detailed circuit diagram showing a waveform generating circuit in the embodiment;

[0022] FIG. 5A is a waveform diagram showing an example of a driving pulse to be applied to a piezoelectric element of the inkjet recording apparatus according to the embodiment;

[0023] FIG. 5B is a waveform diagram showing charge and discharge timing signals and voltage measurement timing signal in the case of the driving pulse as shown in FIG. 5A;

[0024] FIG. 6A is a waveform diagram showing an example of a driving pulse to be applied to a piezoelectric element for explanation of a voltage control operation of the embodiment;

[0025] FIG. 6B is a waveform diagram showing charge timing signal and voltage measurement timing signal in the case of the driving pulse as shown in FIG. 6A;

[0026] FIG. 7A is a waveform diagram showing another example of a driving pulse to be applied to a piezoelectric element for explanation of a voltage control operation of the embodiment; and

[0027] FIG. 7B is a waveform diagram showing charge timing signal and voltage measurement timing signal in the case of the driving pulse as shown in FIG. 7A;

[0028] Referring to FIG. 1, an inkjet recording apparatus has a control loop for controlling the waveform of a driving pulse by adjusting the peak voltage of the driving pulse while detecting the peak voltage applied to a piezoelectric element. More specifically, a controller 10 produces a voltage control signal depending on a detected driving voltage V_M. The voltage control signal makes a variable-voltage source 11 produce a waveform control voltage which is output to a voltage-waveform controller 12. The voltage-waveform controller 12 produces a driving pulse whose waveform is controlled depending on the waveform control voltage and outputs it to an inkjet head 13 making use of a piezoelectric element.

[0029] The voltage V_DRVof the driving pulse is monitored by a driving voltage monitor 14 and the monitored voltage is sampled and converted into digital form by an analog-to-digital converter (ADC) 15 to produce the detected driving voltage V_M. The controller 10 compares the detected driving voltage V_Mto preset voltage and produces the voltage control signal so that the detected driving voltage V_Magrees with the preset voltage. The voltage control signal may be produced so that a difference of the detected driving voltage V_Mand the preset voltage is reduced in units of a predetermined step. The more detailed descriptions will be made hereinafter.

[0030] Referring to FIG. 2, the controller 10 is comprised of a control processor 101, a read-only memory (ROM) 102 storing a program, and a timing generator 103. The control processor 101 is a program-controlled processor on which the program runs. Under control of the control processor 101 running the program, the timing generator 103 generates a charge timing signal S_CSC, a discharge timing signal S_DCHGand a sampling timing signal S_DSCwhich have predetermined pulse widths, respectively.

[0031] The control processor 101 produces a leading-edge form control signal S_Land a trailing-edge form control signal S_Tdepending on a difference of the detected driving voltage V_Mand a preset voltage. The leading-edge form control signal S_Land the trailing-edge form control signal S_Tare a voltage-setting signal which is used to determine the peak voltage and the slopes of the leading edge and the trailing edge of the driving pulse as will be described hereinafter.

[0032] The variable-voltage source 11 may be formed with a digital-to-analog converter (DAC). In this embodiment, the variable-voltage source 11 is comprised of DA converters 104 and 105 which receive the leading-edge form control signal S_Land the trailing-edge form control signal S_Tfrom the control processor 101, respectively. The DA converters 104 and 105 convert the control signals S_Land S_Tto analog voltages V_Land V_T, respectively, which are output to the voltage-waveform controller 12.

[0033] The voltage-waveform controller 12 is comprised of open/close switches SW_Land SW_T, variable current sources 106 and 107, and integrator circuit 108, and a current amplifier 109. The open/close switches SW_Land SW_Tperform open/close operations according to the charge timing signal S_CHGand the discharge timing signal S_DCHG, respectively. The variable current sources 106 and 107 receive the analog voltages V_Land V_Tfrom the DA converters 104 and 105 through the open/close switches SW_Land SW_Tand produce a charge constant current I_CHGand a discharge constant current I_DCHGdepending on the analog voltages V_Land V_T, respectively.

[0034] The integrator circuit 108 includes a capacitor C which is charged or discharged with the charge constant current I_CHGor the discharge constant current I_DCHG. The voltage V_Cacross the capacitor C is output to the current amplifier 109 which produces the driving pulse having a desired trapezoidal waveform. Since I=C×dV_C/dt, the rate of increase of the voltage V_Cis determined by the charge constant current I_CHGand the rate of decrease of the voltage V_Cis determined by the discharge constant current I_DCHG. In other words, the leading-edge form of the driving pulse is determined by the analog voltages V_Land the trailing-edge form of the driving pulse is determined by the analog voltages V_T.

[0035] The voltage V_DRVof the driving pulse is divided by a voltage divider 110 because the voltage V_DRVof the driving pulse is much higher than a voltage used in logic circuits. The resultant divided voltage is converted into digital form by an AD converter 111. The voltage divider 110 is comprised of a plurality of resistors connected in series.

[0036] The AD converter 111 samples a voltage from the divided voltage with the timing of the sampling timing signal S_ADCand then converts it into digital form to produce the detected voltage V_M. As will be described later, the sampling timing signal S_ADCis generated when the voltage V_DRVof the driving pulse is at the peak voltage of the trapezoidal waveform, in other words, at a time instant of the time period corresponding to the upper or shorter base of the trapezoidal waveform. The detected voltage V_Mis output to the control processor 101 where the detected voltage V_Mis compared to data of the preset voltage expected to be applied to a piezoelectric element.

[0037] The voltage V_DRVof the driving pulse is also output to the inkjet head 13 and is applied to a selected piezoelectric element 112. Since the driving pulse is automatically set to the desired trapezoidal waveform having the expected peak voltage and slopes by the control loop adjusting the analog voltage V_Land V_T, the piezoelectric element 112 properly deforms with stability even in the case of a change in temperature, resulting in the stable quality of printing.

[0038] Referring to FIG. 3, when starting the program, the control processor 101 outputs initial control signals S_LOand S_TOto the DA converters 104 and 105, respectively (step S301). The initial control signals S_LOand S_TOare previously stored in the ROM 102 and are expected to provide a desired peak voltage of the driving pulse. The respective initial control signals S_LOand S_TOare converted to initial analog voltages V_LOand V_TO. In general, the analog voltages V_Land V_Tare produced depending on the leading-edge and trailing-edge form control signals S_Land S_T, respectively (step S302).

[0039] The timing generator 103 outputs the charge timing signal S_CHGto the switch SW_L. The charge timing signal S_CHGcauses the switch SW_Lto be closed and the variable current source 106 outputs the charge constant current I_CHGto the integrator circuit 108. As the capacitor C is charged with the charge constant current I_CHG, the voltages V_Clinearly increases and, when the charge timing signal S_CHGfalls and the switch SW_Lis open, the voltages V_Cat that time is kept as a peak value. Therefore, the time-varying voltage V_DRVhaving such an upward slope and the peak value is applied to the piezoelectric elements 112 (step S303). The voltage divider 110 divides the voltage V_DRVto produce a divided voltage (step S304).

[0040] After a lapse of predetermined time interval, the control processor 101 instructs the timing generator 103 to output the sampling timing signal S_ADCto the AD converter 111. This causes the AD converter 111 to sample a voltage from the divided voltage with the timing of the sampling timing signal S_ADCand then converts it into digital form to produce the detected voltage V_M(step S305). Thereafter, the timing generator 103 outputs the discharge timing signal S_DCHGto the switch SW_T. The discharge timing signal S_DCHGcauses the switch SW_Tto be closed and the variable current source 107 provides the discharge constant current T_DCHGto the integrator circuit 108. As the capacitor C is discharged with the discharge constant current I_DCHG,the voltages V_Clinearly decreases and, when or before the discharge timing signal S_DCHGfalls and the switch SW_Tis open, the voltages V_Cfalls to the grounding level.

[0041] When receiving the detected voltage V_Mfrom the AD converter 111, the control processor 101 determines whether the detected voltage V_Mfalls into a predetermined range around an expected voltage V_P(step S306). Here, the control processor 101 calculates an absolute difference between the detected voltage V_Mand the expected voltage V_Pand then compares the absolute difference to a permissible error ε. If the detected voltage V_Mfalls into the predetermined range around the expected voltage V_P(YES in step S306), the driving voltage setting control is terminated.

[0042] Contrarily, if the detected voltage V_Mfalls out of the predetermined range around the expected voltage V_P(NO in step S306), the control processor 101 determines whether the detected voltage V_Mis higher than the expected voltage V_P(step S307). When the detected voltage V_Mis higher than the expected voltage V_P(YES in step S307), the control processor 101 decreases the leading-edge form control signal S_Lby a controlled amount (step S308). When the detected voltage V_Mis not higher than the expected voltage V_P(NO in step S307), the control processor 101 increases the leading-edge form control signal S_Lby a controlled amount (step S309). The controlled amount may be a fixed step or a variable step which increases depending on the absolute difference calculated in the step S306.

[0043] When the leading-edge form control signal S_Lhas been updated, control goes back to the step S302 where the analog voltages V_Land V_Tare produced depending on the leading-edge and trailing-edge form control signals S_Land S_T, respectively. In general, the trailing-edge form control signal S_Tvaries in accordance with the leading-edge form control signal S_L.

[0044] In this manner, the steps S302-S309 are repeatedly performed and the detected voltage V_Mchanges from the initial voltage to the expected voltage V_Pwhile the driving pulse changing in upward and downward slopes thereof. Therefore, the waveform of the driving pulse applied to the piezoelectric element 112 is automatically adjusted.

[0045] It is possible to replace the steps S3076-S309 with a table searching step in FIG. 3. More specifically, the controller 10 is provided with a table storing the leading-edge form control signal S_Land the trailing-edge form control signal S_Twith respect to the difference of a detected voltage V_Mand the expected voltage V_P. When receiving the detected voltage V_M, the control processor 101 calculates the difference of the detected voltage V_Mand the expected voltage V_Pand searches the table for the difference to produce the corresponding control signal S_Land S_T.

[0046] FIG. 4 shows the detailed circuit configuration of an example of the voltage-waveform controller 12. The switch SW_Lis comprised of a transistor Q1 having a collector connected to the DA converter 104 through a resistor R1. The base of the transistor Q1 receives the charge timing signal S_CHGfrom the timing generator 103. The emitter of the transistor Q1 is connected to the variable current source 106.

[0047] The variable current source 106 includes two stages of current mirror circuit. The first current mirror circuit is comprised of transistors Q2 and Q3. The base and collector of the transistor Q2 and the base of the transistor Q3 are connected in common to the emitter of the transistor Q1. The respective emitters of the transistors Q2 and Q3 are grounded through resistors R2 and R3. The collector of the transistor Q3 is connected to the second current mirror circuit through a resistor R4. The second current mirror circuit is comprised of transistors Q4 and Q5. The base and collector of the transistor Q4 and the base of the transistor Q4 are connected in common to the collector of the transistor Q3 through the resistor R4. The respective emitters of the transistors Q4 and Q5 are connected to power supply voltage V_CCthrough resistors R5 and R6. The collector of the transistor Q5 is connected to the integrator circuit 108 and the current amplifier 109. The two states of current mirror circuit is needed to match the logic voltage level of the DA converter 104 (here, +5V) with the power supply voltage V_CC(here, +30V).

[0048] The integrator circuit 108 is comprised of the capacitor C and diodes D1 and D2. The capacitor C is connected to the collector of the transistor Q5 through the diode D1 and to the variable current source 107 through the diode D2.

[0049] When the transistor Q1 is forced into conduction by the charge timing signal S_CHG, the analog voltages V_Lof the DA converter 104 causes a constant current to flow through the resistors R1 and R2. This constant current activates the first and second current mirror circuits and the charge constant current I_CHGflows into the capacitor C through the diode D1 of the integrator circuit 108. As described before, the capacitor C is charged with the charge constant current I_CHGand the voltage V_Cacross the capacitor C increases linearly.

[0050] On the other hand, the switch SW_Tis comprised of a transistor Q6 having a collector connected to the DA converter 105 through a resistor R7. The base of the transistor Q6 receives the discharge timing signal S_DCHGfrom the timing generator 103. The emitter of the transistor Q6 is connected to the variable current source 107.

[0051] The variable current source 107 includes a current mirror circuit. The current mirror circuit is comprised of transistors Q7 and Q8. The base and collector of the transistor Q7 and the base of the transistor Q8 are connected in common to the emitter of the transistor Q6. The respective emitters of the transistors Q7 and Q8 are grounded through resistors R8 and R9. The collector of the transistor Q8 is connected to the capacitor C through the diode D2 of the integrator circuit 108.

[0052] When the transistor Q6 is forced into conduction by the charge timing signal S_DCHG, the analog voltages V_Tof the DA converter 105 causes a constant current to flow though the resistors R7 and R8. This constant current activates the current mirror circuit and the discharge constant current T_DCHGflows from the capacitor C through the diode D2 of the integrator circuit 108. As described before, the capacitor C is discharged with the discharge constant current I_DCHGand the voltage V_Cacross the capacitor C decreases linearly.

[0053] The current amplifier 109 is comprised of transistors Q9 and Q10. The collector of the transistor Q9 is connected to the power supply voltage V_CCand the emitter of the transistor Q9 is connected to that of the transistor Q10. The base of the transistor Q9 is connected to the collector of the transistor Q5 and that of the transistor Q10 is connected to the collector of the transistor Q8. The emitters of the transistors Q9 and Q10 are connected to the inkjet head 13 and the voltage divider 110. The current amplifier 109 provides an output current required to activate the piezoelectric element 112. Therefore, it is possible to use the integrator circuit 108 and the current mirror circuits with the lower rating thereof.

[0054] Referring to FIG. 5A, the control processor 101 running the program has a desired peak voltage V_Pof the driving pulse. As described before, the upward slope 501 and the downward slope 503 of the trapezoidal waveform are automatically determined by the peak voltage of the upper base thereof. Therefore, by adjusting the peak voltage, a desired waveform of the driving pulse can be obtained. The rising time of the upward slope 501 is determined by the charge timing signal S_CHGand the falling time of the downward slope 503 is determined by the discharge timing signal S_DCHG.

[0055] Referring to FIG. 5B, more specifically, the timing generator 103 outputs the charge timing signal S_CHGof a pulse width T₁to the switch SW_Land thereby the switch SW_Lis closed and the variable current source 106 outputs the charge constant current I_CHGto the integrator circuit 108. As the capacitor C is charged with the charge constant current I_CHG, the voltages V_Cacross the capacitor C linearly increases to form the upward slope 501. When the charge timing signal S_CHGfalls and the switch SW_Lis open, the voltages V_Cat that time is kept as the peak voltage to form the upper base 502. Therefore, the time-varying voltage V_DRVhaving such an upward slope and the peak voltage is applied to the piezoelectric elements 112.

[0056] After a lapse of predetermined time interval, the control processor 101 instructs the timing generator 103 to output the sampling timing signal S_ADCto the AD converter 111 and then receives the detected voltage V_M. After a further lapse of predetermined time interval, the timing generator 103 outputs the discharge timing signal S_DCHGof pulse width T₂to the switch SW_Tto be closed and the variable current source 107 provides the discharge constant current I_DCHGto the integrator circuit 108. As the capacitor C is discharged with the discharge constant current I_DCHG, the voltages V_Cacross the capacitor C linearly decreases to form the downward slope 503 and, when or before the discharge timing signal S_DCHGfalls and the switch SW_Tis open, the driving voltage V_DRVfalls to the grounding level.

[0057] Referring to FIGS. 6A and 6B, when starting the program, the control processor 101 produces the initial control signals S_LOand S_TOwhich are expected to provide the desired trapezoidal waveform of the driving pulse. In this initial state, when receiving the detected voltage V_M=V_C1lower than the expected peak voltage V_Pfrom the AD converter 111, the control processor 101 increases the leading-edge form control signal S_Lby a fixed amount which will provide a predetermined voltage increase step ΔV_C. Accordingly, the driving voltage V_DRVlinearly increases with an upward slope 601 corresponding to the updated peak voltage V_C2=V_C1+ΔV_C. In this manner, the control processor 101 repeatedly increases the leading-edge form control signal S_Lin steps of the fixed amount until the peak voltage reaches the expected peak voltage V_P. It is preferable that the initial control signal S_LOis set to a lower value so that the detected voltage V_Mis lower than the expected peak voltage V_P.

[0058] Contrarily, when receiving the detected voltage V_M=V_DOhigher than the expected peak voltage V_Pfrom the AD converter 111, the control processor 101 decreases the leading-edge form control signal S_Lby a fixed amount which will provide a predetermined voltage decrease step ΔV_D. Accordingly, the driving voltage V_DRVlinearly decreases with a downward slope 602 corresponding to the updated peak voltage V_D2=V_D1−ΔV_D. In this manner, the control processor 101 repeatedly decreases the leading-edge form control signal S_Lin steps of the fixed amount until the peak voltage reaches the expected peak voltage V_P.

[0059] As described before, the increase/decrease rate may be a variable step which increases or decreased depending on the absolute difference of the detected voltage and the expected peak voltage.

[0060] According to such waveform adjustment, the waveform of a driving pulse can be properly adjusted to stabilize the ink droplet ejection even in the case of variations of circuit parameters due to a change of ambient temperature.

[0061] Referring to FIGS. 7A and 7B, the present invention can be also applied to the case of negative peak voltage. Since the operation is basically similar to that of the case as shown in FIGS. 6A and 6B, the detailed descriptions are omitted.

[0062] While the invention has been described with reference to the specific embodiment thereof, it will be appreciated by those skilled in the art that numerous variations, and modifications, and combinations are to be reported as being within the scope of the invention.