Semiconductor device

[0002] 1. Field of the Invention

[0003] The present invention relates to a semiconductor device and, in particular, to a semiconductor device having a circuit which generates an internal potential by a charge pump.

[0004] 2. Description of the Background Art

[0005] Recently, semiconductor devices in which a large number of transistors are integrated are used in various electrical equipment, such as workstations and personal computers. Of these semiconductor devices, a DRAM is used as a main memory of personal computers. This DRAM has a charge pump for stetting up power-supply potential. FIG. 11 is a block diagram of a boost circuit contained in a conventional DRAM.

[0006] Referring to FIG. 11, the DRAM has a boost circuit 1 normally operating, and a boost circuit 2 that operates when the DRAM is active. Step-up potential V_PPis outputted by the boost circuits 1 and 2. The boost circuit 1 includes a detecting circuit 3 that compares and amplifies reference potential V_REFand input potential V_IN. The input potential V_INobeys the step-up potential V_PP. The boost circuit 1 further includes a buffering circuit for buffering the output of the detecting circuit 3, a clock generating circuit 5 that outputs a clock signal in response to the output of the buffering circuit 4, and a charge pump 6 driven by the output of the clock generating circuit 5. The charge pump 6 has a low capability of supplying step-up potential V_PP, but has a low power consumption.

[0007] The boost circuit 2 comprises a detecting circuit 7 that compares and amplifies reference potential V_REFand input potential V_IN, a buffering circuit 8 for buffering the output of the detecting circuit 7, and an AND gate 9 that receives the output of the buffering circuit 8 and signal ACTL indicating the activation of the DRAM. The signal ACTL reaches its high level when the DRAM is active. The boost circuit 2 further comprises a clock generating circuit 10 that outputs a clock signal in response to the output of the AND gate 9, and a charge pump 11 driven by the output of the clock generating circuit 10. The charge pump 11 has a higher capability of supplying step-up potential V_PPthan the charge pump 6.

[0008] When the signal ACTL is at its low level indicating the inactive state, from the output of the AND gate 9, a low level is outputted regardless of the detection result of the detecting circuit 7. In response to this low level output, the clock generating circuit 10 stops oscillation of a clock signal. Then, the boost circuit 2 stops step-up operation, and only the boost circuit 1 executes step-up operation.

[0009] It is designed so that the detecting circuits 3 and 7 have the same detecting level. However, because of change in process, the detecting circuit 7 can be ahead of the detecting circuit 3 in detecting a decrease in step-up potential V_PP. Such a circuit has caused the following problems. That is, when signal ACTL is at its low level indicating the inactive state, the detecting circuit 7 detects a decrease in step-up potential V_PPwhereas the detecting circuit 3 does not detect it in some cases. In this case, both clock generating circuits 5 and 10 stop a clock signal oscillation, and both boost circuits 1 and 2 stop step-up operation. As a result, the output node of the detecting circuit 7 becomes an intermediate potential, and a through current passing through the subsequent buffering circuit 8.

[0010] According to a first aspect of the invention, a semiconductor device comprises: a first internal potential generating circuit including: a first detector for detecting a deviation from a predetermined level of an internal potential, a buffer circuit for receiving the output of the first detector, a control circuit for supplying a clock enable signal which becomes disable regardless of the output of the buffer circuit when an activation signal indicates the inactive state, and which is responsive to the output of the buffer circuit when the activation signal indicates the active state, a first oscillator that oscillates a first clock signal in response to the clock enable signal, and a first charge pump that generates the internal potential at an output node, according to the first clock signal; and a second internal potential for generating circuit including: a second detector that is ahead of the first detector in detecting a deviation from the predetermined level of the internal potential, a second oscillator that oscillates a second clock signal in response to the output of the second detector, and a second charge pump that generates the internal potential at the output node, according to the second clock signal.

[0011] According to a second aspect, the semiconductor device of the first aspect is characterized in that the second charge pump has a smaller capability of supplying the internal potential than the first charge pump.

[0012] According to a third aspect, the semiconductor device of the first aspect is characterized in that the second internal potential generating circuit further includes a buffer circuit for receiving the output of the second detector and supplying a clock enable signal to the second oscillator.

[0013] According to a fourth aspect, the semiconductor device of the first aspect is characterized in that the second detector detects a deviation from the predetermined level of the internal potential, based on the result of a comparison of a reference potential with an internal potential related potential related to the internal potential.

[0014] According to a fifth aspect, the semiconductor device of the fourth aspect further comprises: a level shifter for performing level shifting of the internal potential to supply a shift potential, the internal potential related potential includes the shift potential, characterized in that the second detector includes a current mirror circuit, and first and second transistors which are connected to the current mirror circuit and receive at their respective gates the shift potential and the reference potential, the first and second transistors have different current drive capabilities.

[0015] According to a sixth aspect, the semiconductor device of the fifth aspect is characterized in that the first and second transistors are of a first conductivity type, the current mirror circuit includes a third transistor of a second conductivity type having a drain and gate connected to the drain of the first transistor in common, and a fourth transistor of the second conductivity type having a drain connected to the drain of the second transistor, and having a gate connected to the gate of the third transistor; the second transistor has a greater channel width than the first transistor; and the output of the second detector is supplied from between the drains of the second and fourth transistors.

[0016] According to a seventh aspect, the semiconductor device of the first aspect is characterized in that the first detector detects a deviation from the predetermined level of the internal potential, based on the result of a comparison of a reference potential with an internal potential related potential related to the internal potential; and the second detector detects a deviation from the predetermined level of the internal potential, based on the result of a comparison of the reference potential with the internal potential related potential.

[0017] According to an eighth aspect, the semiconductor device of the seventh aspect further comprises: a level shifter for performing level shifting of the internal potential to supply a shift potential, the internal potential related potential including the shift potential, characterized in that the first detector includes a first current mirror circuit, and first and second transistors which are connected to the first current mirror circuit and receive at their respective gates the shift potential and the reference potential; the second detector includes a second current mirror circuit, and third and fourth transistors which are connected to the second current minor circuit and receive at their respective gates the shift potential and the reference potential; and the ratio of current drive capability of the first transistor to the second transistor is different from the ratio of current drive capability of the third transistor to the fourth transistor.

[0018] According to a ninth aspect, the semiconductor device of the eighth aspect is characterized in that the first to fourth transistors are of a first conductivity type; the first current mirror circuit includes a fifth transistor of a second conductivity type having a drain and gate connected to the drain of the fir transistor in common, and a sixth transistor of the second conductivity type having a drain connected to the drain of the second transistor and having a gate connected to the gate of the fifth transistor, the output of the first detector is supplied from between the drains of the second and sixth transistors; the second current mirror circuit includes a seventh transistor of the second conductivity type having a drain and gate connected to the drain of the third transistor, and an eighth transistor of the second conductivity type having a drain connected to the drain of the fourth transistor and having a gate connected to the gate of the seventh transistor; the output of the second detector is supplied from between the drains of the fourth and eighth transistors; and the ratio of channel width of the third transistor to the fourth transistor is larger than the ratio of channel width of the first transistor to the second transistor.

[0019] According to a tenth aspect, the semiconductor device of the first aspect is characterized in that the first detector detects a deviation from the predetermined level of the internal potential, based on the result of a comparison of a first reference potential with an internal potential related potential related to the internal potential; and the second detector detects a deviation from the predetermined level of the internal potential, based on the result of a comparison of the internal potential related potential with a second reference potential having a different level from the first reference potential.

[0020] According to an eleventh aspect, the semiconductor device of the tenth aspect further comprises: a first reference potential generating circuit which includes a first constant current source connected between a power-supply node and a first node supplying the first reference potential, and a first resistor connected between the first node and ground; and a second reference potential generating circuit which includes a second constant current source connected between the power-supply node and a second node supplying the second reference potential, and a second resistor connected between the second node and ground, the second resistor having a higher resistance value than the first resistor.

[0021] According to a twelfth aspect, the semiconductor device of the first aspect is characterized in that the first detector detects a deviation from the predetermined level of the internal potential, based on the result of a comparison of a reference potential with a first internal potential related potential related to the internal potential; and the second detector detects a deviation from the predetermined level of the internal potential, based on the result of a comparison of the reference potential with a second internal potential related potential that is related to the internal potential and is different from the first internal potential related potential.

[0022] According to a thirteenth aspect, the semiconductor device of the twelfth aspect further comprises: a level shifter for performing level shifting of the internal potential to supply first and second shift potentials of different levels to the first and second detectors, respectively, the first and second internal potential related potentials including the first and second shift potentials.

[0023] According to a fourteenth aspect, the semiconductor device of the thirteenth aspect is characterized in that the level shifter includes a resistor disposed between the output node and ground; and the first and second shift potentials are supplied from the node of the output node side of the resistor and the node of the ground side, respectively.

[0024] An object of the present invention is to provide a semiconductor device of a low power consumption.

[0025] Another object of the present invention is to reduce a through current passing through a circuit in which an internal potential is generated by a charge pump.

[0026] These and other objects, features aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.

[0027] FIG. 1 is a block diagram of a DRAM according to a first preferred embodiment of the present invention;

[0028] FIG. 2 is a circuit diagram of a boost circuit on the DRAM of the first preferred embodiment;

[0029] FIG. 3 is a circuit diagram of a detector on the boost circuit of the first preferred embodiment;

[0030] FIG. 4 is a circuit diagram of a charge pump on the boost circuit of the first preferred embodiment;

[0031] FIG. 5 is a circuit diagram of an important part in the DRAM of the first preferred embodiment;

[0032] FIG. 6 is a circuit diagram of a subword driver in the DRAM of the first preferred embodiment;

[0033] FIG. 7 is a circuit diagram of a step-up converter in the DRAM of the first preferred embodiment;

[0034] FIG. 8 is a circuit diagram of a bit line separating signal generating circuit of the first preferred embodiment;

[0035] FIG. 9 is a circuit diagram of a boost circuit in a DRAM according to a second preferred embodiment;

[0036] FIG. 10 is a circuit diagram of a boost circuit in a DRAM according to a third preferred embodiment; and

[0037] FIG. 11 is a circuit diagram of a conventional boost circuit.

[0038] First Preferred Embodiment

[0039] A DRAM (dynamic random access memory) according to a first preferred embodiment will be described by referring to FIGS. 1 to 8. FIG. 1 is a schematic block diagram of a DRAM 100. Referring to FIG. 1, the DRAM 100 has a command decoder 110. The command decoder 110 latches a variety of control signals (e.g., clock enable signal CKE, chip select signal {overscore (CS)}, row address strobe signal {overscore (RAS)}, column address strobe signal {overscore (CAS)}, write enable signal {overscore (WE)}, and data mask signal DM) in synchronization with a clock signal CLK supplied from the exterior, and it decodes these control signals. An operation command is indicated by a logical combination of these control signals. Examples of commands are a bank activation command, read command, write command, precharge command, CBR refresh command, and self refresh command. The command decoder 110 decodes the supplied command and then outputs many kinds of internal control signals in order to control the operation of the DRAM 100 in response to the above command.

[0040] The DRAM 100 further comprises a row address buffer and refresh counter 120, which receives address signals A₀-A₁₂containing multiple bits and bank address signals BA₀-BA₁containing multiple bits, each being supplied from the exterior, and then outputs a row address signal and internal bank address signal. When the internal control signal from the command decoder 110 indicates that a bank activation command is supplied to the command decoder 110, the row address buffer and refresh counter 120 supplies the address signals A₀-A₁₂and bank address signals BA₀-BA₁as a row address signal and internal bank address signal, respectively.

[0041] When the internal control signal from the command decoder 110 indicates that a refresh command (e.g., CBR refresh command or self refresh command) is supplied to the command decoder 110, the row address buffer and refresh counter 120 for itself generates and supplies a row address signal and internal bank address, irrespective of the address signals A₀-A₁₂and bank address signals BA₀-BA₁supplied from the exterior.

[0042] The DRAM further comprises a column address buffer and latency/burst controller 130 which receives address signals A₀-A₁₂and bank address signals BA₀-BA₁, each being supplied from the exterior, and then outputs a column address signal and internal bank address signal. When the internal control signal from the command decoder 110 indicates that a read command or write command is supplied to the command decoder 110, the column address buffer and latency/burst controller 130 supplies the address signals A₀-A₁₂and bank address signals BA₀-BA₁, each being supplied from the exterior, as a column address signal and internal bank address signal, respectively.

[0043] When the internal control signal from the command decoder 110 indicates that a mode register set command is supplied to the command decoder 110, the column address buffer and latency/burst controller 130 sets {overscore (CAS)} latency in response to a predetermined bit (e.g., A₄-A₆) of the address signals A₀-A₁₂from the exterior, and sets a burst length in response to a predetermined other bit (e.g., A₀-A₂).

[0044] The DRAM 100 further comprises a plurality of banks 140 which are called bank A, B, C or D. Each bank has a memory array 141 in which a plurality of memory cells are disposed with multiple rows and multiple columns; row decoder 142 for selecting a row of the memory array 141; sense amplifier 143 for sensing and amplifying a memory cell data that is placed on a column of the memory array 141; and a column decoder 144 for selecting a column of the memory array 141. Each bank 140 is constructed so as to select a memory cell of an address independent of an address of a memory cell to be selected by other bank. Specifically, each bank can select any memory cell regardless of which memory cell is selected by other bank.

[0045] The row decoder 142 decodes a row address signal and internal bank address signal from the row address buffer and refresh counter 120, and selects a memory cell of the row in response to a row address signal (which is therefore also in response to the bank address signals A₀-A₁₂) of the bank 140 in response to the internal bank address signal (which is therefore also in response to the bank address signals BA₀-BA₁).

[0046] The sense amplifier 143 senses and amplifies the data of a memory cell on the row selected by the row decoder 142, which is placed on a column of the memory array 141. The column decoder 144 decodes a column address signal and internal bank address signal from the column address buffer and latency/burst controller 130. The column decoder 144 selects, from the data to be amplified by the sense amplifier 143, data at a row in response to a column address signal (which is therefore also in response to the address signals A₀-A₁₂) of the bank 140 in response to the internal bank address signal (which is therefore also in response to the bank address signals BA₀-BA₁).

[0047] The DRAM 100 further comprises a data controller and input/output buffer 150, from which data DQ is outputted from the memory array 141 to the exterior, in synchronization with a clock signal CLK, and in response to the internal control signal from the command decoder 110, and to the {overscore (CAS)} latency and burst length set to the latency/burst controller 130. Also, the data controller and input/output buffer 150 supplies the memory array 141 data DQ to be supplied from the exterior, in synchronization with a clock signal CLK, and in response to the internal control signal from the command decoder 110, and to the burst length set to the column address buffer and latency/burst controller 130.

[0048] When the internal control signal from the command decoder 110 indicates that a read command is provided to the command decoder 110, the data controller and input/output buffer 150 starts outputting of a read data DQ after an elapse of the cycle of a clock signal CLK corresponding to the value of {overscore (CAS)} latency after the read command is supplied. In read data outputting, an amount equivalent to a burst lenth is outputted serially to each of multiple (e.g., four) DQ pins. The data controller and input/output buffer 150 can serially output, to each DQ pin, the data from the memory array 141 selected by the column decoder 144.

[0049] When the internal control signal from the command decoder 110 indicates that a write command is provided to the command decoder 110, the data controller and input/output buffer 150 fetches therein sequentially a write data by an amount equivalent to a burst length to be supplied serially from the exterior to each DQ pin, in synchronization with a clock signal CLK, and then supplies the write data to a column of the memory array selected by the column decoder 144. Alternatively, it is possible to arrange so as not to fetch part of a write data provided serially from a data mask signal DM.

[0050] The DRAM 100 also has an internal potential generating circuit group 160 which outputs step-up potential V_PPobtained by setting up power-supply potential V_DD; the precharge potential V_BLof a bit line that is the intermediate potential, $\frac{\left(V_{\mathrm{DD}}+V_{\mathrm{SS}}\right)}{2},$

[0051] between the power-supply potential V_DDand V_SS; and a cell plate potential V_CP.

[0052] FIG. 2 is a circuit diagram illustrating the configuration of a boost circuit 161 contained in an internal potential generating circuit group 160. The boost circuit 161 is disposed per bank 140, for supplying step-up potential V_PP. Referring to FIG. 2, step-up potential V_PPis generated at an output node 161aby the boost circuit 161. The boost circuit 161 has step-up potential generating circuits 161band 161c.

[0053] The step-up potential generating circuit 161cnormally senses the level of step-up potential V_PPand, when the level lowers, executes the supply of step-up potential V_PP. The step-up potential generating circuit 161breceives an activation signal ACTL and, only when the signal ACTL indicates a high level indicating the active state, executes the supply of step-up potential V_PPwhen the step-up potential V_PPlowers. The activation signal ACTL becomes its high level in response to the activation indication of the corresponding bank 140. Accordingly, the step-up potential generating circuit 161bexecutes the supply of step-up potential V_PPwhen the corresponding bank 140 is activated in response to a bank activation command. The activation signal ACTL is provided from the command decoder 110 shown in FIG. 1.

[0054] The boost circuit 161 further comprises a reference potential generating circuit 161dfor generating reference potential V_REF, and a level shifter 161ethat supplies a shift potential V_SHFby performing level shifting of step-up potential V_PP.

[0055] The step-up potential generating circuit 161bhas a detector 161bathat detects the deviation from a predetermined level of step-up potential V_PP. The detector 161bareceives reference potential V_REFand shift potential V_SHF, compares these potentials, and outputs the comparison result based on the obtained deviation. The step-up potential generating circuit 161bfurther comprises a buffer circuit 161bbthat receives and buffers the output of the detector 161ba.The buffer circuit 161bbhas buffers BF₁, BF₂, and an inverter IV₁, which are connected in series. The input of the buffer BF₁receives the output of the detector 161ba. Each of the buffers BF₁and BF₂is formed by an even number of inverters connected in series. Here, the detector 161bamay be configured so as to compare step-up potential V_PPitself with the corresponding reference voltage.

[0056] The step-up potential generating circuit 161bfurther comprises a control circuit 161bcthat receives an activation signal ACTL and the output of the buffer circuit 161bb,and provides a clock enable signal EN₁. The control circuit 161bcincludes an AND gate AN that receives such two input signals. Alternatively, a logical circuit different from the AND gate may be added depending on the kind and number of input signals. The clock enable signal EN₁becomes disable (low level) regardless of the output of the buffer circuit 161bb,when an activation signal ACTL is inactive indicating a low level, and it becomes the level responsive to the output of the buffer circuit 161bbwhen the activation signal ACTL is active indicating a high level.

[0057] The step-up potential generating circuit 161bfurther comprises an oscillator 161bdthat oscillates a clock signal CK₁in response to a clock enable signal EN₁. The oscillator 161bdoscillates a clock signal CK₁when a clock enable signal EN₁is at its high level indicating the enable state, and reduces a clock signal CK₁to its low level when the signal is disable indicating a low level. The step-up potential generating circuit 161bfurther comprises a charge pump 161beby which a step-up potential V_PPis generated at an output node 161a,in response to a clock signal CK₁. The charge pump 161behas a high capability of supplying step up potential V_PP.

[0058] The step-up potential generating circuit 161chas a detector 161cathat detects the deviation from a predetermined level of step-up potential V_PP. The detector 161careceives reference potential V_REFand shift potential V_SHF, compares these potentials, and outputs the comparison result in accordance with the deviation. The detector 161cais ahead of the detector 161bain detecting the deviation from a predetermined level of step-up potential V_PP. That is, the detector 161cais ahead of the detector 161bain detecting a decrease in step-up potential V_PP. Here, the detector 161camay be configured so as to compare step-up potential V_PPitself with the corresponding reference voltage.

[0059] The step-up potential generating circuit 161cfurther comprises a buffer circuit 161cbthat receives the output of the detector 161caand buffers this output, thereby to supply a clock enable signal EN₂. The buffer circuit 161cbhas buffers BF₃, BF₄, and an inverter IV₂, which are connected in series. The input of the buffer BF₃receives the output of the detector 161ca. Each of the buffers BF₃and BF₄is formed by an even number of inverters connected in series.

[0060] The step-up potential generating circuit 161cfurther comprises an oscillator 161ccthat oscillates a clock signal CK₂in response to a clock enable signal EN₂. Since the clock signal CK₂is responsive

[0061] to the output of the detector 161ca,the oscillator 161ccoscillates a clock signal CK₂in response to the output of the detector 161ca.The oscillator 161ccoscillates a clock signal CK₂when a clock enable signal EN₂is enable indicating a high level and reduces a clock signal CK₁to its low level when the signal is disable indicating a low level.

[0062] The step-up potential generating circuit 161cfurther comprises a charge pump 161cdby which a step-up potential V_PPis generated at an output node 161ain accordance with a clock signal CK₂. The charge pump 161cdhas a low capability of supplying step-up potential V_PPbut has a low power consumption, than the charge pump 161be.In the DRAM 100, the specification of current consumption is defined in detail, according to the status of operation, such as the standby or active state. The presence of the charge pumps 161beand 161cdhaving different supply capabilities and different current consumption as described above, allows to adjust current consumption so as to conform to the specification. For instance, in the standby status requiring no large supply capability, current consumption can be reduced by stopping the operation of the charge pump 161be.

[0063] The level shifter 161ehas a resistor R₁connected between the output node 161aand node 161ea,and a resistor R₂connected between the node 161eaand ground 100a.Shift potential V_SHFis supplied from the node 161ea.The resistors R₁and R₂may be a resistor composed of polysilicon, or a channel resistor of the transistor. Shift potential V_SHFis derived as follows: $V_{\mathrm{SHF}}=\frac{\left(V_{\mathrm{PP}}-V_{\mathrm{SS}}\right)·r_2}{\left(r_1+r_2\right)+V_{\mathrm{SS}}}$

[0064] wherein the resistance value of the resistors R₁and R₂are r₁and r₂, respectively. In this preferred embodiment the resistors R₁and R₂are set so as to have a substantially equal value, and the ground potential V_SSis normally 0 V. Accordingly, the shift potential V_SHFis one half of step-up potential, that is, $\frac{V_{\mathrm{PP}}}{2}.$

[0065] FIG. 3 is a circuit diagram illustrating the configuration of the detectors 161baand 161cashown in FIG. 2. Referring now to FIG. 3, the detector 161bacomprises a current mirror circuit CM₁, and n-channel MOS transistors NT₁and NT₂connected to the current mirror circuit CM₁. The n-channel MOS transistors NT₁and NT₂receive at their respective gates shift potential V_SHFand reference potential V_REF. The detector 161bafurther comprises an n-channel MOS transistor NT₃which receives at its gate a bias potential BIAS falling in between power-supply potential V_DDand ground potential V_SS. The drain of the n-channel MOS transistor NT₃is connected in common to the respective sources of the n-channel MOS transistors NT₁and NT₂. The source of the n-channel MOS transistor NT₃is connected to ground 100a.

[0066] The current mirror circuit CM₁comprises a p-channel Resistor PT₁which has a drain and gate connected to the drain of the n-channel MOS transistor NT₁. The source of the p-channel MOS transistor PT₁is connected to the power-supply node 100b.The current mirror circuit CM₁further comprises a p-channel transistor PT₂which has a drain connected to the drain of the n-channel MOS transistor NT₂. The p-channel MOS transistor PT₂has a gate connected to the gate of the p-channel MOS transistor PT₁. The source of the p-channel MOS transistor PT₂is connected to the power-supply node 100b.The output of the detector 116bais supplied from a node ND₁disposed between the p-channel MOS transistor PT₂and n-channel MOS transistor NT_2.

[0067] The detector circuit 161cacomprises a current mirror CM₂, and n-channel MOS transistors NT₄and NT₅connected to the current mirror circuit CM₂. The n-channel MOS transistors NT₄and NT₅receive at their respective gates shift potential V_SHFand reference potential V_REF. The detector 161cafurther comprises an n-channel MOS transistor NT₆which receives at its gate a bias potential BIAS. The drain of the n-channel MOS transistor NT₆is connected in common to the respective sources of the n-channel MOS transistors NT₄and NT₅. The source of the n-channel MOS transistor NT₆is connected to the ground 100a.

[0068] The current mirror circuit CM₂comprises a p-channel transistor PT₃which has a drain and gate connected to the drain of the n-channel MOS transistor NT₄. The source of the p-channel MOS transistor PT₃is connected to the power-supply node 100b.The current mirror circuit CM₂further comprises a p-channel transistor PT₄which has a drain connected to the drain of the n-channel MOS transistor NT₅. The p-channel MOS transistor PT₄has a gate connected to the gate of the p-channel MOS transistor PT₃. The source of the p-channel MOS transistor PT₄is connected to the power-supply node 100b.The output of the detector 161cais supplied from a node ND₂disposed between the p-channel MOS transistor PT₄and n-channel MOS transistor NT_5.

[0069] It is set so that the n-channel MOS transistor NT₅has a larger current drive capability than the n-channel MOS transistor NT₄. It is also set so that the ratio of the current drive capability of the channel MOS transistor NT₅to the channel MOS transistor NT₄is higher than the ratio of the current drive capability of the channel MOS transistor NT₂to the channel MOS transistor NT_1.

[0070] The current drive capability depends on μ·W/L, wherein μ is the mobility of electrons; W is the channel width of a transistor; and L is the channel length of the transistor. Therefore, the current drive capability is adjustable by changing the doping amount of impurity ions to the channel. Alternatively, the current drive capability can be increased by increasing the channel width W, or decreasing the channel length L. In this preferred embodiment, it is so designed that all the n-channel transistors NT₁, NT₂, NT₄and NT₅have the same mobility of electrons and the same channel length, and that a difference in current drive capability is produced by changing the channel width.

[0071] Specifically, in this embodiment the channel width W₄of the n-channel MOS transistor NT₅is greater than the channel width W₃of the n-channel MOS transistor NT₄. The ratio of the channel width W₄of the n-channel MOS transistor NT₅to the channel width W₃of the n-channel MOS transistor NT₄(i.e., W₄/W_{3,) is greater than the ratio of the channel width W2}of the n-channel MOS transistor NT₂to the channel width W₁of the n-channel MOS transistor NT₁(i.e., W₂/W₁). In this embodiment it is especially designed for W₁=W₂=W₃<W₄. The channel width W₄of the n-channel MOS transistor NT₅can be increased merely by increasing the channel width of a single transistor. Alternatively, it is possible to increase the channel width by connecting in parallel two transistors having the same channel width.

[0072] In the detector 161ba,the n-channel MOS transistors NT₁and NT₂have the same current drive capability and the same volt-ampere characteristic. Accordingly, the detector 161baoutputs a low level signal to the node ND₁when the shift potential V_SHFis lower than the reference potential V_REF. On the other hand, in the detector 161ca,the n-channel MOS transistor NT₅has a larger current drive capability than the n-channel MOS transistor NT₄, and therefore, the detector 161caoutputs a low level signal to the node ND₂under conditions where shift potential V_SHFis slightly higher than reference potential V_REF. That is, the detector 161caoutputs a low level signal before shift potential V_SHFis reduced to reference potential V_REF.

[0073] Thus, the detector 161cacan be ahead of a detector 161bain detecting a decrease in step-up potential V_PP, by allowing the transistors to have different current drive capabilities. As a result, when an activation signal ACTL is at its low level, the output of the detector 161bareaches its high level. This permits a reduction in the through current passing through the buffer circuit 161bb.Even when an activation signal ACTL is at its high level, the charge pump 161beis not required to operate by arranging so that the detector 161cais ahead in detecting a decrease in step-up potential V_PP, and the charge pump 161cdoperates to increase the step-up potential V_PP. It is therefore possible to reduce power consumption by the amount that the charge pump 161bedoes not operate which has a large capability of supplying step-up potential V_PPbut requires a large power consumption.

[0074] FIG. 4 is a circuit diagram illustrating the configuration of the charge pumps 161beand 161cdshown in FIG. 2. Referring to FIG. 4, the charge pump 161becomprises a boost capacitor BC₁which receives at one electrode a clock signal CK₁. The capacitance value of the boost capacitor BC₁determines the magnitude of the capability of supplying step-up potential V_PP. The charge pump 161behas a large supply capability because it is designed so that the boost capacitor BC₁has a high capacitance value. This, however, increases the amount of power consumed when the boost capacitor BC₁is charged or discharged.

[0075] The charge pump 161befurther comprises a driver transistor NT₇connected between the other electrode of the boost capacitor BC₁and an output node 161a.The driver transistor NT₇is formed by an n-channel MOS transistor in which a gate is connected to the other electrode of the boost capacitor BC₁. The charge pump 161befurther comprises a charging transistor NT₈connected between the other electrode of the boost capacitor BC₁and a power-supply node 100b.The charging transistor NT₈is formed by an n-channel MOS transistor in which a gate is connected to the power-supply node 100b.

[0076] The charge pump 161cdcomprises a boost capacitor BC₂which receives at one electrode a clock signal CK₂. Since it is designed so that the boost capacitor BC₂has a smaller capacitance value than the boost capacitor BC₁, the charge pump 161cdhas a smaller supply capability than the charge pump 161be,but less power is consumed when the boost capacitor BC₂is charged or discharged.

[0077] The charge pump 161cdfurther comprises a driver transistor NT₉connected between the other electrode of the boost capacitor BC₂and the output node 161a.The driver transistor NT₉is formed by an n-channel MOS transistor in which a gate is connected to the other electrode of the boost capacitor BC₂. The charge pump 161cdfurther comprises a charging transistor NT₁₀connected between the other electrode of the boost capacitor BC₂and the power-supply node 100b.The charge transistor NT₁₀is formed by an n-channel MOS transistor in which a gate is connected to the power-supply node 100b.

[0078] Modification may be made in this preferred embodiment, such as transposing shift potential V_SHFand reference potential V_REFto be inputted to the detectors 161baand 161ca,respectively. In this case, since the output logical of the detectors 161baand 161cais reversed, there is no need to provide inverters IV₁and IV₂on their respective buffer circuits 161bband 161cb.The n-channel MOS transistors in the detectors 161baand 161cahave a channel width relationship of W₃>W₄and W₄/W₃<W₂/W_1.

[0079] Description will now be made of the intended use of step-up potential V_PPgenerated by a boost circuit 161. FIG. 5 is a circuit diagram illustrating in part the memory array 141, row decoder 142 and sense amplifier 143, which are shown in FIG. 1. The memory array 141 is divided into a plurality of memory blocks MB_i(i=0-15), part of which is omitted in FIG. 5. Sense amplification bands SB_j(j=0-16) are provided at opposite sides so as to sandwich the respective memory blocks MB_i. The sense amplification band SB_jare contained in the sense amplifier 143 of FIG. 1. A sense amplification band SB_x+1disposed between memory blocks MB_xand MB_x+1(x=0-14) is common to two adjacent both memory blocks MB_xand MB_x+1. That is, a so-called shared sense amplification configuration is employed in the DRAM 100.

[0080] Each memory block MB_ihas a plurality of memory cells 141awhich are avenged with multiple rows and multiple columns. Each memory block MB_iis divided into memory sub-blocks MSB_k(k=0-15) which have a plurality of columns of the memory cells 141a(only MSB₀is shown in FIG. 5). Each memory sub-blocks MSB_kcomprises a plurality of subword lines 141bthat are provided so as to correspond to their respective rows of the memory cells 141a.Each subword line 141bis connected to the memory cell 141aat the corresponding row. Each memory sub-blocks MSB_kfurther comprises a plurality of paired bit lines 141c(BL, {overscore (BL)}) which are provided so as to correspond to their respective rows of the memory cells 141a.Each of the paired bit lines 141cis connected to the memory cell 141aat the corresponding column.

[0081] Each memory cell 141acomprises a memory capacitor CP which receives at one electrode a cell plate potential V_CP, and a memory transistor TR which is connected between the other electrode of the memory capacitor CP and a bit line BL or {overscore (BL)} forming the paired bit lines 141c, and is formed by an n-channel MOS transistor in which a gate is connected to the subword line 141b.

[0082] In addition, a plurality of main word lines 141dare provided in common to the multiple memory sub-blocks MSB_kin each memory block MB_i. The main word lines 141dand subword lines 141bextend in the row direction, and the paired bit lines 141cextend in the column direction. Four subword lines 141bin each memory sub-block MSB_kcorrespond to a single main word line 141d.

[0083] A plurality of subword drivers 142aconnected to their respective subword lines 141bare disposed at opposite sides so as to sandwich the corresponding memory sub-blocks MSB_k. The subword drivers 142aare contained in the row decoder 142 shown in FIG. 1. Each subword driver 142asupplies step-up potential V_PPto the corresponding subword line 141b,in response to a main word signal MWL_m(m=0-127) transmitted from the corresponding main word line 141d, and to a row decode signal X_n⁺(n=0, 1, 2, or 3; and “+” indicates that it becomes step-up potential V_PPhigher than power-supply potential V_DD) which accords with an address signal. That is, the step-up potential V_PPis utilized to step up the selected subword line 141b. In response to an address signal, the row decoder 142 of FIG. 1 selects one from 128 main word lines 141d, and reduces a main word signal MWL_mto its low level, which is then supplied to the selected main word line 141d.

[0084] Each sense amplification band SB_jcomprises a power-supply line 143ato which power-supply potential V_DDis supplied; a power-supply line 143bto which ground potential V_SSis supplied; a common source line 143c; a common source line 143d; and a precharge potential line 143efor remitting a bit line precharge potential V_BL. The sense amplification band SB_jfurther comprises a p-channel MOS transistor 143fthat charges the common source line 143cto power-supply potential V_DD, in response to a sense amplification enable signal {overscore (PSE)}; and an n-channel MOS transistor 143gthat discharges the common source line 143dto ground potential V_SS, in response to a sense amplification enable signal NSE_j.

[0085] Each sense amplification band SB_jfurther comprises a plurality of sense amplifiers 143hby which a potential difference of the paired bit lines 141cis amplified so that the potential of one bit line becomes power-supply potential V_DDand the potential of the other becomes ground potential V_SS. Each sense amplifier 143hcomprises p-channel MOS transistors PT₅and PT₆connected to a cross couple, by which either a bit line BL or {overscore (BL)} having a higher potential is amplified up to power-supply potential V_DD; and n-channel MOS transistors NT₁₁and NT₁₂connected to a cross couple, by which either a bit line BL or {overscore (BL)} having a lower potential is amplified up to ground potential V_SS. To the sense amplifier 143h,power-supply potential V_DDand ground potential V_SSare provided from the power-supply lines 143aand 143b.

[0086] Each sense amplification band SB_jfurther comprises a bit line precharge/equalizing circuit 143ithat equalizes/precharges the potential of a bit line BL or {overscore (BL)}, in response to a bit line equalizing signal BLEQ_j. The bit line precharge/equalizing circuit 143icomprises an n-channel MOS transistor NT₁₃for equalizing the potential of a bit line BL or {overscore (BL)}, in response to a bit line equalizing signal BLEQ_j; and n-channel MOS transistors NT₁₄and NT₁₅for precharging the potential of a bit line BL or {overscore (BL)}, in response to a bit line equalizing signal BLEQ_j.

[0087] Each sense amplification band SB_jfurther comprises a separated gate circuit 143jconnected between the paired bit lines 141cand sense amplifier 143h.The separated gate circuit 143hincludes n-channel MOS transistors NT₁₆and NT₁₇arranged in pairs, each having a gate that receives a bit line isolation signal BLI_2j-1or BLI_2j. The bit line isolation signals BLI_2j−1and BLI_2jbecome step-up potential V_PPor ground potential V_SSin response to an address signal. That is, the step-up potential V_PPis utilized to step up the bit line isolation signals BLI_2j−1and BLI_2j. In response to a bit line isolation signal BLI_2j−1or BLI_2j, each gate isolation circuit 143jisolates the corresponding paired bit lines 141cfrom the sense amplifier 143hand bit line precharge/equalizing circuit 143i.

[0088] Each sense amplification band SB_jfurther comprises a data bus 143khaving paired data bus lines, by which data is transmitted from the memory any 141; and a data transfer circuit 143mhaving n-channel MOS transistors NT₁₈and NT₁₉, by which the paired bit lines 141cand data bus 143kare selectively connected together, in response to a column selection signal CSL_p(p=0, 1, . . . ).

[0089] Each sense amplification band SB_jfurther comprises a common source line precharge/equalizing circuit 143nthat precharges/equalizes the potential of common source lines 143cand 143d, in response to a bit line equalizing signal BLEQ_j. The common source line precharge/equalizing circuit 143nfurther comprises an n-channel MOS transistor NT₂₀for equalizing the potential of the source lines 143cand 143d, in response to a bit line equalizing signal BLEQ_j; and n-channel MOS transistors NT₂₁and NT₂₂that precharge the potential of the common source lines 143cand 143dup to bit line precharge potential V_BL; in response to a bit line equalizing signal BLEQ_j.

[0090] FIG. 6 is a circuit diagram illustrating an example of a subword driver 142a. Referring to FIG. 6, the subword driver 142acomprises a p-channel MOS transistor PT₇connected between a row decode signal line 142band subword line 141b. The p-channel MOS transistor PT₇has a gate that receives a main word signal MWL_mtransmitted from the main word line 141d. The back gate of the p-channel MOS transistor PT₇receives step-up potential V_PP.

[0091] The subword driver 142afurther comprises an n-channel MOS transistor NT₂₃which is connected between a subword line 141band ground 100a, and has a gate for receiving a main word signal MWL_mtransmitted from the main word line 141d; and an n-channel MOS transistor NT₂₄which is connected between a subword line 141band ground 100a, and has a gate for receiving the reverse signal {overscore (X_n+L )}, of a row decode signal X_a⁺ (the reverse signal has V_DD-V_SSamplitude, unlike V_PP-V_SSamplitude in X_n⁺).

[0092] FIG. 7 is a circuit diagram of a step-up converter 142cfor generating a row decode signal X_n⁺. Referring to FIG. 7, the soup converter 142ccomprises a p-channel MOS transistor PT₈connected between an output node 161aof a boost circuit 161 and a row decode signal line 142b; and an n-channel MOS transistor NT₂₅connected between the row decode signal line 142band ground 100a. The gate of the n-channel MOS transistor NT₂₅is connected to the gate of the p-channel MOS transistor PT₈.

[0093] The step-up converter 142cfurther comprises a p-channel MOS transistor PT₉that is connected between the output node 161a,and the gate of the n-channel MOS transistor NT₂₅and p-channel MOS transistor PT₈; and an n-channel MOS transistor NT₂₆that is connected between the input receiving a row decode signal {overscore (X_n+L )}, and the gate of the n-channel MOS transistor NT₂₅and p-channel MOS transistor PT₈. The gate of the n-channel MOS transistor NT₂₆is connected to the power-supply node 100b.

[0094] In accordance with a low 2-bit of a row address signal, one of row decode signals {overscore (X_n+L )} becomes its low level. The step-up converter 142 receiving a row decode signal {overscore (X_n+L )} of a low level converts the corresponding row decode signal X_n⁺ to step-up potential V_PP. The row decode signal X_n⁺ stepped up by using the step-up potential V_PPis then supplied to the subword line 141bby the subword driver 142a.

[0095] FIG. 8 is a circuit diagram illustrating the configuration of a bit line isolation signal generating circuit 142d. A bit line isolation signal BLI is generated, based on a block selection signal BS, by a similar circuit to the step-up converter 142cshown in FIG. 7. The correspondence relationships are as follows: signals BS_jand BS_j−1correspond to signals {overscore (X_n+L )}; signals BLI_2j−1and BLI_2jcorrespond to signal X_n⁺; p-channel MOS transistors PT₁₈and PT₁₉, and PT₂₈and PT₂₉correspond to PT₈and PT₉; and n-channel MOS transistors NT₁₂₅and NT₁₂₆, and NT₂₂₅and NT₂₂₆correspond to NT₂₅and NT₂₆, respectively. In response to a row address signal, one of the block selection signals BS becomes its high level. Two bit line separation signals BLI corresponding to the high level block selection signal become their low level. The remaining bit line isolation sins are stepped up by using step-up potential V_PP, and then supplied to the gate isolation circuit 143jshown in FIG. 5. For instance, when a block selection signal BS_jbecomes its high level, bit line isolation signals BLI_2j−1and BLI_2j+2become their low level. When a block selection signal BS_j−1becomes its high level, bit line isolation signals BLI_2j−3and BLI_2jbecome their low level. For the sake of convenience, FIG. 8 merely shows part of the bit line isolation signal BLI_2j−1to be controlled by the block selection signal BS_j, and part of the bit line isolation signal BLI_2jto be controlled by the block selection signal BS_j−1.

[0096] Second Preferred Embodiment

[0097] A DRAM according to a second preferred embodiment will now be described by referring to FIG. 9. This DRAM differs from the DRAM of the first preferred embodiment in the configuration of a boost circuit 161. In the foregoing embodiment, a common reference potential V_REFis supplied to the detectors 161baand 161ca,and the detector 161cais ahead of the detector 161bain detecting a decrease in step-up potential V_PP, by adjusting the channel width of the transistors in the detectors 161baand 161ca.In the second preferred embodiment, detectors 161baand 161caare configured as shown in FIG. 3, and the channel widths W₁, W₂, W₃and W₄of their respective n-channel MOS transistors NT₁, NT₂, NT₃and NT₄are all the same.

[0098] In the second preferred embodiment, the detector 161cais ahead of the detector 161bain detecting a decrease in step-up potential V_PP, with the configuration that reference potentials V_REFLand V_REFSare supplied to both detectors 161baand 161ca,and the reference potential V_REFSis made higher than V_REFL. Other circuit configurations are the same as the first preferred embodiment. Therefore, its description is omitted herein, and only different parts will be described hereafter. As another configuration, detectors 161baand 161camay compare step-up potential V_PPitself with its corresponding first and second reference potentials.

[0099] Referring to FIG. 9, a reference potential generating circuit 161dsupplies the detector 161careference potential V_REFShigher than reference potential V_REFL. The reference potential generating circuit 161dcomprises a reference potential generating circuit 161dagenerating reference potential V_REFL, and a reference potential generating circuit 161dbgenerating reference potential V_REFS. The reference potential generating circuit 161dahas a constant current source CS₁that is connected between a power-supply node 100b, and a node ND₃from which reference potential V_REFLis supplied; and a resistor R₃connected between the node ND₃and ground 100a.

[0100] The reference potential generating circuit 161dbcomprises a constant current source CS₂connected between the power-supply node 100b,and a node ND₄from which reference potential V_REFSis supplied; and a resistor R₄connected between the node ND₄and ground 100aThe resistor R₄has a higher resistance value than the resistor R₃, thereby supplying reference potential V_REFShigher than reference potential V_REFL. That is, the detector 161cacan be ahead of the detector 161bain detecting a decrease in step-up potential V_PP. As a result, like the first preferred embodiment, when an activation signal ACTL is at its low level, the output of the detector 161babecomes its high level, thereby to reduce a through current passing through a buffer circuit 161bb.

[0101] Even when an activation signal ACTL is at its high level, the charge pump 161bcis not required to operate by arranging so that the detector 161cais ahead in detecting a decrease in step-up potential V_PP, and a charge pump 161cdoperates to increase the step-up potential V_PP. This enables to reduce power consumption by the amount that the charge pump 161 be requiring a large power consumption does not operate.

[0102] Further, different reference potentials V_REFSand V_REFLdescribed in the second embodiment can be applied to the configuration with different channel widths described in the first embodiment.

[0103] Third Preferred Embodiment

[0104] A DRAM according to a third preferred embodiment will now be described by referring to FIG. 10. This DRAM differs from the DRAM of the second preferred embodiment in the configuration of a boost circuit 161. In the second embodiment, reference potentials V_REFSand V_REFL, and common shift potential V_SHFare supplied to both detectors 161baand 161ca.Whereas in the third preferred embodiment, common reference potential V_REFis used as a reference potential supplied to detectors 161baand 161ca,as in the first preferred embodiment.

[0105] In the third preferred embodiment, the detector 161cais ahead of the detector 161bain detecting a decrease in step-up potential V_PP, with the configuration that both shift potentials V_SHFLand V_SHFSare supplied to the detectors 161baand 161ca,and the shift potential V_SHFSis lower than V_SHFL. Other circuit configurations are the same as the second preferred embodiment Therefore, its description is omitted herein, and only different parts will be described hereafter.

[0106] Referring to FIG. 10, a level shifter 161esupplies the detector 161cashift potential V_SHFSlower than shift potential V_SHFL.The level shifter 161dcomprises a resistor R₅disposed between an output node 161aand ground 100a.The shift potential V_SHFLis supplied from an end ND₅on the output node 161aside of the resistor R₅. The shift potential V_SHFSis supplied from an end ND₆on the ground 100aside. The level shifter 161efurther comprises a resistor R₆connected between the output node 161aand resistor R₅; and a resistor R₇connected between the ground 100aand resistor R₅.

[0107] Thus, the shift potential V_SHFSlower than the shift potential V_SHFLcan be supplied by utilizing a voltage drop of the resistor R₅. Thereby, the detector 161cacan be ahead of the detector 161bain detecting a decrease in step-up potential V_PP. Accordingly, as in the first and second preferred embodiments, when an activation signal ACTL is at its low level, the output of the detector 161babecomes its high level, thereby to reduce a through current passing through the buffer circuit 161bb.

[0108] Even when an activation signal ACTL is at its high level, the charge pump 161beis not required to operate by arranging so that the detector 161cais ahead in detecting a decrease in step-up potential V_PP, and the charge pump 161cdoperates to increase the step-up potential V_PP. This enables to reduce power consumption by the amount that the charge pump 161berequiring a large power consumption does not operate.

[0109] As stated above, the present invention has the effect of reducing power consumption.

[0110] While the invention has been shown and described in detail, the foregoing description is in all aspects illustrative and not restrictive. It is therefore understood that numerous modifications and variations can be devised without departing from the scope of the invention.