Switching DC-to-Dc converter having on-time signal generation circuit and method for generating signal indicative of converter on-time

[0002] 1. Field of the Invention

[0003] The present invention relates to switching controllers for use in switching DC-to-DC converters, in which the duty cycle of each power channel is controlled by a pulse width modulated control signal. More specifically, the invention is a method and circuit for generating a train of pulses whose width is indicative of the nominal power switch on-time needed to produce a DC output potential V_outin response to a DC input potential V_in. The pulse train is useful in a switching controller for a DC-to-DC converter.

[0004] 2. Description of the Related Art

[0005] For convenience, we will use the expression “switching controller” chip below to denote either a controller (implemented as an integrated circuit) which generates power switch control signals for at least one power switch implemented external to the chip (typically multiple power switches, each implemented external to the chip), or a switching “regulator” (implemented as an integrated circuit) which generates such power switch control signals and which also includes at least one power switch implemented on-board the chip (typically multiple power switches, each implemented on-board the chip ). The power switches are typically MOSFET devices.

[0006] One type of conventional switching power supply which employs current mode control to achieve output voltage regulation is a DC-to-DC converter including a current mode switching controller chip, and circuitry external to the controller chip which defines one or more power channels (e.g., multiple paralleled power channels). Each power channel includes an inductor and at least one power switch. The controller chip includes a control signal channel for each power channel. Each control signal channel generates a pulse width modulated power switch control signal in response to a feedback signal (a ramped voltage) indicative of the current through the channel's inductor, and a second feedback signal indicative of the DC-to-DC converter's output potential. This allows control of the time-averaged duty cycle of each of the channel's power switches. Typically, a ramped voltage (internally generated in the controller chip) adjusts the effective ramp rate slightly for improved stability through a technique called “slope compensation.” The adjusted feedback signal (e.g., one whose value is the difference between the second feedback signal and the internally generated ramped voltage) controls the peak value to which the inductor is allowed to ramp up. Also typically, each pulse width modulated power switch control signal is a binary signal having periodically occurring leading edges, and trailing edges which occur at times determined by the instantaneous value of the feedback signal.

[0007] Some DC-to-DC converters include a current mode switching controller chip and buck converter circuitry external to the controller chip. The buck converter circuitry comprises an NMOS transistor (which functions as a power switch, and has a drain coupled to the DC-to-DC converter's input node), an inductor and a current sense resistor (connected in series with the channel of the NMOS transistor), a Schottky diode (coupled between ground and the source of the NMOS transistor), an output capacitor coupled between ground and the output node, and a feedback resistor divider coupled between ground and the output node.

[0008] In order to generate a pulse width modulated power switch control signal in response to feedback (or in response to a DC signal which corresponds to a desired DC-to-DC converter output potential V_out), it would be desirable for DC-to-DC converter switching controller chips (of many different types) to include circuitry for generating a train of pulses whose width is indicative of the nominal power switch on-time needed to produce a DC output potential V_outin response to a DC input potential V_in. It would be especially useful for the circuitry to do so in an accurate manner, independently of process variations (i.e., variations in the manufactured characteristics of integrated circuits produced using the same design) and variations in operating temperature.

[0009] In a class of embodiments, the invention is an on-time signal generation circuit for use in a switching DC-to-DC converter. The on-time generation signal circuit includes a comparator, a ramp generator (whose output is coupled to one input of the comparator), and an amplifier (whose output is coupled to the other input of the comparator). The ramp generator is configured to generate a periodic ramped potential having peak level kV_inand period T_osc, where Vin is the input potential of a DC-to-DC converter and T_OSCis the DC-to-DC converter's switching period. Preferably, the ramp generator includes a transconductance amplifier having an input coupled to receive the input potential V_inof the DC-to-DC converter and configured to assert a current I2 (where I2=gm₂(V_in)=V_in/R2), ramp generation circuitry (including a capacitor and a switch coupled to periodically discharge the capacitor), and an oscillator coupled and configured to assert control signals to the switch for periodically discharging the switch with period T_OSC.

[0010] The amplifier has an input coupled to receive a DC potential V_out, where V_outis the DC-to-DC converter's output potential or a DC signal which corresponds to a desired level for the DC-to-DC converter's output potential (i.e., a DC potential which is proportional to a desired level for the DC-to-DC converter's output potential with a proportionality constant that can but need not equal one), and is configured to assert an amplified potential kV_outin response thereto, where k is the same coefficient as in the peak level kV_inof the ramped voltage produced by the ramp generator. In response to potential kV_outfrom the amplifier and the ramped voltage kV_in, from the ramp generator, the comparator asserts a binary pulse train comprising pulses T_ON. The leading edges of pulses T_ONoccur with period T_OSC. The trailing edge of each pulse T_ONoccurs when ramped voltage kV_inrises to a level matching kV_out. Thus, the width of each pulse T_ONis equal to T_OSC(V_out/V_in), and the width of each pulse T_ONis indicative of the nominal (or critical) power switch on-time needed for the DC-to-DC converter (in the case that it is a step down DC-to-DC converter) to produce output potential V_out(during steady-state operation) in response to input potential V_in.

[0011] Preferably, the on-time signal generation circuit is implemented so that the width of each pulse T_ONis accurately equal to T_OSC(V_out/V_in), independently of process variations and variations in operating temperature. Preferably, the width of each pulse T_ONis caused to be equal to T_OSC(V_out/V_in), independently of operating temperature, by implementing the ramp generator and amplifier so that the factor “k” in the peak level kV_in, of the ramped voltage (produced by the ramp generator) is equal to k=(C1/C2)(R3/R2), where C1 and C2 are the capacitances of periodically discharged capacitors in the ramp generator and R3 and R2 are resistances of resistive elements in the ramp generator.

[0012] Preferably also, the ramp generator of the on-time signal generation circuit includes circuitry for compensating for the delay time of the comparator. In a preferred implementation, the ramp generator includes a transconductance amplifier configured to assert a current I2=gm₂(V_in)=V_in/R2, ramp generation circuitry (including a current multiplying circuit having an input which receives current I2 and an output (coupled to a first input of the comparator) which asserts a current I4 which is proportional to 12, a capacitor which is charged by the output current of the current multiplying circuit, and a switch coupled to periodically discharge the capacitor with period T_OSC), an oscillator coupled and configured to assert control signals for periodically discharging the switch with period T_OSC, and a resistor R5 between the current multiplying circuit and the top plate of the capacitor. Thus, the potential at the top plate of the capacitor is a periodic ramped potential having period T_OSCand peak potential Vpeak=k(V_in), and the potential at the first input of the capacitor is such periodic ramped potential plus an offset potential I4R5. Where k=(Cl/C2)(R3/R2), the offset potential I4R5 is equal to I1(V_in/V_ref)(R3/R2)R5. Since the offset potential I4R5 is proportional to V_in, it desirably provides a greater degree of compensation for comparator delay time when V_inis greater, causing the error (in the width of pulse T_ON) due to the comparator delay time to be relatively greater than for smaller values of V_in. In typical implementations of the comparator, the comparator delay time has a positive temperature coefficient. Since I4 has no significant temperature coefficient, and R5 has a positive temperature coefficient, the offset potential I4R5 desirably varies with temperature in a manner compensating for changes (due to temperature changes) in the comparator delay time.

[0013] In another class of embodiments, the invention is a switching DC-to-DC converter including any embodiment of the inventive on-time signal generation circuit.

[0014] Another aspect of the invention is a method for generating an on-time signal which is a binary pulse train comprising pulses T_ON, where the width of each pulse T_ONis equal to T_OSC(V_out/V_in), where T_OSC, V_out, and V_inin are, respectively, the switching period, the output potential (or a DC potential which corresponds to a desired level for the output potential), and the input potential of a DC-to-DC converter. The method includes the steps of: (a) in response to the input potential (V_in) of the DC-to-DC converter, generating a periodic ramped potential having peak level kV_in+V_offsetand period T_osc, where V_offsetis optionally equal to zero; (b) in response to a potential V_out(where V_outis the output potential, or a DC potential which corresponds to a desired level for the output potential, of the DC-to-DC converter), generating an amplified potential kV_out, where k is the same coefficient as in the peak level of the periodic ramped voltage; and (c) generating the binary pulse train by comparing the periodic ramped potential with the amplified potential. Preferably, step (c) includes the step of asserting the periodic ramped potential to a first input of a comparator (said comparator having an output) while asserting the amplified potential to another input of the comparator, thereby causing the comparator to produce the binary pulse train at the output.

[0015] In some embodiments, step (a) includes the steps of: receiving the input potential of the DC-to-DC converter at an input of a transconductance amplifier to cause the transconductance amplifier to assert a current I2 (where I2=gm₂(V_in)=V_in/R2); employing circuitry to multiply the current I2 by a ratio I1/I3 (determined by reference currents I1 and I3 which are generated by the circuitry) to generate a second current I4=(I1)(I2)/I3=I1(V_in/Vref)(R3/R2), where Vref is a reference potential and R3 is a resistance of said circuitry; and asserting the second current I4 to a capacitor to charge the capacitor while periodically discharging the capacitor (with period T_OSC).

[0016] Preferably, step (a) generates the periodic ramped potential in a manner that compensates for a delay time of the comparator. This is accomplished in embodiments in which the offset potential V_offsetis equal to I4R5, where I4 is a current and R5 is a resistance, and step (a) includes the steps of: receiving the input potential of the DC-to-DC converter at an input of a transconductance amplifier to cause the transconductance amplifier to assert a current I2 equal to gm₂(V_in)=V_in/R2; employing circuitry to multiply the current I2 by a ratio I1/I3 (determined by reference currents I1 and I3 which are generated by the circuitry) to generate the current I4 such that said current is equal to I4=(I1)(I2)/I3=I1(V_in/Vref)(R3/R2), where Vref is a reference potential and R3 is a resistance of said circuitry, wherein the circuitry includes a resistive element having said resistance R5; and asserting the current I4 through said resistive element to a capacitor (to charge the capacitor) while periodically discharging the capacitor (with period T_OSC), thereby producing a periodic ramped potential across the capacitor having period T_OSCand peak potential k(V_in)+I4R5.

[0017] Preferably, step (a) includes the step of operating ramp generation circuitry to generate the periodic ramped potential, wherein the ramp generation circuitry is configured so that the factor “k” in the peak level kV_inof the periodic ramped potential is equal to k=(C1/C2)(R3/R2), where C1 and C2 are the capacitances of periodically discharged capacitors of the circuitry and R3 and R2 are resistances of resistors in said circuitry.

[0018] FIG. 1 is a block diagram of an embodiment of the inventive on-time generation circuit, for use in the switching controller of a DC-to-DC converter.

[0019] FIG. 2 is a block diagram of a preferred embodiment of circuit 1 of FIG. 1.

[0020] FIG. 3 is a block diagram of a preferred embodiment of the inventive circuitry, including circuits 3 and 2 of FIG. 1 and a variation on elements 16, C2, and Q4 of FIG. 2.

[0021] FIG. 4 shows waveforms of signals asserted at the noninverting input of comparator 2 of the FIG. 3 circuit (assuming both zero and nonzero values of resistor R5) and at the output of such comparator.

[0022] FIG. 5 shows waveforms of signals asserted at the noninverting input of comparator 2 of the FIG. 3 circuit (assuming both zero and nonzero values of resistor R5) and at the output of such comparator.

[0023] FIG. 6 is a simplified schematic diagram of a preferred embodiment of a DC-to-DC converter whose controller includes the inventive on-time generation circuit.

[0024] An embodiment of the inventive on-time generation circuit, for use in the switching controller of a DC-to-DC converter, will be described with reference to FIG. 1. The FIG. 1 circuit includes comparator 2, ramp generator 1 (whose output is coupled to one input of comparator 2), and amplifier 3 (whose output is coupled to the other input of comparator 2).

[0025] Ramp generator 1 includes oscillator 4, transconductance amplifier 5, and ramp generation circuitry 6. Transconductance amplifier 5 has an input coupled to receive the input potential (V_in) of a DC-to-DC converter, and an output which asserts current I2=gm₂(V_in)=V_in/R2 to circuitry 6. In response to this amplified potential (and to a train of periodic control pulses from oscillator 4 having period T_osc), circuitry 6 causes a first input of comparator 2 to be at a periodic ramped potential (having peak level kV_inand period T_osc). Preferably, circuitry 6 includes current multiplying circuit 6A (having an input which receives current I2 and an output which asserts a current proportional to I2), a capacitor which is charged by the output current of circuit 6A, and a switch coupled to periodically discharge the capacitor (with period T_OSC) in response to control pulses from oscillator 4.

[0026] Amplifier 3 has an input coupled to receive potential V_out(which is the DC-to-DC converter's output potential, or a DC potential which corresponds to a desired level for such output potential), and is configured to assert an amplified potential kV_outin response thereto, where k is the same coefficient as in the peak level kV_inof the ramped voltage produced by circuitry 6.

[0027] In response to potential kV_outfrom amplifier 3 and ramped voltage kV_infrom generator 1, comparator 2 asserts a binary pulse train comprising pulses T_ON. The leading edges (falling edges) of pulses T_ONoccur with period T_OSC. The trailing edge (rising edge) of each pulse T_ONoccurs when ramped voltage kV_inrises to a level matching kV_out. Thus, the width of each pulse T_ONis equal to T_OSC(V_out/V_in), and the width of each pulse T_ONis thus indicative of the nominal (or critical) power switch on-time needed for the DC-to-DC converter to produce output potential V_out(during steady-state operation) in response to input potential V_in.

[0028] Preferably, the circuitry of FIG. 1 is implemented so that the width of each pulse T_ONis accurately equal to T_OSC(V_out/V_in), independently of process variations (i.e., variations in the manufactured characteristics of the circuitry, which will typically be integrated circuitry) and variations in operating temperature. Examples of such preferred implementations will be described with reference to FIGS. 2 and 3.

[0029] FIG. 2 is a block diagram of a preferred embodiment of circuit 1 of FIG. 1, which includes temperature-independent current source 10, capacitors C1 and C2, matching NMOS transistors Q1 and Q4, comparator 12, one-shot 14, transconductance amplifiers 5 and 15, and current multiplier 16, connected as shown. Both the input of amplifier 15 and the inverting input of comparator 12 are maintained at reference potential Vref. Current source 10 sources a current I1 to the “X” input of current multiplier 16, and to node A (the top plate of capacitor C1 and the drain of transistor Q1). After transistor Q1 has been turned on (to discharge capacitor C1) and then turned off (in response to assertion of appropriate control signals to capacitor C1's gate), Node A's potential rises (as capacitor C1 charges) until it reaches reference potential Vref (the potential at which the inverting input of comparator 12 is held). When Node A's potential reaches Vref, a level transition at the output of comparator 12 causes one-shot 14 to assert a brief reset pulse to the gate of each of transistors Q1 and Q4. In response to each reset pulse, transistors Q1 and Q4 turn on for a brief time to discharge capacitors C1 and C2. The level of current I1 is set so that T_OSC=(Vref)C1/I1. Thus, one-shot 14 asserts a periodic train of reset pulses (to the gates of Q1 and Q4) having period T_OSC.

[0030] The “Y” input of current multiplier 16 is coupled to the output of amplifier 5 to receive current I2 having level I2=gm₂(V_in)=V_in/R2, where R2 is the resistance of a resistor within amplifier 5. The “Z” input of current multiplier 16 is coupled to the output of transconductance amplifier 15 to receive current I3 having level I3=gm₃(V_in)=Vref/R3, where R3 is the resistance of a resistor within amplifier 15. Thus, the output of current multiplier 16 (at Node B, which is the top plate of capacitor C2 and the drain of transistor Q4) is current I4 whose amplitude is I4=(I1)(I2)/I3=I1(V_in/Vref)(R3/R2). Preferably, current multiplier 16 multiplies the currents in a manner that exploits bipolar transistor Vbe-Ic exponential characteristics.

[0031] The FIG. 2 circuit produces at Node B a periodic ramped potential having period T_OSCand peak potential Vpeak. More specifically, during each period T_OSCafter transistor Q4 is turned off (in response to assertion, to capacitor C4's gate, of one of the above-described reset pulses asserted from one shot 14) after being turned on (to discharge the capacitor C4), Node B's potential rises (as capacitor C4 charges) from ground potential until it reaches the peak potential Vpeak=kV_in, where k=(C1/C2)(R3/R2). At the end of each such period T_OSC, capacitor C4 is discharged to cause the potential at Node B to fall rapidly back to zero.

[0032] During each cycle of the ramped potential at Node B (i.e., once per period T_OSC), a level transition occurs at the output of comparator 2 when Node B's potential rises to the level kV_out. More specifically, the output of comparator 2 has falling edges which occur periodically (with period T_OSC), each falling edge occurring in response to the potential at Node B falling to ground potential. The output of comparator 2 has a rising edge each time the potential at Node B rises to a level matching kV_out. Thus, the width of each positive-going pulse T_ONis equal to T_OSC(V_out/V_in).

[0033] As noted, amplifier 3 (of FIG. 1) asserts to comparator 2 an amplified potential kV_out, where k is the same coefficient that multiplies V_inin the peak level kV_inof the ramped potential at Node B. Thus, amplifier 3 asserts to comparator 2 an amplified potential kV_out, where k=(C1/C2)(R3/R2).

[0034] Amplifiers 5 and 15 are implemented so that their gains (1/R2 and 1/R3, respectively) depend in the same way on temperature. Thus, since the value of k depends on the ratio R3/R2, the gains 1/R2 and 1/R3 do not contribute to any temperature coefficient of the value k even though both 1/R2 and 1/R3 depend on temperature.

[0035] Similarly, the capacitors C1 and C2 can be implemented so that their capacitances depend in the same way on temperature. Thus, since the value of k depends on the ratio C1/C2, as well as on the ratio R3/R2, neither the capacitances C1 and C2 nor the gains 1/R2 and 1/R3 contribute to any temperature coefficient or process variation, and the value k is independent on operating temperature of the FIG. 2 circuit.

[0036] FIG. 3 is a block diagram of a preferred embodiment of the inventive circuitry, including circuits 3 and 2 of FIG. 1 and a variation on elements 16, C2, and Q4 of FIG. 2. The FIG. 3 circuit includes circuitry for compensating for the delay time of comparator 2. Specifically, the FIG. 3 circuit includes resistor R5 between Node C (the top plate of capacitor C2) and Node D (the output of current multiplier 16 and noninverting input of comparator 2). The potential at Node C is the same as at Node B of FIG. 2: a periodic ramped potential having period T_OSCand peak potential Vpeak=k(V_in), where k=(C1/C2)(R3/R2). Thus, the potential at Node D is such periodic ramped potential plus the offset potential I4R5(so that the peak potential of the ramped potential at Node D is k(V_in)+I4R5). The offset potential I4R5 is equal to I1(V_in/V_ref)(R3/R2)R5.

[0037] The delay time of comparator 2 is Td (shown in FIG. 4). Thus, if R5 were zero (i.e., if there were no delay compensation), the rising edges of the output of comparator 2 would occur at times Td too late (i.e., each rising edge would occur at a time Td after the potential at the noninverting input of comparator 2 rises to a level matching kV_out). Since each of the above-described pulses T_ON(of the binary output of comparator 2) has duration T_OSC(V_out/V_in), the relative error in the duration of pulses T_ON(due to the delay time of comparator 2) is greater at higher values of V_inthan for lower values of V_in(for a fixed value of V_out). This can be seen by comparison of FIG. 4 (which assumes a relatively low value of V_in) and FIG. 5 (which assumes a relatively high value of V_in).

[0038] The offset potential I4R5 compensates for the error in T_ONdue to the delay time of comparator 2, by causing the comparator output to undergo a low-to-high transition earlier than it would in the absence of the offset potential. Since the offset potential I4R5 is equal to I1(V_in/V_ref)(R3/R2)R5, the offset potential increases proportionally to V_inand thus provides a greater degree of compensation for comparator delay time when the error (in the width of pulse T_ON) due to the comparator delay time is relatively greater (as is apparent from comparison of FIGS. 4 and 5).

[0039] In typical implementations of comparator 2, the delay Td has a positive temperature coefficient. Since I4 has no significant temperature coefficient, and R5 has a positive temperature coefficient, the offset potential I4R5 desirably varies with temperature in a manner compensating for changes (due to temperature changes) in the comparator delay Td.

[0040] FIG. 6 is a simplified schematic diagram of a preferred embodiment of a DC-to-DC converter whose controller includes the inventive on-time generation circuit. The DC-to-DC converter of FIG. 6 includes current mode switching controller chip 100, and buck converter circuitry external to the controller chip. The buck converter circuitry of FIG. 6 comprises NMOS transistors N1 and N2 (which function as power switches), inductor L, capacitor C_out, and feedback resistor divider R_F1and R_F2, connected as shown. The FIG. 6 circuit produces a regulated DC output voltage V_outacross load R_LOAD, in response to input DC voltage V_in.

[0041] Controller chip 100 implements a control signal channel which generates pulse width modulated power switch control signals (“PWM switch control” signals) for power switches N1 and N2 in response to a ramped voltage and a train of set pulses (generated by circuitry within oscillator, logic, and PWM comparator circuit 90), a feedback signal (supplied from Node A to the inverting input of error amplifier 10) indicative of the DC-to-DC converter's output potential, and a feedback signal indicative of current through the channel of switch N1. One of the PWM switch control signals controls the gate of power switch N1, and the other PWM switch control signal controls the gate of power switch N2.

[0042] Typically, each PWM switch control signal is a binary signal having periodically occurring leading edges, and trailing edges which occur at times determined by the instantaneous value of the feedback signals. The feedback signal indicative of the DC-to-DC converter's output potential is asserted to the inverting input of error amplifier 10, and the noninverting input of error amplifier 10 is at a reference potential V_REFERENCE. A comparator (within circuit 90) compares the output of error amplifier 10 with the ramped voltage, and other circuitry within circuit 90 generates reset pulses (in response to the output of the comparator) which determine the times at which one of the PWM switch control signals switches off power switch N1. The described use of the ramped voltage improves stability through a technique known as “slope compensation”.

[0043] Controller chip 100 includes circuit 80, which is an embodiment of the inventive on-time generation circuit. Circuit 80 includes amplifier 3, ramp generator 1, and comparator 2 (connected as shown), which are identical to the correspondingly numbered elements of FIG. 1. The input of amplifier 3 is coupled to the converter's output node (and thus is maintained at the converter's output potential V_out). The input of ramp generator 1 is coupled to the converter's input node (and thus is maintained at the converter's input potential V_in). The output of comparator 2(a binary pulse train comprising the above-described inventive pulses T_ON, each having width equal to T_OSC(V_out/V_in) is coupled to circuit 90, and is employed by logic circuitry within circuit 90 to generate the PWM switch control signals.

[0044] Although only a preferred embodiment has been described in detail herein those having ordinary skill in the art will certainly understand that many modifications and variations thereon are possible without departing from the teachings hereof. For example, a wide variety of DC-to-DC converters which employ circuitry, other than buck converter circuitry, external to a current mode switching controller can be implemented in accordance with the invention (in one class of such DC-to-DC converters, boost converter circuitry external to a current mode switching controller chip is employed, the boost converter circuitry provides voltage signals indicative of the individual channel currents to the controller chip, and the controller chip is implemented in accordance with the invention). All such modifications and variations are intended to be encompassed within the following claims.