Method of fabricating flash memory

[0002] This application claims the priority benefit of Taiwan application serial no. 88101441, filed Jan. 30, 1999, the full disclosure of which is incorporated herein by reference.

[0003] 1. Field of Invention

[0004] The present invention relates to a fabrication method of a flash memory. More particularly, the present invention relates to a method of fabricating an NAND flash memory structure which provides a higher density memory device array.

[0005] 2. Description of Related Art

[0006] A conventional flash memory structure is characterized by a gate structure having two layers. One layer is a floating gate, fabricated from polysilicon for storing charges, and is usually in a floating status without being connected to any other circuits. Another layer is a control gate for controlling the date access to the floating gate. For example, in a NAND flash memory, each floating gate of the flash memory is connected to a word line (W/L) and each source/drain region of the flash memory is connected in series to a bit line (B/L). Flash memory is a very popular Erasable Programmable Read-Only Memory (EPROM) which can provide faster programming and erasing. Conventionally, the read/write function of the flash memory is performed using Fowler-Nordheim tunneling between the floating gate and the doped region, the rate of which depends on the electron transmission speed between the floating gate and the doped region.

[0007] Manufacturing flash memory at a minimized size is necessary in semiconductor process; i.e. the distribution of flash memory needs to have a higher density in order to conform to the process requirements. But, in this case, the extent to minimize the size of the flash memory is limited, if the flash memory conforms to the design rule. Moreover, it is very difficult to fabricate a tunneling oxide layer between the floating gate and the substrate when the thickness of the tunneling oxide layer is required to be very thin. It is especially difficult to perform the alignment step. It is important to precisely conform to the Shallow Trench Isolation (STI) process, so that the unnecessary shorts and leakage resulting between the device and the substrate are prevented.

[0008] The invention provides a method for fabricating an improved flash memory structure. A tunneling oxide layer can be formed as a part of a more precise flash memory structure using a self-aligned method that conforms to STI process steps. It is appropriate to use in a high density memory device array.

[0009] In the invention, a method for fabricating a flash memory is provided with following steps. A substrate is provided with a pad oxide layer and a first insulating layer sequentially formed thereon. A photolithography and etching process is performed to expose a part of the pad oxide layer, wherein the substrate covered by the remaining first insulating layer is defined as an active region. With the first insulating layer serving as a mask, the pad oxide layer and the semiconductor substrate are etched to form a trench in the semiconductor. The trench is filled with a plug which serves as a shallow trench isolation. The surface of the plug is approximately levelled with the surface of the first insulating layer. The first insulating layer and the pad oxide layer are removed, so that the surface of the plug is projected above the substrate. A gate oxide layer is formed on the substrate. Spacer is formed on a sidewall of the plug projecting above the surface of the substrate. With the spacer serving as a mask, the gate oxide layer uncovered by the spacer is removed by etching while a part of the plug is also removed, so that the surface of the plug is lowered to some extent. Then, with the spacer and the plug serving as a mask, a self-aligned tunneling oxide layer is formed by thermal oxidation on the exposed substrate, and the spacer is removed thereafter. In addition, the floating gate is formed on the tunneling oxide layer, the gate oxide layer and a part of the plug. A dielectric layer and a control gate are formed in sequence on the floating oxide layer and the exposed plug, so that the flash memory structure is complete.

[0010] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

[0011] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0012] FIG. 1 is a schematic diagram showing the top view of a NAND flash memory structure according to one preferred embodiment of this invention; and

[0013] FIGS. 2A to 2H are schematic, cross-sectional diagrams showing the process flow for fabricating the flash memory structure according to one preferred embodiment of this invention.

[0014] Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0015] Using a self-aligned method that conforms to the STI process, the invention provides a method of fabricating an NAND flash memory structure with an improved tunneling oxide layer. A flash memory structure can be formed with more precisely aligned steps and higher coupling efficiency than the prior art, and a memory device array of higher density is made.

[0016] FIG. 1 is a schematic diagram showing a top view of an NAND flash memory structure according to one preferred embodiment of this invention. A floating gate 12 (also known as poly 1) lies on a substrate. An array of control gates 14 (also known as poly 2) are formed to cover the floating gate 12 and to serve as a W/L. Typically, the control gates 14 are in a strip shape extending parallel to each other. Bit lines 16 are formed over and perpendicular to the control gates 14. The bit lines are connected in series to the source and drain region (not shown) of each flash memory cell.

[0017] FIGS. 2A to 2H are schematic, cross-sectional diagrams showing the fabricating process flow of the flash memory according to one preferred embodiment of this invention. A substrate 20 is provided with the pad oxide layer 22 and the first insulating layer 24 formed in sequence thereon. Preferably, the first insulating layer is formed of silicon nitride by the chemical vapor deposition (CVD) to a thickness of approximately 200-2000 Å. A photolithography and anisotropic etching step is performed to form a photoresist layer 26 on the first insulating layer 24. The first insulating layer 24 is etched to expose a part of the pad oxide layer 22, wherein the substrate covered by the remaining first insulating layer is defined as an active region.

[0018] In FIG. 2B, using the first insulating layer 24 as a mask, the pad oxide 22 and the substrate 20 are etched to form a trench 28 in the substrate 20. A thin layer of liner oxide layer 30 is formed by, for example, thermal oxidation in the trench 28.

[0019] In FIG. 2C, the trench 28 is filled with a plug 32. Preferably, a second insulating layer, for example a silicon oxide layer is formed by CVD to fill the trench 28 over the substrate 22. A polishing step such as a chemical mechanical polishing (CMP) step or an etch back step is performed to form the plug 32. The surface of the plug 32, which is used for STI, has a surface level similar to that of the first insulating layer 24.

[0020] In FIG. 2D, an etching, such as wet or dry etching is performed to remove the first insulating layer 24 and the pad oxide layer 22. This enables the surface of the plug 32 to be projected above the substrate 20. As a consequence, the plug 32 has a sidewall 33 as shown in FIG. 2D. A gate oxide layer 22ais formed by thermal oxidation on the substrate 20.

[0021] In FIG. 2E, a spacer 34 is formed on the sidewall 33 of the plug 32. A material is selected for the spacer 34 to have a different etch ratio from the underlying gate oxide layer 22aand the plug 32. For example, a SiN layer is used in this embodiment. Preferably, the method of fabricating the spacer 34 is to deposit the silicon nitride layer to a thickness of about 100-1000 Å. Then, with the gate oxide layer 22aserving as the stop layer, the silicon nitride layer is anisotropically etched back. Accordingly, the spacer 34 is formed on the sidewall 33.

[0022] In FIG. 2F, the part of the gate oxide layer 22auncovered by the spacer 34 is removed by anisotropic etching. Here, a portion of the plug can be removed to form a plug 32awith a lower surface, while still higher than that of the substrate 20.

[0023] In FIG. 2G, with the spacer 34 and the plug 32aserving as a mask, a self-aligned tunneling oxide layer 36 is formed on the exposed substrate 20 by a thermal process. Preferably, the tunneling oxide layer 36 is formed by thermal oxidation to a thickness of about 50-100 Å. The silicon reacts with oxygen at a high temperature and thus silicon dioxide is grown on the semiconductor substrate 20.

[0024] FIG. 2H, the spacer 34 is removed by wet etching, dry etching, or dipping the whole semiconductor substrate in phosphoric acid. A floating gate 38 is formed on the tunneling oxide layer 36, the gate oxide layer 22a, and a part of the plug 32. Preferably, the material for the floating gate is polysilicon, formed by CVD and doping to deposit a polysilicon layer to a thickness of about 500-2000 Å. A photolithography and etching step is performed to define the pattern and to form the floating gate 38. A thin dielectric layer 40 is formed on the floating gate 38 and the exposed plug 32. Preferably, the material for the dielectric layer 40 is oxide/nitride/oxide (ONO). The control gate 42 is formed sequentially on the dielectric layer 40. Preferably, the material for the control gate 42 is also a doped polysilicon layer. Thus, the flash memory of the invention is complete. To summarize the above, the invention provides a method of fabricating a flash memory, having the following characteristics:

[0025] (1) The invention provides a fabricating method to improve the tunneling oxide layer for a NAND flash memory.

[0026] (2) Using self-alignment that conforms to the STI process steps, the invention can form a flash memory with a more precise aligned step than the prior art.

[0027] (3) The invention can manufacture a flash memory with a higher coupling efficiency than the prior art, and it is appropriate to use in a high-density memory device array.

[0028] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.