Power management override for portable computers

[0002] The invention relates generally to power management systems for personal computers and, more particularly, to a method and apparatus for overriding selected aspects of such power management systems.

[0003] Portable personal computers (PCs) were first introduced in the early 1980s and have since enjoyed great commercial success and consumer acceptance. As the portable PC market has grown, users have begun to demand lighter weight, lower volume PCs which can be used for longer periods of time between battery charges. Meeting these demands has proved challenging in view of the fact that most portable PCs now support peripheral devices previously available only on desktop PCs. The additional peripherals greatly increase overall power consumption, making it difficult to achieve an optimal level of functionality while maintaining an acceptable battery life. Furthermore, it has also become desirable to more efficiently manage the power consumption of non-battery powered desktop PCs in order to minimize overall operating costs.

[0004] One solution has been to design into the computer's basic input/output system (BIOS) a pre-packaged power management routine, or to load into the computer's operating system (OS) a pre-packaged driver, such as the Microsoft™/Intel™ Advanced Power Management (APM) driver, that regulates the application of power to certain devices by placing such devices in an “idle” state when demand for such devices is low. For example, when die central processing unit (CPU) is not executing a program, its power consumption can be reduced considerably by decreasing the speed at which it operates. Further examples include turning off the LCD backlight or blanking the monitor screen after a period of keyboard inactivity and stopping the hard-disk drive motor after the drive has not been accessed for a preset internal of time.

[0005] Once the power to the CPU, an I/O device, or other peripheral device is reduced the device can be powered back up if there is a demand for that device. The device though does not “wake up,” i.e., regain its full capabilities, instantly, but rather requires a finite amount of time, or “latency,” to do so.

[0006] A problem with power management systems, as they are currently available, is that important data may be lost during the latency of the CPU when data is initially transmitted to it Specifically, such a loss of data can result when the CPU is connected to critical, “real-time” devices such as serial peripheral I/O devices, including instrumentation interfaces, modems, and PCMCIA controllers, that transmit data serially to the CPU. These devices typically include a buffer for storing a limited number of bytes of data to be transmitted to the CPU. Once the buffer is full, the stored bytes are overwritten by new incoming bytes of data It can be appreciated that bytes of data can thus be stored in the buffer for only a limited amount of time, and if that time is less than the latency of the CPU, then data will be lost.

[0007] The latency problem may be avoided by selectively disabling the computer's power management system. Most conventional power management systems, prepackaged with available computer operating systems, have the capability to selectively enable and disable their power management functions. However, this defeats the purpose of the power management system because all devices would then utilize full power and the user would forfeit the advantages of power management. While some such systems can be operated by the user to selectively disable only certain devices, many do not have this capability and, in particularly, cannot be operated to disable power management functions with respect to the CPU only, while remaining enabled for the other devices.

[0008] What is needed, therefore, is a system for overriding, the operation of a computer's prepackaged power management system that disables power management functions of the CPU only, without disabling power management for other devices, to thereby solve the CPU latency problem when a power managed computer is operated in connection with serial data devices.

[0009] The foregoing problems are solved and a technical advance is achieved by a system and method for selectively disabling the existing power management functions of a computer with respect to the CPU only, without disabling the other power management functions of the computer, so that the CPU does not experience latency in being reactivated to receive data transmitted from a device connected thereto. In a departure from the art, a power management override system is stored in the computer's memory that controls a CPU idle override flag. If set, the flag prevents the power management system of the computer from reducing the power to the CPU.

[0010] In a preferred embodiment, a system is disclosed for managing the power efficiency of a computer having a memory, a processor, and one or more power consuming devices; wherein the computer is to be operatively connected to a critical input/output (I/O) device requiring the processor to be fully powered when transmitting data to the processor. The system comprises a power management system stored in the memory for selectively controlling the power consumption of the processor and the power consuming devices between operation in full power and reduced power consumption states.

[0011] The system further comprises an override system stored in the memory for overriding the power management system to prevent the processor from being operated in the reduced power consumption stare yet without preventing the power consuming devices from being operated in the reduced power consumption state. The power management override system includes a CPU idle override flag which may be set or cleared to enable or disable, respectively, the power management system. If the override flag is clear, then the override system is disabled, thereby permitting the power management system to execute instructions for reducing power to the CPU. If, however, the override flag is set, then the override system is enabled and the power management system is prevented from executive instructions for reducing power to the CPU. In a first aspect of the present invention, a user may selectively enable or disable the overriding by setting or clearing, respectively, the override flag. In a second aspect of the invention, the processor may selectively enable the overriding automatically by setting the override flag when the critical I/O device is actively connected to the computer, and disable it otherwise.

[0012] A technical advantage achieved with the present invention is that, because the power management of the CPU can be selectively disabled, the CPU can be prevented from experiencing a CPU latency or “wake up” period, thereby avoiding the problem of losing data that may have been transmitted during that period.

[0013] Another technical advantage achieved with the invention is that power management of the CPU may be selectively disabled without shutting down the entire computer system or disabling power management to other system devices.

[0014] Yet another technical advantage achieved with the invention is that it is operable without requiring that pre-packaged power management driver code be rewritten or even modified. Accordingly, the present invention is readily adaptable for use with a number of different prepackaged power management drivers.

[0015] FIG. 1 is a functional block diagram of a personal computer embodying features of the power management override system of the present invention; and

[0016] FIG. 2 is a flowchart of the logic implemented by the power management override system in the system of FIG. 1.

[0017] FIG. 1 is a functional block diagram of a personal computer (PC) 10 embodying features of the present invention. The PC 10 comprises a central processing unit (CPU) 12 connected via a host bus 14 to a system RAM 16 and a number of I/O devices collectively designated by the reference numeral 18. The I/O devices 18 may include for example, serial communication devices 20, PCMCIA controllers 22, a display (not shown), a keyboard (not shown), a disk drive (not shown), and a pointing device such as a mouse (not shown). The PC 10 further includes an operating system (OS) 24 which is stored in the system RAM 16. A power management system providing standard power management routines such the Microsoft/Intel APM driver, designated by the reference numeral 26, is also stored in the RAM 16.

[0018] According to the invention, a power management system override system 28 is stored in the RAM 16. The system 28 includes a user flag 30 and a system flag 32, for reasons discussed in detail below. As explained below, the system 28 is used to override the power management system 26 so that power management functions are disabled with respect to the CPU 12 only, but not disabled with respect to other power-managed devices.

[0019] FIG. 2 illustrates a flowchart of the operation of the system 28. Execution automatically begins at step 200 upon initiation of the operating system 24 of the PC 10. In step 210, a determination is made whether the power management system 26 has issued an instruction to place the CPU 12 in an idle state, i.e., to “power down” the CPU. Typically, the power management system 26 will issue such an instruction when there is a predetermined period of CPU 12 inactivity, for instance when the CPU is not executing a program and may be powered down to an “idle” state. If, in step 210, a CPU idle instruction has not been issued, execution remains at step 210. If, in step 210, a CPU idle instruction has been issued, execution proceeds to step 220.

[0020] In step 220, the override system 28 determines whether the user override flag 30 is set or is cleared. The user may set or clear the override flag 30 using conventional computer interface techniques. If, in step 220, the user override flag 30 has been set, execution returns to step 210. If, in step 220, the user override flag 30 has not been set, i.e., it is clear, execution proceeds to step 230.

[0021] In step 230, the override system 28 determines whether the device override flag 32 is set or is cleared. The device override flag 32 is cleared under normal operating conditions of the operating system 24. However, the flag 32 is set if a “critical” device is activated on the system. As used here, a “critical” device is any device which may require service of an event by the CPU 12 during the CPU's latency “wake up” period wherein loss of such data due to the latency would be unacceptable. Examples of such critical devices include one or more serial communications devices 20 and the PCMCIA controller 22. If, in step 230, the device override flag 32 has been set, execution returns to step 210. If, in step 230, the device override flag 32 has not been set, i.e., it is clear, execution proceeds to step 240 in which power to the CPU 12 is reduced or even removed totally. This is accomplished in a conventional manner such as by controlling the CPU clock speed.

[0022] In step 250, the override system 28 determines whether an interrupt request (IRQ) has been issued to the CPU 12. If, in step 250, an IRQ is not issued, execution remains at step 250. If, in step 250, an IRQ is issued, execution proceeds to step 260 in which the CPU is powered up for operation, and execution then returns to step 210.

[0023] It is understood that the present invention can take many forms and embodiments. The embodiments shown herein are intended to illustrate rather than to limit the invention, it being appreciated that variations may be made without departing from the spirit or the scope of the invention. For example, an override system similar to the system 28 described herein could be implemented for non-CPU devices of the PC 10, such as the hard disk drive. In addition, other criteria, such as time of inactivity, could be used to set or clear the device flag 32.

[0024] Although illustrative embodiments of the invention have been shown and described, a wide range of modification, change and substitution is intended in the foregoing disclosure and in some instances some features of the present invention may be employed without a corresponding use of the other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention.