Electrostatic discharge protection circuit

[0002] 1. Field of the Invention

[0003] The invention relates to an electrostatic discharge protection circuit, and more particularly to a gate coupled electrostatic discharge protection circuit which is formed with parasitic capacitors generated using a principle of gate couple, to ensure that parasitic bipolar junction transistors can be speedily turned on to protect a related high-voltage device from damages.

[0004] 2. Description of the Prior Art

[0005] In semiconductor industry, electrostatic discharge (ESD) is always a main reason to cause damages on ICs during manufacturing. For example, under an environment with higher relative humidity (RH), there will be several hundred, even several thousand, voltages of electrostatic charges detected when a person walks through a rug. In an environment with lower relative humidity, electrostatic charges will reach more than ten thousand voltages. When the rug or person bringing high-voltage electrostatic charges contacts a chip, the electrostatic charges will be discharged toward the chip, causing irretrievable damages on the chip. To prevent chips from any damages caused by electrostatic charge discharge, various electrostatic discharge protection circuits have been developed. Typically, in the prior art, an on-chip electrostatic discharge protection circuit is designed between an internal circuit and each pad for protecting the internal circuit from damages.

[0006] Referring to FIG. 1, a structure of a conventional high-voltage electrostatic discharge protection circuit is shown. In the conventional high-voltage electrostatic discharge protection circuit, a high-voltage N-well region 12 and a high-voltage P-well region 14 adjacent to each other are formed in an N-type substrate 10. A PMOS transistor 16 is formed on the high-voltage N-well region 12. The PMOS transistor 16 has its gate 18 and source 20 electrically connected to a high voltage V_DD, together and its drain electrically connected to an input/output pad (I/P PAD) 23.

[0007] The source 20 is constructed by a P⁺-type region 24, a P-grad region 26 and a P-drift region 28. The P-grade region 26 is beneath and sounding the P⁺-type region 24. The P-drift region 28 is adjacent to the P-grade region 26, partly under the gate 18. Similarly, the drain 22 is constructed by a P⁺-type region 30, a P-grade region 32 and a P-drift region 34. The P-grade region 32 is beneath and surrounding the P⁺-type region 30. The P-grade region 32 is beneath and surrounding the P⁺-type region 30. The P-drift region 34 is adjacent to the P-grade region 32, partly under the gate 18. Furthermore, on the high-voltage N-type well region 12, there are an N⁺-base connection region 38 electrically connected to the high voltage V_DDand a first isolation region 36, wherein the source 20 and the N⁺-base connection region 38 are adjacent to both sides of the first isolation region 36.

[0008] Similarly, an NMOS transistor 42 is formed on the high-voltage P-well region 14. The NMOS transistor 42 has its gate 44 and source 46 electrically connected to ground V_SS, together and its drain 48 electrically connected to the input/output pad 23. The drain 48 is constructed by an N⁺-type region 50, an N-grade region 52 and an N-drift region 54. The N-grade region 52 is beneath and surrounding the N⁺-type region 50. The N-type drift region 54 is adjacent to the N-grade region 52, partly under the gate 42. The source 46 is constructed by an N⁺-type region 56, an N-grade region 58 and an N-drift region 60. The N-grade region 58 is beneath and surrounding the N⁺-type region 56. The drift region 60 is adjacent to the N-grade region 58, partly under the gate 44. Moreover, on the high-voltage P-well region 14, there are an P⁺-base connection region 64 electrically connected to the ground V_SS, wherein the source 46 and the P⁺-base connection region 64 are adjacent to both sides of a second isolation region 62. Additionally, there is a third isolation region 40 is formed on the N-type substrate 10 and between the high-voltage N-well region 12 and the high-voltage P-well region 14. In other words, the drain 22 of the PMOS transistor 16 and the drain 48 of the NMOS transistor 42 are located on both sides of the third isolation region 40.

[0009] Due to the requirement of high-voltage process, the P-well region 14 is formed with high resistance. Consequently, two parasitic bipolar junction transistors 66, 68 shown in FIG. 1 have a higher breakdown voltage (BV). Meanwhile, as shown in FIG. 2, the gates of the PMOS transistor 16 and the NOMS transistor are electrically connected to V_DDand V_SS. As a result, it is uneasy to turn on the parasitic bipolar transistors 66 and 68 to release electrostatic charges in a short time.

[0010] In view of the above, the invention is to provide a high-voltage electrostatic discharge protection circuit, which is formed with parasitic capacitors generated using a principle of gate couple, to ensure that parasitic bipolar junction transistors can be speedily turned on to protect a related high-voltage device from damages.

[0011] A high-voltage electrostatic discharge protection circuit according to the invention has the following structure. A first high-voltage N-well region, a first high-voltage P-well region, a second high-voltage N-well region and a second high-voltage P-well region are adjacent to each other. A PMOS transistor is formed on the first high-voltage N-well region and has its source electrically connected to a high voltage and its drain electrically connected to an input/output pad. A first isolation region is formed between the first high-voltage N-well region and the first high-voltage P-well region and electrically connected to the drain of the PMOS transistor. A first N⁺-type region is formed between the first high-voltage P-well region and the second high-voltage N-well region, adjacent to the first isolation region and electrically connected to the input/output pad. A polysilicon gate region is formed on the second high-voltage N-well region, adjacent to the first N⁺-type region and electrically connected to the gate of the PMOS transistor. An NMOS transistor has its drain located between the second high-voltage N-well region and the second high-voltage P-well region and adjacent to the polysilicon gate region and its gate and source located on the second high-voltage P-well region, wherein the drain is electrically connected to the input/output pad, the gate is electrically connected to the polysilicon gate region and the source is electrically connected to a ground voltage.

[0012] The invention will become more fully understood from the detailed description given hereinafter and the accompanying drawings which are given by way of illustration only, and thus do not limit the present invention, and wherein:

[0013] FIG. 1 is a schematic, cross-sectional view showing a structure of a high-voltage electrostatic discharge protection circuit according to the prior art;

[0014] FIG. 2 is a circuit diagram corresponding to the structure of FIG. 1;

[0015] FIG. 3 is a schematic, cross-sectional view of a structure of a high-voltage electrostatic discharge protection circuit according to a preferred embodiment of the invention; and

[0016] FIG. 4 is a circuit diagram corresponding to the structure of FIG. 3.

[0017] Referring to FIG. 3, a high-voltage electrostatic discharge protection circuit according to a preferred embodiment of the invention is shown. In FIG. 3, a first high-voltage N-well region 102, a first high-voltage P-well region 104, a second high-voltage N-well region 106 and a second high-voltage P-well region 108 adjacent to each other are formed in an N-type substrate 100.

[0018] Moreover, a PMOS transistor 110 is formed on the first high-voltage N-well region 102 and has its source 112 electrically connected to a high voltage V_DD, its drain 116 electrically connected to an input/output pad (I/P PAD) 118 and its gate 114 located between the drain 116 and the source 112.

[0019] Similarly, an NMOS transistor 132 is formed on the second high-voltage P-well region 108 and has its source 138 electrically connected to ground V_SS, its drain 134 electrically connected to the input/output pad (I/P PAD) 118 and its gate 136 located between the drain 134 and the source 138.

[0020] A first N⁺-type region 126 is formed on the N-type substrate 100 and between the second high-voltage N-well region 106 and the first high-voltage P-well region 104 and electrically connected to the P-grade region 118. A polysilicon gate region 128 is formed on the second high-voltage N-well region 106, adjacent to the drain 134 and the first N⁺-type region 126 and electrically connected to the gates 136 and 114.

[0021] Moreover, a first isolation region 120 is formed on the N-type substrate 100 and adjacent to the first N⁺-type region 126 and the P⁺-type region 116. A second isolation region 122 is formed on the first high-voltage N-well region 102 and has the source 112 and an N⁺-type base connection region 124 located on both sides thereof, wherein the N⁺-type base connection region 124 is electrically connected to the high voltage V_DD. A third isolation region 140 is formed on the second high-voltage P-well region 108 and has the source 138 and a P⁺-type base connection region 142 located on both sides thereof, wherein the P⁺-type base connection region 142 is electrically connected to ground V_SS.

[0022] Referring now to FIG. 4, a circuit diagram of the high-voltage electrostatic discharge protection circuit of FIG. 3 is shown. In FIG. 4, transistors 144 and 146 are corresponding to the PMOS transistor 110 and the NMOS transistor of FIG. 3. Furthermore, parasitic capacitors 148 and 150 are formed under the polysilicon gate region 128 thereby to ensure that parasitic bipolar junction transistors can be speedily turned on to protect a related high-voltage device from damages.

[0023] While the invention has been described by way of example and in terms of the preferred embodiment, it is to be understood that the invention is not limited to the disclosed embodiments. On the contrary, it is intended to cover various modifications and similar arrangements as would be apparent to those skilled in the art. Therefore, the scope of the appended claims should be accorded the broadest interpretation so as to encompass all such modifications and similar arrangements.