Method of forming DRAM circuitry on a semiconductor substrate

[0002] This application is a continuation application of Ser. No. 08/612,164, which was filed on Mar. 7, 1996, now U.S. Pat. No. 5,786,249.

[0003] This invention relates to methods of forming DRAM circuitry.

[0004] High density integrated circuitry is principally fabricated from semiconductor wafers. An MOS (metal-oxide-semiconductor) structure in semiconductor processing is created by superimposing several layers of conducting, insulating and transistor forming materials. After a series of processing steps, a typical structure might comprise levels of diffusion, polysilicon and metal that are separated by insulating layers. Upon fabrication completion, a wafer contains a plurality of identical discrete die areas which are ultimately cut from the wafer to form individual chips. Die areas or cut dies are tested for operability, with good dies being assembled into separate encapsulating packages which are used in end-products or systems.

[0005] CMOS is so-named because it uses two types of transistors, namely an n-type transistor (NMOS) and a p-type transistor (PMOS). These are fabricated in a semiconductor substrate, typically silicon, by using either negatively doped silicon that is rich in electrons or positively doped silicon that is rich in holes. Different dopant ions are utilized for doping the desired substrate regions with the desired concentration of produced holes or electrons.

[0006] NMOS remained the dominant MOS technology as long as the integration level devices on a chip was sufficiently low. It is comparatively inexpensive to fabricate, very functionally dense, and faster than PMOS. With the dawning of large scale integration, however, power consumption in NMOS circuits began to exceed tolerable limits. CMOS represented a lower-power technology capable of exploiting large scale integration fabrication techniques.

[0007] One type of integrated circuitry comprises memory. The basic unit of semiconductor memory is the memory cell. Capable of storing a single bit of information, the memory cell has steadily shrunk in size to enable more and more cells per area of a semiconductor substrate or wafer. Such enables integrated memory circuitry to be more compact, as well as faster in operation.

[0008] Example semiconductor memories include ROMs, RAMs, PROMs, EPROMs and EEPROMs. Some emphasize compactness and economy over speed. Others focus on lightening-fast operation. Some store data indefinitely, while others are so temporary they must be refreshed hundreds of times every second. One of the smallest memory cell comprises the single transistor and single capacitor of a dynamic random access memory (DRAM).

[0009] Preferred embodiments of the invention are described below with reference to the following accompanying drawings.

[0010] FIG. 1 is a diagrammatic sectional view of a semiconductor wafer fragment at one processing step in accordance with the invention.

[0011] FIG. 2 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 1.

[0012] FIG. 3 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 2.

[0013] FIG. 4 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 3.

[0014] FIG. 5 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 4.

[0015] FIG. 6 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 5.

[0016] FIG. 7 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 6.

[0017] FIG. 8 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 7.

[0018] FIG. 9 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 8.

[0019] FIG. 10 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 9.

[0020] FIG. 11 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 10.

[0021] FIG. 12 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 11.

[0022] FIG. 13 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 12.

[0023] FIG. 14 is a view of the FIG. 1 wafer fragment at a processing step subsequent to that shown by FIG. 13.

[0024] This disclosure of the invention is submitted in furtherance of the constitutional purposes of the U.S. Patent Laws “to promote the progress of science and useful arts” (Article 1, Section 8).

[0025] In accordance with one aspect of the invention, a method of forming DRAM circuitry on a semiconductor substrate having complementary metal oxide semiconductor field effect transistors and associated capacitors comprising the following steps:

[0026] defining a memory array area on a substrate for formation of first conductivity type DRAM field effect transistors and defining an area peripheral to the array on the substrate for formation of second conductivity type field effect transistors;

[0027] providing a plurality of patterned gate lines within the memory array area and the peripheral area, the gate lines defining respective source areas and drain areas adjacent thereto;

[0028] providing capacitor storage nodes over selected array source areas;

[0029] providing a capacitor dielectric layer and an electrically conductive capacitor cell plate layer over the capacitor storage nodes and the peripheral area; and

[0030] in two separate photomasking and two separate etching steps, collectively etching the capacitor cell plate layer to substantially remove cell plate material from the peripheral area and provide bit line contact openings through the capacitor cell plate layer to selected drains in the array area.

[0031] In another aspect of the invention, a method of forming DRAM circuitry on a semiconductor substrate having complementary metal oxide semiconductor field effect transistors and associated capacitors comprising the following steps:

[0032] defining a memory array area on a substrate for formation of first conductivity type DRAM field effect transistors and defining an NMOS peripheral area and a PMOS peripheral area;

[0033] providing a plurality of patterned gate lines within the memory array area and the peripheral areas, the gate lines defining respective source areas and drain areas adjacent thereto;

[0034] providing capacitor storage nodes over selected array source areas; providing a capacitor dielectric layer and an electrically conductive capacitor cell plate layer over the capacitor storage nodes and the peripheral areas; and

[0035] in two separate photomasking and two separate etching steps, collectively, a) etching the capacitor cell plate layer to substantially remove cell plate material from the NMOS peripheral area and thereafter doping the NMOS peripheral area with n-type material, and b) etching the capacitor cell plate layer to substantially remove cell plate material from the PMOS peripheral area and thereafter doping the PMOS peripheral area with p-type material.

[0036] Referring first to FIG. 1, a wafer fragment in process is indicated generally with reference numeral 10. Such comprises a bulk monocrystalline silicon substrate 12 having a p-well 13 for provision of NMOS circuitry and an n-well 14 for provision of PMOS circuitry. For purposes of the continuing discussion, wafer fragment 10 comprises a memory array area 15 for formation of first conductivity type DRAM field effect transistors and first peripheral area 16 and second peripheral area 17 outside of or peripheral to array area 15 for formation of first and second conductivity type transistors, respectively. In the preferred embodiment, the array transistors will comprise NMOS transistors, with the first conductivity type thus being n and the second conductivity type being p.

[0037] A gate oxide layer 18, conductively doped polysilicon layer 19, silicide formed layer 20, and insulating oxide layer 21 are provided. Example respective thicknesses include 130 Angstroms, 1250 Angstroms, 1200 Angstroms, and 2750 Angstroms.

[0038] Referring to FIG. 2, layers 19, 20 and 21 are patterned to provide a plurality of patterned gate lines 22 within memory array area 15, first peripheral area 16, and second peripheral area 17. Gate lines 22 define respective source areas and drain areas adjacent thereto which will be subsequently doped for providing desired transistor diffusion regions. For purposes of the continuing discussion, areas 24 within memory array area 15 comprise source areas which will ultimately be utilized for forming source regions which ohmically electrically connect with the storage node plates of respective DRAM capacitors. Area 25 within memory array area 15 comprises a drain area which will ultimately be utilized for forming a drain region within the substrate and ohmically electrically connect with a bit line. Likewise, areas 28 and 29 in first peripheral area 16 comprise respective source and drain regions therein, while areas 26 and 27 within second peripheral area 17 comprise respective source and drain areas therein. The positions of 26 and 27 could be swapped, as well as those of 28 and 29, depending upon selective operation of the circuitry as to whether one diffusion region functions as a source or as a drain. Nomenclature within array area 15 is used in its art accepted sense, wherein it is generally accepted that the source of a field effect transistor in a DRAM cell connects with the capacitor, whereas the drain within such a cell connects with the bit line.

[0039] Referring to FIG. 3, a first layer 30 of insulating (oxide) material, such as SiO₂, is deposited, followed by provision of a second oxide layer 32. Example thicknesses for each of layers 30 and 32 are 1500 Angstroms. Such layers might comprise the same or different materials such as one or a combination of doped or undoped oxides. Accordingly, even if layers 30 and 32 comprise doped or undoped oxide, each would comprise the same predominant oxide material. Layers 32 and 30 in the preferred embodiment comprise or define a composite insulating dielectric layer 33 within array area 15, first peripheral area 16 and second peripheral area 17 over gate lines 22, source areas 24, 28, 26, and drain areas 25, 27. Layers 30 and 32 are typically provided in conjunction with other wafer processing not particularly pertinent to this invention. For example, such would typically be utilized for masked n-type LDD and/or NMOS halo implants or masked p-channel halo and/or p-channel LDD implants. Other processing could also occur, such as by way of example only, source/drain reoxidation. Such are common and typical in high performance CMOS transistor fabrication, but are not otherwise referred to herein as not being particularly material to that which is claimed as invention. Nevertheless, layers 30 and 32 (or collectively composite layer 33) do provide a partial etch stop or a buffering function in subsequent processing in accordance with certain aspects of the invention, which will be apparent from the continuing discussion.

[0040] Referring to FIG. 4, a layer 34 of photoresist is deposited and patterned as shown for outwardly exposing selected source areas 24 within array area 15. Insulating dielectric layer 33 is then etched as shown.

[0041] Referring to FIG. 5, photoresist masking layer 34 is removed and an electrically conductive capacitor storage node layer 36 provided over patterned insulating dielectric layer 33. Such preferably comprises heavily conductively doped polysilicon having an example dopant concentration of at least 1×10²⁰ions/cm³.

[0042] Referring to FIG. 6, capacitor storage node layer 36 is patterned and etched to define respective capacitor storage nodes 38 over selected array source areas 24, with the storage node etching effectively stopping relative to insulating dielectric layer 33. For example, the etch utilized to define storage nodes 38 is typically highly selective at a 5:1 or higher ratio of removal rate of silicon relative to oxide. However, considerable over-etching is preferably conducted because of the wafer topography, and may result in substantially etching through outer insulating dielectric portion 32 but substantially not through insulating dielectric portion 30 in spite of the 5:1 selectivity. Regardless of whether stopping occurs relative to layer 30, some of composite layer 33 should remain after the FIG. 6 etch.

[0043] Referring to FIG. 7, a capacitor dielectric layer 40 and an electrically conductive capacitor cell plate layer 42 are provided over capacitor storage nodes 38 and first peripheral area 16 and second peripheral area 17. An example and preferred material for layer 40 would be a nitride, or an O—N—O composite, having an overall thickness of 90 Angstroms. The preferred material for layer 42 is conductively doped polysilicon, with an example thickness being from about 500 Angstroms to about 1000 Angstroms. Thus, DRAM array capacitors 44 are substantially formed.

[0044] Referring to FIG. 8, a layer of photoresist is deposited and patterned as shown to cover array storage nodes 38 and to cover second peripheral area 17, while leaving selected drain areas 25 within array area 15 and the first peripheral area 16 unmasked, with such processing hereinafter being referred to as a first photomasking. Alternately but less preferred (not shown), layer 46 can be patterned such that at this point in the process drain areas are not exposed and remain masked.

[0045] Referring to FIG. 9 and with first photomasking 46 in place, capacitor cell plate layer 40 and underlying layers are first etched to effectively expose selected array drain areas 25 as well as first peripheral area 16.

[0046] Referring to FIG. 10 and with first photomasking 46 still in place, first conductivity type dopant impurity (in the described example, “in”) is implanted into selected array drain areas 25 and first peripheral area 16 to form conductively doped array drain regions 50 and conductively doped first peripheral area source and drain regions 52 and 54, respectively. Alternately, layer 46 could be stripped for an n-type implant since in such instances layer 40 typically comprises n-type doped polysilicon and masking thereof is not necessary. Regardless, in a single and common masking step, cell plate layer 42 is patterned and etched to effectively outwardly expose drain areas within a DRAM array, and ion implanting is then conducted into the DRAM array drain areas to form electrically conductive drain regions within the substrate in the array area.

[0047] Selected array source areas 24 are also conductively doped at some point in the process with first conductivity type material to define electrically conductive first type source regions 56 within substrate 12 in array area 15. Preferably, such conductively doping to provide conductively doped source regions 56 consists essentially of out-diffusion of first conductivity type dopant impurity from capacitor storage node layer 36. Therefore in accordance with the preferred embodiment, the memory array drain areas and the peripheral circuitry area source and drain areas are conductively doped to provide the desired high concentration diffusion regions after formation of the DRAM array capacitors 44.

[0048] Referring to FIG. 11, first photomasking 46 (not shown) is removed and a second photomasking layer 60 is provided to cover array area 15 and first peripheral area 16 while leaving second peripheral area 17 exposed. Second masking layer 60 preferably overlaps with a portion 62 of second peripheral area 17, and thereby a portion of capacitor cell plate layer 42 and capacitor dielectric layer 40 in second peripheral area 17.

[0049] Referring to FIG. 12 and with second photomasking 60 in place, capacitor cell plate layer 42 and underlying layers are second etched from second peripheral area 17. This second etching step leaves a composite hedge or block 64 of capacitor cell plate layer 42 and capacitor dielectric layer 40 relative to an interface 65 of array area 15 and second peripheral area 17.

[0050] Referring to FIG. 13 and with second photomasking 60 still in place, second conductivity type dopant impurity (in this example p-type) is implanted into source areas 26 and drain areas 27 in second peripheral area 17 to form conductively doped second peripheral area drain and source regions 68 and 70, respectively. Accordingly in the preferred embodiment, the collective steps of, a) first and second etching capacitor cell plate layer 42, b) first conductivity type implanting into peripheral area 16, and c) second conductivity type implanting into peripheral area 17 are conducted with no more photomasking steps than said first and second photomaskings. The prior art utilizes three separate photomasking steps for such collective steps when all NMOS and PMOS gates are defined in a single photomasking step. Most preferably in accordance with the invention, the above item “b” also includes first conductivity type implanting into array area 15 in the same step where selected array drain areas have been exposed in conjunction with exposure of peripheral n-type areas.

[0051] Referring to FIG. 14, photomasking 60 is removed and an insulating dielectric layer 72 deposited and patterned to provide a bit contact opening 74 to memory array drain region 50. Subsequently, a conductive material layer 76 is deposited and patterned to effectively form a bit line which ohmically electrically connects with drain region 50.

[0052] Further in accordance with an aspect of the invention, the capacitor cell plate layer is removed from the peripheral area and bit line contacts openings provided through the capacitor cell plate layer to selected drains in the array area in two separate photomasking and two separate etching steps. The prior art heretofore conducts patterning and removal of the cell plate layer in a single masking and etching step.

[0053] The above described embodiment with reference to the figures was with respect to a preferred embodiment bit line over capacitor array construction. However, the invention in its broadest aspects also contemplates fabrication of capacitor over bit line constructions.

[0054] In compliance with the statute, the invention has been described in language more or less specific as to structural and methodical features. It is to be understood, however, that the invention is not limited to the specific features shown and described, since the means herein disclosed comprise preferred forms of putting the invention into effect. The invention is, therefore, claimed in any of its forms or modifications within the proper scope of the appended claims appropriately interpreted in accordance with the doctrine of equivalents.