Bistable reflective cholesteric liquid crystal displays utilizing super twisted nematic driver chips

[0003] This invention relates to the operation of liquid crystal displays. In particular, the present invention relates to a driving circuit for operating a cholesteric liquid crystal display. Specifically, the present invention relates to a driving circuit employing specially modified drivers that are normally used in super twisted nematic liquid crystal displays.

[0004] Cholesteric liquid crystal materials are known and disclosed in U.S. Pat. Nos. 5,437,811; 5,695,682; 5,453,863; and 5,691,795, all of which are assigned to the assignee of the present invention and which are incorporated herein by reference. The primary advantage of the bistable cholesteric liquid crystal materials disclosed in these patents is that they can be driven to a desired texture with application of a voltage and remain in that texture after removal of the applied voltage. As seen in FIG. 1, bistable cholesteric liquid crystal materials are known to exhibit at least four states or textures: homeotropic, focal conic, transient planar, and planar. Both the homeotropic and transient planar textures are considered transitory and do not remain after removal of an electric field. These transitory textures are employed to facilitate the transformation of the cholesteric liquid crystal material into either a weakly light scattering, transmissive focal conic texture or a reflective planar texture.

[0005] The next step in the development of bistable cholesteric liquid crystal devices was focused on how to drive the cholesteric liquid crystal material quickly between the focal conic and planar textures. This development is necessitated by the desire to provide efficient operation of the device, with as fast as possible update rates. Such driving schemes are found in U.S. Pat. No. 5,748,277, and in U.S. patent application Ser. No. 08/852,319, both of which are owned by the assignee of the present invention and which are incorporated herein by reference. Initially, a three phase dynamic drive scheme, as shown in FIGS. 2A and 2B, was employed to control the appearance of the cholesteric device. As is discussed in the above patents, the liquid crystal material is disposed between two substrates, one of which has a plurality of row electrodes and the other which has a plurality of column electrodes orthogonal to the row electrodes. Application of voltage waveforms to the electrodes is multiplexed or applied in a predetermined sequence. Hence, these displays are sometimes referred to as multiplexed displays. Those skilled in the art will appreciate that multiplexed displays are not limited to “row and column” electrode patterns. Segmented liquid crystal displays, such as clock faces and calculator displays, may also be multiplexed. In either type of display the term “common electrode” may be used to refer unto a row electrode, and the term “segment electrode” may be used to refer to a column electrode.

[0006] The liquid crystal material in between the intersecting electrodes form a pixel. As shown in FIGS. 2A and 2B, the appearance of each pixel is controlled by a pixel voltage waveform which comprises a sequence of three RMS voltages: V_preparation, V_{select/non-select}, and V_evolve. V_preparationor V_pdrives the cholesteric liquid crystal material into the homeotropic texture regardless of its initial texture. Application of V_{select/non-select}or V_s/nsdetermines if the homeotropic texture relaxes into the planar (V_select) or the focal conic texture (V_non-select). The evolution voltage or V_eserves two functions. First, it permits the focal conic texture to evolve from the transient planar texture that results from applying V_non-select. The evolution voltage also restores and maintains the homeotropic texture after V_selectis applied allowing relaxation to the planar texture which occurs when V_evolveis removed. It has been determined that display update speed can be increased by applying the voltages V_preparationand V_evolveacross many rows simultaneously. Once V_evolveis removed from the last addressed row, all power is removed from the display and the desired indicia appears on the display.

[0007] Implementation of such a drive scheme has proven to be quite costly. In particular, previous displays required 50-60V (RMS) to drive the cholesteric liquid crystal material into the homeotropic texture from which it relaxes into the reflective planar texture. Since the use of cholesteric liquid crystal materials in displays is relatively new, there are no commercially available electronic driving circuits uniquely designed to apply the necessary voltage waveforms to a display.

[0008] One option that was initially investigated was to employ a multiplexed super twisted nematic (STN) display driver. STN displays are addressed constantly so that each pixel always has an applied voltage across it that is the combination of waveforms being applied to the appropriate intersecting electrodes. The “state” or texture of a particular pixel (on or off, light or dark) depends on the average voltage across the pixel during a single scan or update of the display. The difference between the average voltages of these two pixels states is small, on the order of about 0.1 volt. This difference is generated entirely by the choice of voltage, either high or low, applied to the pixel while it is selected for update. The number of DC voltage levels required to drive a STN display is relatively small. Four voltage levels are required for each common/row and segment/column waveform and typically, two of these voltage levels are common to both. Accordingly, only six distinct DC voltage levels, which are separate from the logic voltage inputs, are required to address an STN display. STN driver chips also include a data input called the frame line that selects between two fixed pairs of display voltage inputs for all the outputs on a chip. For example, if the display voltage inputs are labeled V₁, V₂, V₃, and V₄, the frame line can select between either the pair V₁and V₂or the pair V₃and V₄. No other selections are possible. Of course other label designations could be used for the voltage inputs. Each STN driver chip also includes a shift register containing one data bit per chip output. Each bit selects one of the two display voltage inputs selected by the frame line. Accordingly, each bit can select between V₁and V₂or between V₃and V₄. Once again, no other selections are possible. The voltages applied to the display voltage inputs must obey strict rules. At a minimum, the rule (V₄≧V₃≧V₂≧V₁) must be obeyed. Moreover, it is typical to require two of the four display voltage inputs (V₃and V₄) to be set very near to the chip's upper supply voltage while the other two display voltage inputs (V₁and V₂) are set very near the chip's lower supply voltage. These requirements are intended to ensure proper chip operation and are primarily a function of the chip design.

[0009] Although it was desired to employ the STN driver chips to drive the cholesteric liquid crystal display because of their relatively low cost (about 2 cents per output), it was readily apparent that the drive scheme requirements of cholesteric liquid crystal displays were significantly more severe than super twisted nematic displays. The state of a STN pixel depends only on the average voltage across the pixel during a single update of the display and not on the specific sequence of voltages applied to the pixel. While cholesteric liquid crystal displays respond to the average voltages applied to them, the state of a pixel depends on the sequence of RMS/average voltages applied during an update. As noted previously, the dynamic address scheme requires the proper application of RMS voltages V_p, V_s/ns, and V_ein order to select between the two stable cholesteric liquid crystal textures. The only known way to address cholesteric liquid crystal displays with the dynamic drive scheme was to employ high voltage analog switches to generate the necessary row waveforms.

[0010] A first attempt at employing STN drivers resulted in providing half of the signals needed to drive a cholesteric liquid crystal display. In this approach, the STN driver chips were employed to generate the column waveforms and high voltage analog switches were employed to generate the row waveforms. The row waveforms were AC waveforms, and the necessary RMS voltages were generated entirely by these row waveforms. The column waveforms supplied by the segment/column drivers were of small amplitude and amounted to inconsequential noise on all rows except the row being addressed. On the row being addressed, the row waveform voltage levels were comparable to the column waveform (data) voltage levels. As such, the proper select and non-select voltages could be generated by changing the phase of the column waveforms.

[0011] The fundamental characteristic of STN driver chips that led to this hybrid mixture of driver chips and analog switches is that STN driver chips are “unipolar,” that is, the output voltages can range, for example, from 0-40 volts, as opposed to “bipolar” wherein the output voltages would range from −40V to +40V. It was not thought possible to generate the necessary RMS voltages given the limited voltage range of STN drivers, typically no more than 40 volts, versus the 200 volts required for the analog switches used in the initial embodiment. In particular, the initial embodiment was designed so that one high voltage analog switch chip was needed to drive every two rows. At eight switches per chip, four separate analog switches controlled each row. Accordingly, a four inch by four inch display used in the initial embodiment had 320 rows, so 160 of the high voltage analog switch chips were required. This forced the cost of the drivers alone to over $3,000.00. Although the drivers in association with the other circuitry were effective in driving the display, it was quite cost prohibitive. Moreover, scaling up to a page-size display at a reasonable resolution (133 DPI) was clearly out of the question in attempting to develop a commercially cost-effective cholesteric display.

[0012] It is thus an object of the present invention to provide a low-cost dynamic drive circuit for multiplexing a bistable reflective cholesteric liquid crystal display using drivers originally designed for super twisted nematic displays.

[0013] It is another object of the present invention to provide a drive circuit which employs up to 8 different voltage levels which can range anywhere from 0 to 80 volts.

[0014] It is a further object of the present invention to provide a multiplexing drive circuit and method for use, as above, in which common and segment drivers are coupled to corresponding common and segment electrodes which are employed to drive the liquid crystal material disposed between a pair of substrates.

[0015] It is yet another object of the present invention to provide the drive circuit and method for use, as above, in which each common and segment driver contains at least two frame switches, each of which has a high and low input which receives voltage waveforms that are transferred to a plurality of data switches which in turn are coupled to respective electrodes.

[0016] It is yet another object of the present invention to provide the drive circuit and method for use, as above, in which a frame line is employed to toggle the frame switches in each of the drivers to select a voltage input pair which can be applied to the display.

[0017] It is still another object of the present invention to provide the drive circuit and method for use, as above, in which at least one of the frame switches in the common and segment drivers has two of its inputs connected to one another, thereby allowing an arbitrary waveform to be submitted to the corresponding electrodes.

[0018] It is still a further object of the present invention to provide the drive circuit and method for use, as above, in which each common and segment driver has a plurality of data switches which direct one of the frame switch outputs to the appropriate electrodes.

[0019] It is an additional object of the present invention to provide a driving circuit and method for use, as above, in which one of the row frame switches receives three different voltage values so that the indicia appearing on the display appears row by row.

[0020] It is still yet another object of the present invention to provide a driving circuit and method for use, as above, in which one of the row frame switches receives two different voltage values so that the indicia appearing on the display appears all at once.

[0021] The foregoing and other objects of the present invention, which shall become apparent as the detailed description proceeds, are achieved by a bistable cholesteric liquid crystal display, comprising a pair of opposed substrates, one substrate having a first plurality of electrodes, the other substrate having a second plurality of electrodes oriented in a direction different than the first plurality of electrodes, a cholesteric liquid crystal material disposed between the pair of opposed substrates and forming a pixel at each intersection of the first and second plurality of electrodes, a first super twisted nematic driver having a plurality of outputs connected to the first plurality of electrodes, and a second super twisted nematic driver having a plurality of outputs connected to second plurality of electrodes, wherein both the drivers receive a plurality of voltage input waveforms for selective transmission to first and second plurality of electrodes.

[0022] Other aspects of the present invention are attained by a method for addressing a bistable cholesteric liquid crystal display which has a pair of opposed substrates, one of the substrates having a first plurality of electrodes, the other substrate having a second plurality of electrodes oriented in a direction different than the first plurality of electrodes, the substrates having cholesteric liquid crystal material disposed therebetween to form a pixel at each intersection of the first and the second plurality of electrodes, the first plurality of electrodes having at least a first driver coupled thereto and the second plurality of electrodes having at least a second driver coupled thereto, the method comprising the steps of applying a plurality of voltage input waveforms to the first driver and the second driver, wherein the voltage input waveforms are 50 volts or less, selectively transmitting the plurality of voltage input waveforms through the first and the second drivers to generate respective first and second output waveforms, and combining the first and second output waveforms at the intersecting electrodes to generate a pixel waveform that drives the cholesteric liquid crystal material to the desired appearance.

[0023] Still other aspects of the present invention are attained by a driving circuit for a reflective bistable cholesteric liquid crystal display which includes one substrate having a first plurality of electrodes opposed by another substrate having a second plurality of electrodes, wherein the intersection of the first and the second plurality of electrodes with cholesteric liquid crystal material disposed therebetween form a plurality of pixels, the driving circuit selectively applying voltages to the first and the second plurality of electrodes to control the appearance of each pixel, the driving circuit comprising at least one common driver coupled to the first plurality of electrodes, each common driver having a first and a second common frame switch, each common frame switch having a high input and a low input, first and second frame switches linked to one another by a common frame line, the frame switch outputs connected to a plurality of common data switches, each common data switch having an output, the first common frame switch receiving a first and a second common voltage input and the second common frame switch receiving a third and a fourth common voltage input connected to each other, wherein the common frame line is toggled to selectively pass through the common voltage inputs for use as the common voltage output from each common data switch, and at least one segment driver coupled to the second plurality of electrodes, at least one segment driver having a plurality of segment voltage outputs which are selectively applied to the second plurality of electrodes to drive the cholesteric liquid crystal material to a desired texture.

[0024] Yet other aspects of the present invention are attained by a method for addressing a liquid crystal display having a plurality of common electrodes oriented differently with respect to a plurality of segment electrodes with cholesteric liquid crystal material disposed therebetween, the method comprising the steps of connecting at least one common driver to the plurality of common electrodes, connecting at least one segment driver to the plurality of segment electrodes, and toggling a pair of frame switches in each common and segment driver such that a first of the pair of frame switches applies one of two waveforms to the corresponding electrodes or such that a second of the pair of frame switches applies an arbitrary waveform to the corresponding electrodes.

[0025] These and other objects of the present invention, as well as the advantages thereof over existing prior art forms, which will become apparent from the description to follow, are accomplished by the improvements hereinafter described and claimed.

[0026] For a complete understanding of the objects, techniques and structure of the invention, reference should be made to the following detailed description and accompanying drawings, wherein:

[0027] FIG. 1 is a schematic representation of the various textures of a cholesteric liquid crystal as they appear in a display;

[0028] FIGS. 2A and 2B are exemplary dynamic drive voltage sequences for driving cholesteric liquid crystal material to either a focal conic or planar texture;

[0029] FIGS. 3A and 3B are four phase dynamic drive schemes of the present invention;

[0030] FIG. 4 illustrates the unipolar component waveforms of the dynamic drive scheme that are applied in each mode of the present invention without showing the row and column preparation waveforms which are simply square waves running rail to rail;

[0031] FIGS. 5A-C illustrate the combination of the component waveforms of FIG. 4 to show the typical column, row, and pixel waveforms, respectively, employed in the present invention;

[0032] FIG. 6 is a block diagram for a common driver employed in a driving circuit of the present invention in which a scan mode is employed;

[0033] FIG. 7 is a block diagram for a common driver employed in a driving circuit of the present invention in which a flash mode is employed;

[0034] FIG. 8 is a block diagram for a segment driver employed in a driving circuit of the present invention;

[0035] FIG. 9 is a four by four pixel display showing how such a display would appear according to the waveforms provided in FIGS. 6-8; and

[0036] FIG. 10 is a block diagram according to the present invention showing both common and segment drivers.

[0037] The present invention is employed with cholesteric liquid crystal displays which in and of themselves are quite simple to manufacture. These displays are typically opposed substrates of either glass or plastic. Patterned indium tin oxide electrodes are disposed on one substrate as common/row electrodes and are disposed on the other substrate as segment/column electrodes. The common and segment electrodes are positioned in different directions with respect to one another to form pixels which can be individually addressed by applying voltages to both. The indium tin oxide is usually overlaid with a barrier coat and an alignment layer. Spacing between the substrates is typically between 4 μm to 5 μm. Commercially available materials and standard fabrication techniques are employed to manufacture the displays.

[0038] As noted in the Background Art, cholesteric displays are typically driven into the homeotropic texture by applying bipolar waveforms, average value of about 50-60 V_RMS, to a plurality of rows with high voltage electronics. Given the unipolar output range of super twisted nematic driver chips (nominally 0-40 volts), it was evident that the dynamic drive scheme would need to be revised to a differential drive scheme. In other words, the necessary large RMS voltages can only be generated across the display by proper combination of large amplitude row and large amplitude column waveforms. Moreover, the display design had to be modified to lower the maximum RMS voltage required to drive the display into the homeotropic texture to about 40 volts. Yet another limitation of STN driver chips is that their logic allows only two of the four display voltage inputs to be applied to a display at one time by a single driver chip. Accordingly, the dynamic drive scheme shown in FIGS. 2A and 2B needed to be modified to “fit” onto the common/row driver chips by breaking it into two parts. The first part of this modified dynamic drive scheme applied V_preparationto all pixels in all rows simultaneously, driving the entire display into the homeotropic texture. The second part begins by applying a “holding” voltage (whose value is less than V_preparation) to all pixels not being addressed in order to maintain their homeotropic textures until those pixels can be addressed. This “break up” of the dynamic drive scheme is implemented by having the common driver chips function in one of three operating modes while requiring the segment driver chips to function in one of two additional operating modes.

[0039] The most significant consequence of breaking up the original dynamic drive scheme is the addition of a new application voltage to the RMS pixel waveform in order to “hold” the cholesteric liquid crystal material in the homeotropic texture after applying the preparation voltage V_p. As seen in FIGS. 3A and 3B, the evolution voltage is now provided along with a holding voltage which is designated as V_h/e. Accordingly, a pixel sees a voltage waveform that produces a sequence of four RMS voltages, V_preparation, V_hold, V_{select/non-select}, and V_evolve. V_holdis a voltage value that is applied to a pixel in the homeotropic texture prior to it being addressed with V_{select/non-select}. In other words, a pixel waveform is the resulting waveform produced at any pixel by combining output waveforms at the respective electrodes. All other RMS voltages shown in FIGS. 3A and B serve the same function as they did for the original dynamic drive scheme. All of the voltage values associated with the drive scheme are dependent upon the particular cholesteric material used and the design of the display. As such, any voltage value discussed herein is exemplary and not meant to be limiting.

[0040] The drive scheme of the present invention requires the common driver chips to function in one of three operating modes and the segment driver chips to function in one of two additional operating modes as seen in FIG. 4. In each operating mode, the driver chips apply different monopolar component output waveform combinations to the display electrodes. The common and segment input preparation waveforms are simply square waves running rail to rail and are not shown. The two segment operating waveforms are segment select and segment non-select. The three common input operating waveforms are common hold/evolve, common select, and common non-select. Those skilled in the art will appreciate that the RMS value of the hold/evolve and data waveforms provided to the pixel are properly independent of the segment waveforms. Combination of the input waveforms shown in FIG. 4 generate the segment output waveform shown in FIG. 5A, the common output waveform shown in FIG. 5B, and the pixel waveform shown in FIG. 5C. The pixel waveform is a result of the difference between the common and segment waveforms. Accordingly, the pixel is prepared, held, written to, evolved, and then turned off, whereupon the desired appearance of the pixel is displayed.

[0041] Referring now to FIGS. 6-8, implementation of the input, output and resulting pixel waveforms for cholesteric displays is accomplished by using standard, off-the-shelf, low cost super twisted nematic drivers. FIGS. 6-8 are simply graphical representations of the functionality of the driver chips for selectively transmitting input waveforms (shown to the left of the chip) to obtain the desired output waveforms (shown to the right of the chip). The output waveforms from row/column driver(s) and the column/segment drivers are then combined at the pixel to form the pixel waveforms. The drivers shown herein are not meant to be an accurate representation the internal design or construction of an STN driver. Rather, these block diagrams are meant to be a representation of the logic of the driver showing how the driver's display voltage inputs can be routed to the driver's outputs. As such, the “switches” drawn in the figure are not real, physical switches, but they do represent the functionality of the circuitry of the driver.

[0042] In FIG. 6, a common driver according to the present invention is generally indicated by the numeral 40. As shown, the driver 40 can be thought of as an analog multiplexer with four voltage inputs and anywhere from 80 to 160 outputs. For simplicity sake, only four outputs are shown in the drawing. In FIG. 6, the common driver 40 has four inputs which are arbitrarily designated as V₀, V₅, V₂, and V₃.

[0043] The common driver 40 includes a pair of frame switches 42 wherein each frame switch has an alphabetic suffix. As such, the common driver 40 has a frame switch 42aand a frame switch 42b. Each frame switch 42 incorporates a high input 44 and a low input 46. As such, the frame switch 42ahas a high input 44aand a low input 46a. The frame switches 42aand 42bare coupled to one another by a frame line 48 which is ultimately controlled by a digital control circuit (not shown) that may include a microprocessor. It will be appreciated that the digital control circuit associated with the driver chips contains the necessary hardware, software and memory to fully implement the objects of the present invention.

[0044] Connected to the outputs of each frame switch 42 are a plurality of data switches 50, each of which has an alphabetic suffix. Each data switch 50 has a high input 52 and a low input 54, both of which have a corresponding alphabetic suffix. Selection of the high input 52aor low input 54ais controlled by a data shift register within the driver and the data shift register is ultimately controlled by the digital control circuit. Depending upon the input voltages, the toggling of the frame line 48 and the data bits controlling the data switches 50, a data output 56 with a corresponding alphabetic suffix is generated by each data switch.

[0045] A modification to the common driver 40, which allows implementation of the dynamic drive scheme, is attained by electrically connecting the voltage inputs V₂and V₃of frame switch 42bto one another to form a super input 58. The super input 58 allows an arbitrary waveform that conforms to the display voltage input rules mentioned in the Background Art to be piped to a single output or to multiple outputs of the common driver 40 while the other outputs of the driver 40 swing rail to rail as the frame line 48 is toggled. If the receiving data switch 50 is set to a high input 52, the data output 56 will be either voltage input V₀or V₅, depending upon the state of the frame line 48. If the receiving data switch 50 is set to the low input 54, the data output will be the arbitrary waveform applied to the super input 58, regardless of the state of the frame line 48.

[0046] The common driver 40 presented in FIG. 6 is employed in a “scan mode” that updates the display row by row. The particulars of this mode are discussed below. In order to implement this mode, three different voltage values (V_n/s, V_s+, V_s−) must be supplied to the super input 58.

[0047] Referring now to FIG. 7, it can be seen that the common driver 40 may also receive a 2-level select waveform at the superinput 58. This allows for a “flash mode update” wherein the entire image appears on the display all at once. The superinput 58 receives either a voltage value of V_s+ or V_s− during the selection phase. The particular aspects of this mode are also discussed below. In all other respects, the common driver shown in FIG. 7 is substantially the same as the common driver shown in FIG. 6.

[0048] Referring now to FIG. 8, a segment driver designated generally by the numeral 70, is presented. The segment driver 70 is employed in either the scan mode or the flash mode. While the row or common electrodes apply the majority of the pixel waveform, the segment or column output waveforms supply the data that combines with the row select waveform during the select phase to apply a high or low selection voltage value to the pixel. Accordingly, the cholesteric liquid crystal material is driven to the texture corresponding to the high or low selection data voltage.

[0049] The segment driver 70, much like the common driver 40, includes frame switches 72aand 72b, each of which has a high input 74 and a low input 76 with corresponding alphabetic suffixes. The frame switches 72aand 72bare coupled to one another by a frame line 78. Receiving the output generated by the frame switches 72 are data switches 80, each of which has an alphabetic suffix. The data switches 80 each have a high input 82 and a low input 84, wherein each output 86 has a corresponding alphabetic suffix. As with the common drivers, the segment driver 70 contains a data shift register that controls the selection of the high input 82 or the low input 84 of the data switches 80. Toggling of the frame line 78 and setting of the data switches 80 is ultimately controlled by the digital control circuit. The voltage input V_Oreceives preparation voltage V_p+ while voltage input V₅receives preparation voltage V_p− or data voltage V_d−. Inputs V₂and V₃are electrically connected to form superinput 88 that receives data voltage V_d+. The digital control circuit associated with the driving circuit sequences application of the various segment waveforms in much the same manner as the common waveforms. As seen in the resulting segment waveforms for the corresponding outputs of the data switches 80, the preparation voltages are applied during the preparation phase while the data voltages are applied thereafter. Accordingly, depending upon whether the data voltage applied is V_d− or V_d+, simultaneous with the application of the selection voltages to the row electrodes, the resulting planar or focal conic textures are obtained.

[0050] The digital control circuit controls the sequencing of the common and segment drivers to obtain the desired image appearance. As seen in FIGS. 6-8, the digital control circuit controls the drivers 40 and 70 to simultaneously apply the preparation voltages during a first phase, the hold/select/evolve and data voltages during a second phase and the evolve, non-select and pseudo data voltages during a third phase.

[0051] It must be stated at this time that the only way for all pixels in all rows of a bistable cholesteric display to be properly prepared (driven into the homeotropic texture) is for those pixels to be driven into the homeotropic texture simultaneously. This simultaneity is mandated by the differential nature of the revised dynamic drive scheme and the SIN driver logic.

[0052] The only way to generate the necessary large RMS voltages of the preparation phase of the pixel waveform is for the segment driver 70 to apply the segment preparation waveform to the segment electrodes while the common driver 40 applies the common preparation waveform to the common electrodes. Once the segment driver 70 begins applying the data waveforms to the segment electrodes, the preparation phase of the pixel waveform is no longer generated even if the common driver 40 still applies the common preparation waveform to the common electrodes. Likewise, if the common driver 40 begins applying the hold/evolve waveform, the select waveform, or the non-select waveform, the preparation phase of the pixel waveform is no longer generated even if the segment driver 70 still applies the segment preparation waveform.

[0053] The logic of the STN common driver prevents the simultaneous output of the common preparation waveform and any other common output waveform on a single driver.

[0054] Consequently, in order to generate properly the preparation phase of the pixel waveform, all segment driver outputs must apply the segment preparation waveform to the segment electrodes while all common driver outputs are applying the common preparation waveform to the common electrodes. This requirement holds regardless of the number of common or segment STN drivers connected to a bistable cholesteric liquid crystal display.

[0055] The common driver 40 initially controls application of the preparation phase by setting the data switches 50 to the high input to receive the preparation voltage V_p+ or V_p−. As best seen in the common or row output waveforms, the preparation section shows application of V_p+ or V_p−. This is accomplished by toggling frame switch 42abetween its high and low inputs, with all the data switches 50 toggled to their high input 52. During this phase, the segment driver 70 outputs V_p−or V_p+, to the segment or column electrodes. As a result, the difference between the intersecting common and segment electrodes is applied to the pixel. In particular, the frame switch 72 is toggled between the high input 74 and the low input 76, with all the data switches 80 toggled to their high input 82.

[0056] In the hold/select/evolve section of the common or row output waveforms, it can be seen that initially row 0 receives one cycle of V_s+ and V_s− from the superinput 58 by virtue of the data switch 50abeing toggled to the low input 54a. Simultaneously, all other data switches are toggled to their respective high inputs 52 to receive either V_h/e+ or Vb_h/e− depending upon toggling of the frame line 48 that places the frame switch 42aat either the high input 44aor the low input 46a. Once the application of the selection voltage is complete for row 0, the data switch 50ais then set to the high input 52aso that the evolution phase may begin. Upon completion of the application of the selection voltage to row 0, data switch 50bis set to the low input 54bto apply V_s+ and V_s− for one cycle to row 1. The above process is then repeated to complete the hold/select/evolve section of the waveform for row 1 and the remaining rows. During this phase, the segment driver 70 outputs V_d− or V_d+ to the segment or column electrodes. In particular, the data switches 80 are toggled between their high inputs 82 and low inputs 84, as selectively determined by the digital control circuit, to apply either V_d+ and V_d− in the appropriate sequence to the columns 0-4 during application of V_s+ and V_s− by the common driver 40 to obtain the desired appearance of all pixels in the row being addressed.

[0057] Upon completion of the hold/select/evolve phase, frame switches 42 are toggled between high inputs 44 and low inputs 46 for a predetermined period for application of V_h/e, whereupon data switches 50 are toggled to a low input and V_n/sis applied to the rows in the scan mode. Shortly after voltage V_n/sis applied, all pixels in the row display the desired texture. As can be seen in row 1 of the output waveforms, the application of V_s+ and V_s− is one segment cycle and one-half common cycle removed from the application of V_s+ and V_s− in the row 0 output. Likewise, the application of V_s+ and V_s− in the outputs of rows 2 and 3 are removed from the preceding row by the same amounts during the hold/select/evolve phases.

[0058] One requirement of any liquid crystal display drive scheme is that the time-averaged voltage on every pixel be about 0 when averaged over some number of image updates. If the time average voltage across a pixel is not 0, ions in the liquid crystal material will migrate toward the electrodes. This ion migration will screen the voltage appearing on the pixel's electrodes, reduce the effective voltage across the pixel and change the switching properties of the pixel. Additionally, the electrodes can be permanently damaged if the migrating ions reach the electrodes. These changes are usually observed as image retention from one display update to the next. The dynamic drive scheme employed by the driving circuit of the present invention accomplishes this 0 average over two image updates by changing the phase of the hold/evolve waveform between 0 and 180 degrees on every image update. A 0-degree hold/evolve waveform begins high and halfway through its cycle changes to low. Conversely, a 180-degree hold/evolve waveform begins low and halfway through its cycle changes to high. As can be seen in FIG. 6, rows 1 and 3 develop a non-0 DC offset because the number of high half-cycles is not equal to the number of low half-cycles during the hold/evolve phases. Specifically, row 1 has three high half-cycles and two low half-cycles, and row 3 has four high half-cycles and three low half-cycles. On the next image update the phase of the hold/evolve waveform is changed 180 degrees so that row 1 will have two high half-cycles and three low half-cycles and row 3 will have three high half-cycles and four low half-cycles. Consequently, over two image updates a given row has an equal number of high and low half-cycles, and hence a 0 time-averaged voltage and 0 DC offset. Rows 0 and 2 naturally have 0 DC offset regardless of the phase of the hold/evolve waveform because the number of high half-cycles is always equal to the number of low half-cycles during the hold/evolve phases. Specifically, row 0 has two high half-cycles and two low half-cycles while row 2 has three high half-cycles and three low half-cycles.

[0059] As seen in FIG. 9, the combination of the output waveforms in FIG. 8 with the output waveforms of either FIG. 6 or FIG. 7 forces the material into focal conic textures for all column 0 pixels. Column 1 pixels are all focal conic except for row 1. While in column 2, all the pixels are focal conic except for row 0. In column 3, all the pixels are planar except for row 3. After application of the data voltages necessary to generate an image, a pseudo data voltage waveform is applied to the column electrodes while the evolve/non-select phase is applied to the row electrodes.

[0060] When the scan mode is desired, the waveform fed to the superinput 58 is three-level (V_n/s, V_s+, V_s−) and performs either the row select function or the row non-select function. The duration of the evolution phase is the same for all rows and the image update has the following appearance. First, the entire display is black for the duration of the preparation time plus the evolution time occurring after the pixels in the first row are addressed. Upon completion of the evolution phase, the pixels in the first row relax into their final stable states. Likewise, all the pixels in the second row addressed relax into their final stable states. These steps are then repeated until the pixels in all the addressed rows have arrived into their final reflective planar or transparent focal conic textures. After the evolution of the final row addressed is complete, all rows and columns are taken to an equal potential resulting in the voltage across pixel being driven to 0.

[0061] The total amount of time for the image update can be determined by the following equation:

[0062] Scan mode update time=Preparation Time+(Row Select Time)*(Total Number of Rows)+Evolution time

[0063] The minimum possible evolution time, given that all rows have equal select times is determined by:

[0064] Minimum Evolution Time=(Number of outputs per row chip−1)*(Row Select Time)

[0065] In the flash mode, the pixels in each row experience an evolution time that depends on when the row was addressed and hence on the total number of rows in the display. The waveform fed to the superinput 58 is only two-level and only performs the select function by applying V_s+ or V_s−. All rows evolve until the last row addressed receives the minimum evolve time necessary, which depends on the cholesteric liquid crystal material used. After the evolution of the final row addressed is complete, all rows and columns are taken to an equal potential resulting in the voltage across each pixel being driven to 0. Consequently, the image appears all at once on the display.

[0066] Flash mode addressing yields an image update with the following appearance. First, the whole display is black for the duration of the preparation time plus the row select time times the total number of rows plus the minimum evolution time. Next, the whole image appears on the display at once, with all planar pixels relaxing into their final reflective states simultaneously. The transparent focal conic pixels have already reached their final transparent stable states by the end of the evolution time and do not change their appearance.

[0067] Employing the segment and common drivers of the present invention, the following exemplary voltage values have been determined:

[0068] The relationship between these row and column waveform levels and the pixel voltage RMS values are as follows:

[0069] Preparation RMS Voltage:

[0070] V_PREP=V_p+ −V_p−

[0071] Hold/Evolve RMS Voltage:

[0072] V_H/E=[(V_h/e+ −V_d+)²+(V_h/e+ −V_d−)²+(V_h/e− −V_d+)²+(V_h/e− −V_d−)²]^½/2

[0073] V_H/E≅V_h/e+ −V_h/e−

[0074] Planar Texture Select Phase RMS Voltage (Column Data out of phase with Row Select waveform):

[0075] V_Planar=[(V_s+ −V_d−)²+(V_s− −V_d+)²]^½/sqrt(2)

[0076] Focal Conic Texture Select Phase RMS Voltage (Column Data in phase with Row Select waveform:

[0077] V_Focal=[(V_s+ −V_d+)²+(V_s− −V_d−)²]^½/sqrt(2)

[0078] In order to guarantee no DC offset across all the pixels in the display over two image updates, the following rules must apply to the voltage levels:

[0079] Referring now to FIG. 10, it can be seen that a driving circuit block diagram is designated generally by the numeral 100. The driving circuit 100 includes a plurality of common drivers 40 and a plurality of segment drivers 70.

[0080] The circuit produces the common and segment driver input waveforms of FIGS. 6, 7, and 8. Take note that this block diagram is not meant to be an accurate representation the design or construction of the drive circuit. Rather, it is meant to be a representation of the logic of the drive circuit showing how the DC voltages may be routed to the common and segment drivers'display voltage inputs.

[0081] The voltages V_h/e+, V_h/e−, V_s+, V_s−, V_n/s, V_d+, and V_d−, are DC voltages whose values and relationships have been previously stated.

[0082] A plurality of buffers 130a-dare coupled to the drivers 40a-band 70a-band have voltage inputs 132 that are isolated from their voltage outputs 134 and thus serve to keep the voltages applied to the inputs 132 from varying when a load is applied to the outputs 134 (i.e., the buffer inputs are high impedance while the outputs are low impedance). The buffers 130 ensure that the proper voltage values are maintained throughout the drive circuit as the display is updated.

[0083] A pair of mode select switches 102a-bare connected to corresponding drivers 40a-bto determine in which mode the corresponding common driver operates, whether in the hold/select/evolve mode or the evolve/non-select mode. All mode select switches 102 are independent of each other and are ultimately controlled by the digital control circuit. When the mode select switch 102ais set to a high input 104a, the select common input waveform is routed to the input 132a, through the buffer 130a, and onto the common driver 40a. In particular, the buffer 130 generates an output 134 that is received by the superinput 78. When the switch 102ais set to the low input 106a, the input non-select DC voltage V_n/sis routed to the input 132a, through the buffer 130a, and onto the common driver 40ain a like manner.

[0084] A common select waveform generator switch 110 creates the select common input waveform that has been previously described. It consists of a high input 112 connected to V_s+, a low input 114 connected to V_s−, and an output 116 connected to the high inputs 104 of the mode select switches 102. It is ultimately controlled by the digital control circuit. Toggling the common select waveform generator switch 110 between the high input 112 and the low input 114 generates the select common input waveform at the output 116 by alternately routing the voltages Vs+ and Vs− to the output 116.

[0085] A prep/write select switch 120 consists of a high input 122 connected to V_h/e−, a low input 124 connected to V_d+, and an output 126 connected to the buffer input 132c. It is ultimately controlled by the digital control circuit. During the preparation phase of an image update the prep/write switch 110 is set to the high input 122 and V_h/e− is routed to the buffer 132 and on to the segment drivers. During the writing phase of an image update the prep/write switch 110 is set to the low input 124 and V_d− is likewise routed to the buffer 132 and on to the segment drivers 70.

[0086] Although the superinputs 88 are used on the segment drivers in the current invention, it is not necessary. All that is necessary is that V₃be less than or equal to V₂. The V₃voltage input is never used with the current waveforms.

[0087] Thus, it can be seen that the objects of the invention have been satisfied by the structure and its method for use presented above. While in accordance with the Patent Statutes, only the best mode and preferred embodiment has been presented and described in detail, it is to be understood that the invention is not limited thereto or thereby. Accordingly, for an appreciation of true scope and breadth of the invention, reference should be made to the following claims.