Method of planarization

[0002] This application claims the priority benefit of Taiwan application Ser. No. 87118921, filed Nov. 16, 1998, the full disclosure of which is incorporated herein by reference.

[0003] 1. Field of Invention

[0004] The present invention relates to a method of planarization. More particularly, the present invention relates to a method including the step of forming a spin-on-glass (SOG) layer over a semiconductor wafer prior to performing a chemical-mechanical polishing process, so that a smooth polished wafer surface is obtained.

[0005] 2. Description of Related Art

[0006] In the fabrication of VLSI or ULSI circuits, all the devices, metallic interconnects or isolating trench structures on a semiconductor wafer must be carefully laid out so that the level of device integration and operating speed are optimized. However, these devices and structures are likely to be distributed non-uniformly above the semiconductor wafer. Consequently, a portion of the wafer surface will be densely packed while some other areas may have very few devices or isolating structures. Furthermore, all these devices and structures have different thicknesses. Hence, the wafer is likely to have a highly undulating cross-sectional profile. To facilitate the next processing process, the semiconductor wafer is usually planarized.

[0007] At present, the most commonly used method of planarizing a semiconductor wafer is the chemical-mechanical polishing (CMP) method. In a CMP process, chemical agents in the form of slurry are delivered to a rotating polishing table with a polishing pad on top. With the back of a wafer grasped by a handle, a global polishing of the wafer is carried out by pressing the front surface against the polishing pad though the handle. Since the polishing pad is made from a soft, flannel-like material, the pad is able to follow the varying contour of the wafer surface.

[0008] Because devices and structures are not evenly distributed on the surface of the semiconductor wafer, some areas are densely packed while other areas are loosely packed. Therefore, when an insulation layer is deposited over the semiconductor wafer, the insulating material will accumulate to a higher level in the densely packed areas than in the loosely packed areas. Subsequently, if a chemical-mechanical polishing process is carried out to planarize the wafer surface, recess cavities can easily form in the loosely packed device areas. Hence, a completely planarized semiconductor wafer surface is difficult to obtain.

[0009] FIGS. 1A through 1C are schematic, cross-sectional views showing the progression of steps according to a conventional method of planarizing an insulation layer above a semiconductor wafer.

[0010] First, as shown in FIG. 1A, a semiconductor wafer 100 having a densely packed device region 108 and a loosely packed device region 110 thereon is provided. Next, an insulation layer 102 is formed over the substrate 100 in both regions 108 and 110. The insulation layer can be formed by performing a chemical vapor deposition (CVD) process. The insulating material of the insulation layer 102 accumulates to a higher level in the densely packed device region 108 than in the loosely packed device region 110. Hence, the upper surface of the insulation layer 102 has a highly undulating profile.

[0011] Next, as shown in FIG. 1B, a chemical-mechanical polishing (CMP) process is carried out to planarize the semiconductor wafer 100. Due to the relative softness of the polishing pad 104, the polishing pad 104 is able to contact the upper surface of the insulation layer 102 in the loosely packed region 110 more closely than the densely packed region 108.

[0012] Thereafter, as shown in FIG. 1C, a recess cavity 106 is formed in the loosely packed device region 110 so that a not-so-planar insulating layer 102 results. Consequently, when material is deposited over the wafer, thickness tends to vary across the surface. Additionally, when the wafer is subsequently etched, depth of etching will tends to vary across the surface, too. Hence, more defects accumulate on the wafer and failure rate of the devices within the wafer is higher.

[0013] In light of the foregoing, there is a need to provide an improve method for planarizing a semiconductor wafer.

[0014] Accordingly, the purpose of the present invention is to provide a method for planarizing a semiconductor wafer by preventing the formation of recess cavities above the loosely packed device areas of an insulation layer after performing a chemical-mechanical polishing process.

[0015] To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for planarizing a semiconductor wafer to prevent the formation of recess cavity in loosely packed device areas above an insulation layer. An insulation layer over a semiconductor wafer having a pre-defined upper profile is formed over a substrate. The upper profile of the semiconductor wafer is formed due to the formation of semiconductor devices, metallic interconnects, and trench structures above the substrate. Furthermore, the profile can be further divided into densely packed and loosely packed device regions. The insulation layer accumulates to a higher level in the densely packed region than in the loosely packed region. A spin-on-glass (SOG) layer is spin-coated over the insulation layer. A baking process is carried out to remove volatile organic solvent inside the SOG layer. A chemical-mechanical polishing process is conducted to planarize the wafer. The entire SOG layer is removed, retaining only an insulation layer polished to the expected thickness.

[0016] One major aspect of this invention is the coating of a spin-on-glass layer over the insulation layer prior to the carrying out of a planarization process. Spin-on-glass is highly flowable, and hence is able to form a very smooth planar surface. After the spin-on-glass material is baked, the spin-on-glass layer is planarized by performing a chemical-mechanical polishing process. The problem of having too many recess cavities in the loosely packed device region above the insulation layer is avoided.

[0017] Another aspect of this invention is that the curing process for solidifying the spin-on-glass layer is omitted. In other words, only the spin-coating process for forming a spin-on-glass layer over the insulation layer and its subsequent baking process are performed.

[0018] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

[0019] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,

[0020] FIGS. 1A through 1C are schematic, cross-sectional views showing the progression of steps according to a conventional method of planarizing an insulation layer above a semiconductor wafer; and

[0021] FIGS. 2A through 2D are schematic, cross-sectional views showing the progression of steps for planarizing the upper surface of an insulating layer without forming recess cavities in the loosely packed region according to one preferred embodiment of this invention.

[0022] Reference will now be made in detail to the present preferred embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and the description to refer to the same or like parts.

[0023] FIGS. 2A through 2D are schematic, cross-sectional views showing the progression of steps for planarizing the upper surface of an insulating layer without forming recess cavities in the loosely packed region according to one preferred embodiment of this invention.

[0024] As shown in FIG. 2A, a semiconductor wafer 200 having a pre-defined surface profile is provided. The pre-defined surface profile arises from substrate, semiconductor devices, metallic interconnects and the trench structures of isolating devices formed above the wafer. Furthermore, the pre-defined surface profile can be divided into densely packed device regions 206 and loosely packed device regions 208. An insulation layer 202 is formed over the semiconductor wafer 200 using, for example, a chemical vapor deposition (CVD) method. The upper surface of the insulation layer 202 has a profile similar to the semiconductor wafer 200. In other words, the insulation layer 202 rises to a higher level in the densely packed regions 206 than in the loosely packed regions 208.

[0025] As shown in FIG. 2B, a spin-on-glass (SOG) layer 204 is spin-coated over the insulation layer 202. Due to the flowability of the SOG material, a very flat upper surface will be obtained.

[0026] As shown in FIG. 2C, a baking process is carried out at a temperature of between 100° C. and 170° C. so that volatile organic solvent inside the SOG layer 204 can be evaporated away. The SOG layer 204 is hardened. At the same time, the SOG layer 204 contracts a little along the upper surface of the insulation layer 202. However, the degree of contraction is not much so that surface profile of the insulation layer 202 does not emerge again at the top of the SOG layer 204. Consequently, the baked SOG layer 204 can still maintain a high degree of planarity at its upper surface. Nevertheless, baking of the SOG layer 204 must not be carried out for too long, otherwise the SOG material will be transformed into an oxide layer, which is ineffective for forming a planar surface.

[0027] In a conventional SOG planarization process, the SOG layer is cured after the baking process. Curing is a process of solidifying the SOG material into silicon dioxide (SiO₂) so that the SOG layer is hardened. However, in this invention, curing is not carried out. Curing results in a rather large contraction of the SOG layer 204, and hence the upper surface profile of the insulation layer 202 would ultimately emerge on the upper surface of the SOG layer 204. If a chemical-mechanical polishing process were carried out, the polishing pad 204 within the loosely packed region 208 would follow the upper profile of the SOG layer 204. Hence, recess cavities would likely form in the upper surface of the insulation layer 202 in the loosely packed region 208.

[0028] As shown in FIG. 2D, a chemical-mechanical polishing (CMP) method is used to remove the SOG layer 204 and planarize the insulation layer 202. Hence, an insulation layer having a thickness as specifically required and a planar upper surface is obtained. Since the SOG layer 204 with which the polishing pad 210 makes contact during the CMP process is flat, recess cavities do not form on the insulation layer 202 in the loosely packed region 208.

[0029] In summary, this invention includes coating a spin-on-glass layer 204 over the insulation layer 202. The SOG layer 204 is only baked to transform the highly undulating surface profile of the insulation layer 202 into a much smoother surface. Although the insulation layer 202 is higher in the densely packed regions 206 than in the loosely packed regions 208, the flowable property of the SOG material permits an equalization of the height difference between the two regions. Hence, when a chemical-mechanical polishing process is later carried out, the polishing pad 210 will be in contact with a flat surface. Consequently, unlike in a conventional method, no recess cavity such as 106 is formed on the insulation layer 102 in the loosely packed region 110. The central idea behind this invention is to provide a planar surface above the insulation layer 202 of a semiconductor wafer 200 so that subsequent processing processs above the insulation layer 202 can have better effects. In other words, the invention is able to prevent the generation of undesirable defects resulting from a non-planar surface, thereby increasing the product yield and lowering wafer production cost.

[0030] Furthermore, this invention includes another advantage that a curing step of the SOG layer 204 above the insulation layer 202 is not conducted after the baking process. This is because curing makes the SOG layer 204 contract. Contraction of the SOG layer 204 eliminates the positive effect of leveling the height difference between the insulation layer 202 in the densely packed region 206 and the loosely packed region 208. Hence, when a chemical-mechanical polishing process is later carried out, height difference between the densely packed region 206 and the loosely packed region 208 again produces recess cavities on the insulation layer 202.

[0031] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.