Method for decreasing contact resistance of an electrode positioned inside a misaligned via for multilevel interconnects

[0002] 1. Field of the Invention

[0003] This invention relates to a method of fabricating an integrated circuit and more specifically to a method for reducing the resistance of electrical coupling between conductive layers in vias or contact holes.

[0004] 2. Background of the Invention

[0005] Several factors adversely impact the effectiveness of multilevel interconnects. Among them include, but are not limited to, misalignment of vias or contact holes caused by the via patterning process and the failure to remove resistive compounds formed on electrodes positioned in the misaligned contact holes. These two factors cause an increase in resistance of the contact holes, resulting in poor conduction between the levels of the interconnect. Consequently, the reliability of the produced device is diminished. As VLSI feature sizes continues to shrink, for example to sub 0.25 μm region, the problem of misaligned or “unlanded” vias seem unavoidable. Thus, to improve device performance and reliability, as related to conduction between conductive layers, it would be desirable to reduce or eliminate the presence of the aforementioned resistive compounds.

[0006] To pose the problem more concretely by way of example, aluminum (Al) is a preferred material for electrodes because it is lightweight, corrosion resistant, and inexpensive. However, aluminum is porous and has a high effective surface area capable of easily adsorbing oxygen and water vapor. As a result, during the processing of multilevel interconnects, a native oxide layer is formed on the aluminum. The oxidized aluminum acts as a resistive film.

[0007] As discussed above, the problem of conductivity is also heightened due to the misalignment of vias or contact holes. Ideally, as illustrated in FIG. 1, the vias 2 should be positioned directly above the aluminum electrodes 4, as depicted by area X. Referring to FIG. 1, there is illustrated a substrate 6 supporting the electrodes 4. An intermediate dielectric layer 8 separates the electrodes 4 from a second level of interconnect 10. The direct alignment of tungsten (W) filled vias 2 on the aluminum electrodes 4 can provide a resistance of about 1 Ω to about 2 Ω for the contact holes 2. When the tungsten filled vias 2 are misaligned or “unlanded,” generally illustrated by area Y in FIG. 2, the resistance of the contact holes can increase, causing the reliability of the device to suffer.

[0008] The combination of having an oxidized aluminum electrodes 4 and misaligned tungsten filled vias 2, therefore, can produce a resistance about 8-10 Ω, for the contact holes 2. This combination is illustrated in FIG. 2. In order to compensate for the increase in resistivity caused by the misalignment of the contact holes 2, the resistance of the aluminum electrode 4 has to be decreased. Therefore, the active conductive contact area (i.e., the area not covered by native oxide) of the aluminum electrode 4 must be enlarged. The only active contact area of aluminum electrode 4 is area D, an area which is typically covered by titanium nitride 5. It is desirable to remove the oxidized aluminum film, as illustrated by shaded area 7, from the aluminum electrode 4, and in effect, to make contact area C active. The activation of contact area C produces a resistivity of about 2 Ω to about 3 Ω for the “unlanded” tungsten filled contact holes 2, a decline of about 5 Ω to about 8 Ω.

[0009] The present invention accomplishes its desired objects by broadly providing a method for decreasing contact resistance of an electrode, comprising:

[0010] a) providing an electrode having a resistive film formed thereon;

[0011] b) removing the resistive film from the electrode; and

[0012] c) forming a protective layer on the electrode.

[0013] The electrode can comprise an aluminum layer supported by a titanium nitride layer or a titanium/titanium nitride bi-layer. The resistive film may comprise native oxide, formed on the electrode during etching or processing of the electrode. The removing step (b) comprises employing a plasma of an etchant gas to etch and remove the resistive film from the electrode. The etchant gas includes about 100% by volume argon.

[0014] After the resistive film has been removed from the electrode, a protective layer is formed on the electrode. Preferably, the protective layer comprises titanium nitride. Alternatively, the protective layer may comprise a titanium/titanium nitride stack.

[0015] The present invention also accomplishes its desired objects by broadly providing a method for manufacturing a multilevel interconnect, comprising:

[0016] a) providing a first electrode layer on a substrate;

[0017] b) removing a portion of the first electrode layer from the substrate to produce metal lines, the metal lines having a resistive film formed thereon during processing of the metal lines;

[0018] c) etching the metal lines of step (b) including employing a plasma of an etchant gas to remove the resistive film;

[0019] d) forming a protective layer on the substrate and the metal lines, the protective layer having intermediate portions;

[0020] e) etching the intermediate portions of the protective layer to break through and remove the intermediate portion from the substrate;

[0021] f) forming a dielectric layer on the substrate and the metal lines;

[0022] g) etching vias in the dielectric layer to expose a portion of the metal lines;

[0023] h) filling the vias with plugs; and

[0024] i) forming a second electrode layer on the dielectric layer and the plugs to produce a multilevel interconnect.

[0025] The first electrode layer, as discussed above, comprises a titanium nitride layer supporting an aluminum layer. The first electrode layer may additionally comprise a titanium layer disposed under the titanium nitride layer. The first electrode layer may additionally comprise a second titanium nitride layer disposed on the aluminum layer. Selected portions of the first electrode layer is etched or removed from the substrate to form metal lines. During the processing of the metal lines, a resistive film, such as native oxide, is formed on the metal lines. In other words, a portion of the aluminum is oxidized. As stated previously, the resistive film is etched from the metal lines by employing a plasma of an etchant gas comprising about 100% by volume argon.

[0026] As discussed previously, after the resistive film has been removed from the metal lines, a protective layer is formed on the metal lines, including the substrate. The protective layer that is formed on an intermediate portion, i.e., the space between the metal lines, is etched and removed from the substrate. The protective layer that is formed on top of the metal lines is also removed. In the alternative embodiment, the protective layer that is formed on the second titanium nitride layer on top of the metal lines is removed.

[0027] A first level of the multilevel interconnect is now in condition for the addition of the next level. A dielectric layer is formed on the substrate and the metal lines. The dielectric layer may, for example, comprise silicon or a fluorine based compound having a low dielectric constant. Contact holes or vias are patterned in the dielectric layer to expose a portion of the metal lines. A film comprising, for example, titanium/titanium nitride, is formed on the dielectric layer. Additionally, the film is formed on inside surfaces of the contact holes. The contact holes are filled with plugs, such as tungsten. A second electrode layer may be disposed on the dielectric layer and the plugs, thus creating a multilevel interconnect.

[0028] These advantages, together with the various ancillary features which will become apparent to those skilled in the art as the following description proceeds, are attained by these novel methods, a preferred embodiment thereof shown with reference to the accompanying drawings, by way of example only, wherein:

[0029] FIG. 1 is a cross sectional view of a multilevel interconnect having contact holes or vias connecting the two levels of interconnect through a dielectric layer, the contact holes or vias are directly aligned with respect to electrodes;

[0030] FIG. 2 is a cross sectional view of a multilevel interconnect wherein a resistive film, represented by the shaded area, has reduced the active conductive contact area of electrodes positioned in misaligned or “unlanded” contact holes;

[0031] FIG. 3A is a cross sectional view of a semiconductor wafer having a substrate, a first barrier bi-layer disposed on the substrate, an electrode layer disposed on the first barrier bi-layer, and resists disposed on the electrode layer;

[0032] FIG. 3B is a cross sectional view of the semiconductor wafer of FIG. 3A additionally including a second barrier layer disposed on the electrode layer;

[0033] FIG. 4A is a cross sectional view of the semiconductor wafer of FIG. 3A after etching and removing a portion of the electrode layer and the first barrier bi-layer from the surface of the substrate;

[0034] FIG. 4B is a cross sectional view of the semiconductor wafer of FIG. 3B after etching and removing a portion of the second barrier layer, the electrode layer, and the first barrier bi-layer from the surface of the substrate;

[0035] FIG. 5A is a cross sectional view of the semiconductor wafer of FIG. 4A, after the resists have been removed and stripped-off the electrodes to produce metal lines, the metal lines having a resistive film, represented by the shaded area, formed thereon during processing of the metal lines;

[0036] FIG. 5B is a cross sectional view of the semiconductor wafer of FIG. 4B, after the resists have been removed and stripped-off the second barrier layer to produce metal lines, the metal lines having a resistive film, represented by the shaded area, formed thereon during processing of the metal lines;

[0037] FIG. 6A is a cross sectional view of the semiconductor wafer of FIG. 5A, wherein the metal lines are being bombarded by ion particles to etch and remove the resistive film;

[0038] FIG. 6B is a cross sectional view of the semiconductor wafer of FIG. 5B, wherein the metal lines are being bombarded by ion particles to etch and remove the resistive film;

[0039] FIG. 7A is a cross sectional view of the semiconductor wafer of FIG. 6A wherein the resistive film has been removed and a protective layer has been formed on the metal lines and the substrate;

[0040] FIG. 7B is a cross sectional view of the semiconductor wafer of FIG. 6B wherein the resistive film has been removed and a protective layer has been formed on the metal lines and the substrate;

[0041] FIG. 8A is a cross sectional view of the semiconductor wafer of FIG. 7A wherein the protective layer between and on top of the metal lines has been etched and removed from the substrate;

[0042] FIG. 8B is a cross sectional view of the semiconductor wafer of FIG. 7B wherein the protective layer between the metal lines and on top of the second barrier layer has been etched and removed from the substrate;

[0043] FIG. 9 is a cross sectional view of the semiconductor wafer having the substrate supporting the metal lines, the protective layer formed on the side of the metal lines, and a dielectric layer disposed on the substrate including the metal lines;

[0044] FIG. 10 is a cross sectional view of the semiconductor wafer of FIG. 9 having resists selectively disposed on the dielectric layer for etching contact holes or vias in the dielectric layer, as represented by dashed lines;

[0045] FIG. 11 is a cross sectional view of the semiconductor wafer of FIG. 10 after etching the contact holes or vias in the dielectric layer to expose a portion of the metal lines, the contact holes or vias being misaligned or “unlanded” with respect to the metal lines;

[0046] FIG. 12 is a cross sectional view of the semiconductor wafer of FIG. 11 after a film is formed on the dielectric layer including the inside surfaces of the contact holes or vias;

[0047] FIG. 13 is a cross sectional view of the semiconductor wafer of FIG. 12 after plugs are formed in the contact holes or vias, the plugs being represented by diagonal lines; and

[0048] FIG. 14 is a cross sectional view of the semiconductor wafer of FIG. 13 having a second electrode layer disposed on the dielectric layer and the plugs, producing a multilevel interconnect.

[0049] Embodiments of the present invention will be described with reference to is the aforementioned figures. These figures have been simplified for ease of understanding and describing the embodiments of the present invention. Referring in detail now to the drawings wherein similar parts of the present invention are identified by like reference numerals, there is seen in FIG. 3A a semiconductor substrate, e.g., silicon substrate, generally illustrated as 12. A first barrier bi-layer is disposed on the substrate 12 and an electrode layer 16 is disposed on the first barrier bi-layer 14. Resists 20 are selectively positioned, i.e., spun, exposed and developed, on the electrode layer 16. In another preferred embodiment of the invention, as shown in FIG. 3B, a second barrier layer 18 is disposed on the electrode layer 16. The first barrier bi-layer 14, the second barrier layer 18 (only in reference to the FIG. 3B embodiment), and the electrode layer 16 can collectively be referred to as a multilayer electrode 22.

[0050] The electrode layer 16 may be made of any conductive material and may be of any suitable thickness. Preferably, electrode layer 16 comprises aluminum (Al). The thickness of the Al electrode layer 16 depends on its end use. Typically, the thickness of the Al electrode layer 16 ranges from about 3000 Angstroms to about 8000 and more preferably from about 4500 Angstroms to about 6500 Angstroms. The Al electrode layer 16 may be disposed on the substrate layer 12 by evaporation, dc magnetron sputtering, physical vapor deposition (PVD), or chemical vapor deposition (CVD).

[0051] The first barrier bi-layer 14 may be any suitable barrier layer which is capable of functioning as both an adhesive and a diffusion barrier to the Al electrode layer 16. The first barrier bi-layer 14 may be of any suitable thickness. Preferably, the first barrier bi-layer 14 comprises a titanium (Ti) layer 13 and a titanium nitride (TiN) layer 15 disposed on the Ti layer 13. Ti promotes good adhesion as it forms TiSi₂by reacting with the Si of the silicon substrate 12. The use of TiN as a buffer layer between Al—Ti creates excellent thermal stability and contact resistivity (10⁻⁶Ω-cm²). The TiN layer 15 may possess, for example, a thickness ranging from about 100 Angstroms to about 300 Angstroms, more preferably from about 200 Angstroms to about 250 Angstroms, and most preferably about 200 Angstroms. The Ti layer 13 may possess a thickness ranging from about 100 Angstroms to about 300 Angstroms, more preferably from about 100 Angstroms to about 150 Angstroms, and most preferably about 100 Angstroms. The Ti layer 13 is preferably disposed on the silicon substrate 12 by physical vapor deposition (PVD). The TiN layer 15 may be disposed on the Ti layer 13 by evaporating the Ti in a N₂ambient, by reactively sputtering the Ti in an Ar+N₂mixture, by sputtering from a TiN target in an inert Ar ambient, by sputter deposing Ti in an Ar ambient and changing it to TiN in a separate plasma nitration step, or by CVD.

[0052] The second barrier layer 18 may be any suitable barrier layer which is capable of functioning as an anti-reflective coating and for aluminum hillock suppression upon the aluminum's exposure to high process temperatures. Preferably, second barrier layer 18 comprises TiN and possesses a thickness ranging from about 200 Angstroms to about 1000 Angstroms, more preferably from about 200 Angstroms to about 500 Angstroms, and most preferably about 250 Angstroms. The second barrier layer 18 is formed, for example, by PVD.

[0053] The resists 20 (i.e., the photoresist 20) are a light-sensitive organic polymer film which are spun on the multilayer electrode 22, exposed, and developed as is well understood to those skilled in the art. The resists 20 protect the underlying substances from attack during the etching process of the present invention.

[0054] The structure of FIG. 3A or FIG. 3B is initially placed in a plasma processing apparatus to break through and remove or etch away from the surface of the substrate 12 the multilayer electrode 22, except the multilayer electrode that is below the resists 20, as depicted by dashed lines 22ain FIGS. 3A and 3B. In other words all portions of the Al electrode layer 16, the Ti layer 13, the TiN layer 15, and the TiN layer 18 are removed except for portions 16a,13a,15a,and 18a. The result of the etching is illustrated in FIGS. 4A and 4B, respectively. Thereafter, the resists 20 are removed or stripped-off from the surface of the aluminum electrode 16ain FIG. 4A or the TiN layer 18ain FIG. 4B. The result of the resist strip is illustrated in FIGS. 5A and 5B. The plasma processing apparatus may employ any suitable etchant gas to break through (i.e., to clean and etch away) the electrode layer 16, first barrier bi-layer 14, and the second barrier layer 18, except the multilayer electrodes 22a(i.e., metal lines 24) below the resists 20. Such procedure is well known to those skilled in the art.

[0055] After the resists 20 have been removed or stripped-off, the metal line 24 profiles are developed, as illustrated in FIGS. 5A and 5B. In processing the metal lines 24, a resistive film such as native oxide, generally illustrated by shaded area 26, is formed on the Al electrode 16a.Native oxide 26 is typically formed when the Al electrode 16ais exposed to either air or oxygen and water desorbed during the etching process. The native oxide 26 impedes the conductivity of the aluminum electrode 16aas it forms an resistive barrier or film.

[0056] The resistive film 26, e.g., native oxide, is removed from the electrode 16a, e.g., aluminum electrode, by etching the electrode 16a.By preference, the resistive film 26 is sputter etched in a plasma chamber containing a plasma of an etchant gas. The etchant gas is preferably 100% (i.e., greater than about 99.9%) by volume argon. Argon plasma are known to have a high energetic ion concentration and are often used for physical sputtering. The sputtering effect due to the ions is a function of an acceleration potential which exists between the plasma and the sample. In other words, the physical ejection of material occurs when positive ions are propelled into the sample by the negative potentials at the edge of the plasma. As illustrated in FIGS. 6A and 6B, positive ions 30 are accelerated across the sheath and strike the metal lines 24 with high kinetic energy. A portion of this kinetic energy is transferred to surface atoms which are then ejected, causing the physical removal of the resistive film 26, i.e., the native oxide. A low pressure and a long mean-free path are required in the reactor for the material to leave the vicinity of the sample without being back-scattered and redeposited. The substrate 12 is disposed in any one the well known plasma chambers having an inductor and a wafer pedestal and the etching and removing step is performed under the conditions listed in Table I below:

[0057] After the removal of the resistive film 26, the substrate 12 is transferred under a vacuumed condition to a deposition station within a deposition chamber where a protective layer 32 is formed on the substrate 12 and the metal lines 24, as illustrated by FIG. 7. The protective layer 32 protects the metal lines 24 from a further developing a resistive film. The protective layer 32 may be of any suitable thickness. Protective layer 32 may possess a thickness ranging from about 50 Angstroms to about 200 Angstroms, more preferably from about 50 Angstroms to about 100 Angstroms, and most preferably about 50 Angstroms. Preferably, the protective layer 32 comprises TiN. Alternatively, the protective layer 32 may comprise a Ti/TiN stack. The Ti of the protective layer 32 may be formed by any of the well known PVD methods. The metal lines 24 are heated to a temperature of about 100° C. to about 300° C., preferably about 100. The deposition chamber is pressurized from about 3 mTorr to about 10 mTorr, preferably about 5 mTorr. Argon gases are used in the chamber for physical vapor deposition of a Ti layer on the metal lines 24. Preferably, the TiN of the protective layer 32 may be formed by CVD. The metal lines 24 are heated to a temperature of about 370° C. to about 450° C., preferably 375° C. The deposition chamber is pressurized from about 500 mTorr to about 1000 mTorr, preferably 700 mTorr. Tetrakis (dimethylamido) titanium (TDMAT) or tetrakis (diethylamido) titanium (TDEAT) is provided at a flow rate of about 200 sccm.

[0058] Next, a portion of the protective layer 32 which is formed between the metal lines 24, generally referred as intermediate portion 34, is removed or etched from the substrate 12, the result of which is illustrated in FIGS. 8A and 8B. Moreover, a portion of the protective layer 32 which is formed on top of the electrode 16a(FIG. 7A) or on top of the second barrier layer 18a(FIG. 7B), generally illustrated as top portion 33, is also removed, as shown in FIG. 8A and 8B. The intermediate portion 34 and the top portion 33 of the protective layer 32 are removed in any one of the well known plasma chambers having an inductor and a wafer pedestal and the etching and removing step is performed under the conditions listed in Table II below:

[0059] Referring to FIG. 9, in order to create a multilevel interconnect, a dielectric layer 36 is formed on the above described substrate layer 12 and metal lines 24. Dielectric layers are used to electrically isolate adjacent levels of conductors. Preferably, the dielectric layer 36 comprises silicon or a fluorine base compound having a low dielectric constant. The dielectric 36 layer possesses a thickness ranging from about 5000 Angstroms to about 10,000 Angstroms, more preferably from about 5000 Angstroms to about 8000 Angstroms, and most preferably about 6500 Angstroms. After the dielectric layer 36 is formed, chemical-mechanical polishing is employed to planarize the dielectric layer 36. Silicon dielectric layers can be deposited by means of a number of CVD processes, including atmospheric CVD or plasma-enhanced CVD, which are well known in the art.

[0060] Referring to FIG. 10, resists 20 are selectively placed, i.e., spun, exposed, and developed, on the dielectric layer 36. The portion of the dielectric layer 36 that is not protected by the resists 20 is etched to pattern contact holes or vias 38 in the dielectric layer 36 to expose a portion of the metal lines 24. Resists 20 are placed a distance of B apart from one another. Distance B is equal to width A of the metal lines 24. As a result, the vias 38 will have diameter equal to A or B. As previously discussed in the Background of the Invention section of the application, one of the factors that adversely impacts multilevel interconnects is the misalignment of vias during the via patterning process. In other word the vias 38 do not “land” directly on the metal lines 24, as illustrated in FIG. 11. The vias 38 are commonly shifted and misaligned with respect to the metal lines 24. Resists 20 can be removed during or after the patterning process of the vias 38. Proceeding the removal of the resists 20, as illustrated by FIG. 12, a film 40 is formed on the dielectric layer 36, including inside surfaces 39 of the vias 38. The film 40 also forms over the metal lines 24. The film 40 may comprise any suitable material functioning as an adhesive and a diffusion barrier. Preferably, the film 40 comprises Ti/TiN stack, as this stack promotes adequate adhesion not only for a second electrode layer 44 but also for plugs 42 which are formed in the vias 38 (see FIGS. 13 and 14). The film 40 may be of any suitable thickness. The film 40 can possess a thickness ranging from about 200 Angstroms to about 1000 Angstroms, more preferably from about 200 Angstroms to about 300 Angstroms, and most preferably about 200 Angstroms. The Ti/TiN film 40, may be formed using CVD, PVD, or a combination of both.

[0061] After the deposition of the film 40, the vias 39 are filled, through the deposition of metal, to form plugs 42. Preferably, tungsten (W) is used as the plugs 42. CVD techniques have been used to fill the vias 38 with tungsten. Finally, chemical-mechanical polishing or tungsten etch back is used to planarize the dielectric layer 36 and to form the plugs 42. A second electrode layer 44, as illustrated in FIG. 14, can now be disposed, creating a multilevel interconnect.

[0062] Thus, while the present invention has been described herein with reference to particular embodiments thereof, a latitude of modifications, various changes and substitutions are intended in the foregoing disclosure, and it will be appreciated that in some instances some features of the invention will be employed without a corresponding use of other features without departing from the scope of the invention as set forth.