Method of forming a sidewall spacer and a salicide blocking shape, using only one silicon nitride layer

[0002] (1) Field of the Invention

[0003] The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a process sequence used to form sidewall spacers, and salicide blocking shapes, using silicon nitride.

[0004] (2) Description of Prior Art

[0005] The use of complimentary metal oxide semiconductor, (CMOS), devices, for both logic, as well as memory applications, fabricated on the same semiconductor chip, have resulted in increased process complexity, as well as increased cost, for the integrated CMOS devices. The ability to share specific process steps, or sequences, used for each type, logic and memory, can significantly reduce process complexity and cost. For example a Self-ALigned metal silICIDE, (salicide), layer, is used with the high performance, CMOS logic devices, while the salicide layer is not desired for CMOS memory applications. A silicon nitride shape is sometimes used to block salicde formation in the CMOS memory region, while being introduced in the CMOS logic area. The silicon nitride layer used for the salicide blocking shape, can however be the second silicon nitride used in the integration of CMOS logic and memory devices. Prior to formation of heavily doped source/drain regions, for both type devices, sidewall spacers, formed from a first silicon nitride layer, are formed on the sides of gate structures, to prevent gate to substrate leakage or shorts. Since the integrity of the sidewall spacer, as well as the quality of the silicide blocking shape, are paramount, high quality silicon nitride layers, in terms of diffusion barrier, are needed for these functions. Therefore these silicon nitride layers are obtained via a low pressure chemical vapor deposition, (LPCVD), procedure, usually performed at a temperature between about 800 to 900° C., instead of the use of plasma enhanced vapor deposition, (PECVD), silicon nitride layers, obtained at temperatures lower than 800° C.

[0006] The use of two, high temperature deposited silicon nitride layers, however can exhaust the thermal budget allotted for the fabrication of the integrated CMOS chip,. in terms of unwanted movement of doping profiles. Therefore a novel process sequence, utilizing only a single silicon nitride layer, for both sidewall spacer, and salicide blocking shape, will be presented, removing one high temperature process, thus preserving the thermal budget. The novel process sequence detailed in this present invention, features definition of a silicon nitride blocking shape, in the CMOS memory region, and the formation of a L shaped, silicon nitride spacer, on the sides of CMOS logic gate structures, with both silicon nitride shapes defined from the same LPCVD silicon nitride layer. Salicide formation is then initiated in the CMOS logic region, while the silicon nitride blocking shape protects all CMOS memory regions, during the salicide procedure. Prior art, such as Cote et al, in U.S. Pat. No. 4,838,991, as well as Chor et al, in U.S. Pat. No. 5,801,077, describe the use of organic spacers, on the sides of gate structures, however these prior arts do not describe the process sequence for forming silicon nitride, sidewall spacers, for both memory and logic devices, and a salicide blocking shape, for memory devices, from a single deposition of an LPCVD silicon nitride layer.

[0007] It is an object of this invention to integrate the fabrication of CMOS logic devices, featuring salicide layers, with CMOS memory devices, formed without salicide layers.

[0008] It is another object of this invention to use only one silicon nitride layer for the formation of silicon nitride spacers, on the sides of the CMOS logic gate structures, and for the formation of a silicon nitride blocking shape, used to prevent salicide formation in the CMOS memory region.

[0009] It is still another object of this invention to use an organic spacer, on the sides of all gate structures, as a mask for definition of heavily doped, source/drain regions.

[0010] In accordance with the present invention a method of using one silicon nitride for the formation of silicon nitride spacers, on the sides of CMOS logic gate structures, and for the formation of a silicon nitride shape, located in the CMOS memory region, used to prevent salicide formation in the CMOS memory region, is described. After the formation of gate structures, on an underlying gate insulator layer, lightly doped source/drain,(LDD), regions are formed in an area of the semiconductor substrate not covered by the gate structures. After growing a thin silicon oxide layer, on the gate structures, and on the top surfaces of the LDD regions, a first organic layer is deposited, then subjected to an anisotropic reactive ion etch, (RIE), procedure, to create organic spacers, on the sides of the thin silicon oxide coated, gate structures. After creation of heavily doped source/drain regions, in all regions of the semiconductor substrate, not covered by the gate structures, or by the organic spacers, the organic spacer is selectively removed, followed by the deposition of a silicon nitride layer, and of a second organic layer. A photoresist shape is then used to protect the CMOS memory region from another anisotropic RIE procedure, creating a composite spacer, on the sides of the gate structures in the CMOS logic region, with the composite spacer comprised of the overlying, organic shape, and an L shaped, silicon nitride feature. The blanket, anisotropic RIE procedure removes the exposed portions of the silicon nitride layer, in the CMOS logic region, resulting in exposure of the top surface of the gate structure, and the top surface of the heavily doped source/drain region, while all regions of CMOS memory region remain covered by silicon nitride Removal of the photoresist shape, and of all portions of the second organic layer, followed by a hydrofluoric acid procedure, results in a CMOS memory region, still covered with silicon nitride, and a CMOS logic region, still with the silicon nitride component, of the composite spacer, remaining on the sides of the gate structure, however with the top surface of the gate structures, as well as the top surface of the heavily doped source/drain region exposed. Deposition of a metal layer, followed by an anneal procedure, used to form metal silicide on regions in which the metal layer resided on exposed silicon surfaces, followed by removal of unreacted metal, from the surface of the silicon nitride layer, results in the desired salicide formation, in the CMOS logic region only, with silicon nitride spacers on the sides of the CMOS logic gate structures, and the silicon nitride shape, overlying the CMOS memory devices, all accomplished using only one silicon nitride deposition procedure, protecting these regions from salicide formation.

[0011] The object and other advantages of this invention are best described in the preferred embodiments with reference to the attached drawings that include:

[0012] FIGS. 1-7, which schematically, in cross-sectional style, show key stages of fabrication used to form CMOS devices, using one silicon nitride layer to form silicon nitride spacers on the sides of the salicided CMOS logic gate structures, and to form a silicon nitride blocking shape, for non-salicicde CMOS memory devices.

[0013] The method of fabricating CMOS devices using one layer of silicon nitride for formation of silicon nitride spacers, on the sides of CMOS logic gate structures, and using the same silicon nitride layer for formation of a silicon nitride blocking shape, used to prevent salicide formation for CMOS memory devices, will now be described in detail. Region 50, shown schematically in FIG. 1, will be used for fabrication of high performance, CMOS logic devices, incorporating metal silicide layers, while region 60, will be used for high density, CMOS memory devices, fabricated without metal silicide layers, or without being subjected to a salicide procedure. This invention will be described for N channel, or NMOS devices, however if desired this invention can be applied to P channel, or PMOS devices. A P type, semiconductor substrate 1, comprised of single crystalline silicon, with a <100> crystallographic orientation, is used, and shown schematically in FIG. 1. A gate insulator layer 2, comprised of silicon dioxide, is obtained via thermal oxidation procedures, at a thickness between about 10 to 100 Angstroms. A polysilicon layer is next deposited via LPCVD procedures, to a thickness between about 1000 to 3000 Angstroms, and either doped during deposition, via the addition of arsine, or phosphine, to a silane ambient, or deposited intrinsically, then doped via implantation of arsenic, or phosphorous ions. Conventional photolithographic and anisotropic RIE procedures, using Cl₂or SF₆as an etchant, are used to form polysilicon gate structure 3, overlying gate insulator 2, in both CMOS logic region 50, and CMOS memory region 60. The selective RIE procedure, using selective etchants, terminates at the appearance of gate insulator layer 2. The photoresist shape, used to define polysilicon gate structures 3, is then removed via plasma oxygen ashing, and careful wet cleans, via use of a buffered hydrofluoric acid procedure, used as part of the wet clean procedure, resulting in the removal of the portions of gate insulator layer, not covered by polysilicon gate structures 3. Lightly doped source/drain regions 4, shown schematically in FIG. 1, are next formed in regions of semiconductor substrate 1, not covered by polysilicon gate structures 3, via implantation of arsenic, or phosphorous ions, at an energy between about 3 to 40 KeV, at a dose between about 1E13 to 1E15 atoms/cm³.

[0014] The formation of heavily doped source/drain regions, formed using a disposable organic spacer, will next be addressed and schematically shown in FIGS. 2-3. A thin silicon oxide layer 5, is deposited via LPCVD or PECVD procedures, at a thickness between about 100 to 250 Angstroms, followed by the application of a first organic layer 6, comprised of a material such as propylene glycol monomethyl ether, sometimes used as a bottom anti-reflective coating, (BARC), layer. First organic layer 6, is applied at a thickness between about 600 to 1000 Angstroms. An anisotropic RIE procedure, using CF₄/HBr/O₂or Cl₂/O₂as an etchant, is used to etch first organic layer 6, selectively stopping at the appearance of underlying, thin silicon oxide layer 5, and creating organic spacers on the sides of all gate structures. This is schematically shown in FIG. 2. Implantation of arsenic, or phosphorous ions, is next performed, at an energy between about 30 to 100 KeV, at a dose between about 1E15 to 1E16 atoms/cm², creating heavily doped source/drain regions 7, in areas of semiconductor substrate 1, not covered by gate structures 3, or by the organic spacers formed from first organic layer 6. The organic spacers are then removed via plasma oxygen ashing, or via wet procedures. The result of these procedures is schematically shown in FIG. 3.

[0015] A critical, silicon nitride layer 8a, is next deposited via LPCVD procedures, to a thickness between about 150 to 300 Angstroms, using a deposition temperature between about 800 to 900° C. The use of LPCVD procedures, results in an enhanced barrier layer, when compared to counterpart silicon nitride layers, deposited at lower temperatures, via PECVD procedures. The LPCVD silicon nitride layer, at a thickness of only between about 150 to 300 Angstroms, will still be impermeable to subsequent salicide formation processes, where a less dense, PECVD silicon nitride layer, deposited at lower temperatures, may not survive the same salicide procedure. A second organic layer 9a, is next applied, at a thickness between about 400 to 800 Angstroms, with second organic layer 9a, again being comprised of propylene glycol monomethyl ether, which is sometimes used as a BARC layer. This is schematically shown in FIG. 4.

[0016] A photoresist shape 20, is used to protect CMOS memory region 60, from an anisotropic RIE procedure, used to create a composite spacer, on the sides of the polysilicon gate structures 3, in CMOS logic region 50. The anisotropic RIE procedure is performed using CF₄/HBr/O₂or Cl₂/O₂as an etchant for second organic layer 9a, while using SF₆/HBr or CF₄/HBr as an etchant for silicon nitride layer 8a, resulting in the formation of the composite spacer, comprised of second organic shape 9b, and L shaped, silicon nitride 8b. This is shown schematically in FIG. 5. A plasma oxygen ashing, or an organic wet strip, is then used to remove photoresist shape 20, and second organic layer 9a, in CMOS memory region 60, resulting in polysilicon gate structures 3, as well as heavily doped source/drain regions 7, in CMOS memory region 60, still covered by silicon nitride layer 8a. The same stripping procedures remove second organic shape 9b, from the composite spacer, in CMOS logic region 50, resulting in L shaped silicon nitride spacers 8b, on the sides of polysilicon gate structures, as well as exposing the top surface of heavily doped source/drain regions 7, in CMOS logic region 50. A wet etch clean procedure, performed after the plasma, or wet strip of photoresist shape 20, includes a buffered hydrofluoric acid cycle, resulting in the removal of regions of thin silicon oxide layer 5. The result of these procedures is schematically shown in FIG. 6.

[0017] Selective formation of metal silicide, or salicide formation, on exposed silicon or polysilicon surfaces, in CMOS logic region 50, is next performed. A metal layer, such as titanium, is deposited via plasma vapor deposition procedures, at a thickness between about 200 to 500 Angstroms. An anneal procedure, performed using rapid thermal anneal, (RTA), or conventional furnace procedures, at a temperature between about 600 to 800° C., results in the formation of metal silicide, or titanium silicide layer 10, in regions in which the metal layer resided directly on silicon, or polysilicon surfaces Regions of the metal layer, residing either on L shaped, silicon nitride spacer 8b, in CMOS logic region 50, or on silicon nitride layer 8a, in CMOS memory region 60, remains unreacted. Removal of unreacted metal, or titanium, is accomplished selectively via use of a H₂SO₄—H₂O₂—HCl—NH₄OH solution, resulting in the desired salicide formation in CMOS logic region 50, with polysilicon gate to substrate shorts prevented by L shaped silicon nitride spacer 8b, which was formed from silicon nitride layer 8a. Non-salicided, CMOS memory region 60, were also protected from salicide formation via use of the same silicon nitride layer 8a. If desired a second anneal procedure can be used to reduce the resistance of metal silicide layers 10. The result of the salicide procedure is schematically shown in FIG. 7.

[0018] While this invention has been particularly shown and described with reference to, the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of this invention.