Apparatus and method to reduce node toggling in semiconductor devices

[0002] 1. Technical Field

[0003] This invention generally relates to semiconductor devices, and more specifically relates to power conservation in semiconductor devices.

[0004] 2. Background Art

[0005] The proliferation of electronics in our modern world is in large part due to integrated circuit semiconductor devices. Integrated semiconductor devices are designed and used in almost every electronic device today. In many applications power consumption is a critical issue for several reasons. For example, in portable devices such as wireless telephones, battery life and battery size is a primary design concern. Consumers want the portable electronic device to run as long as possible using a single battery charge and also want the device, including the battery to be as small and portable as possible. Thus, it is strongly desirable to be able to decrease power consumption of the device such that battery life can be extended and/or the size of the battery decreased.

[0006] In other applications power consumption is critical because it is directly related to the amount of heat generated by a device. A semiconductor device that consumes more power will generate more heat. In applications where heat sensitivity is a critical factor, reducing the power consumption reduces the heat generated by the device.

[0007] One factor that leads to excessive power consumption is unnecessary node toggling. In CMOS circuits, the power consumed is directly proportional to the size of the capacitive load being switched, and to the frequency with which it is being switched. In a typical random logic network, a given logic circuit output might switch many times in a single clock cycle before settling down on its final value. This phenomenon is due to the fact that in a multi-input circuit, input signals can arrive at different times due to different path delays and load conditions. Each time an input signal arrives, it can cause a switch on the output, causing unnecessary multiple switches each cycle that increase active power yet have no redemptive value since they have no effect on the final logic state.

[0008] Turning now to FIGS. 9-10, an exemplary logic gate 900 is illustrated in FIG. 9, and a timing chart 910 for the logic gate 900 is illustrated in FIG. 10. The logic gate 900 comprises an AND-OR-INVERTOR logic gate, but the problem is equally applicable to any type of logic circuit. The timing chart 910 illustrates how the unnecessary toggling can occur as a result of different inputs arriving at different times during a clock cycle. At the beginning of the clock cycle, at time T₁, the logic circuit starts out with a low output. Partially into the clock cycle, at time T₂, the input B change arrives. This change is propagated through the logic gate 900, and causes the output of the logic gate to toggle. At time T₃, input A change arrives, causing the output to toggle a second time. Finally, at time T₄, the input C changes, resulting in a third and final toggle. Thus, the output of the logic gate experienced two unnecessary toggles at times T₂and T₃before finally stabilizing at the final output at time T₄. These unnecessary toggles, generally called glitches, consume power as they charge and discharge any capacitance connected to the out, without producing useful work.

[0009] Therefore, there exists a need to provide reduced power consumption by reducing unnecessary node toggling in semiconductor devices.

[0010] According to the present invention, a device and method for reducing power consumption by reducing unneeded node toggling is provided. The preferred embodiment reduces unneeded node toggling in a circuit by holding portions of the logic circuit at their previous values until all the inputs to the logic circuit have stabilized to their final value. This results in a reduction of the number of unnecessary node toggling that occurs each cycle, reducing power. The present invention also provides a method for designing circuits that efficiently uses the node toggling reduction devices of the present invention.

[0011] The foregoing and other features and advantages of the invention will be apparent from the following more particular description of a preferred embodiment of the invention, as illustrated in the accompanying drawings.

[0012] The preferred exemplary embodiment of the present invention will hereinafter be described in conjunction with the appended drawings, where like designations denote like elements, and:

[0013] FIG. 1 is a schematic view of a device in accordance with the preferred embodiment;

[0014] FIG. 2 is a schematic view of a logic gate in accordance with the preferred embodiment;

[0015] FIG. 3 is a timing diagram for the logic gate of FIG. 2;

[0016] FIG. 4 is a schematic view of a enable signaler in accordance with the preferred embodiment;

[0017] FIG. 5 is a timing diagram for the enable signaler of FIG. 4;

[0018] FIG. 6 is a schematic view of an AND-OR-INVERTOR gate;

[0019] FIG. 7 is a schematic view of an AND-OR-INVERTOR in accordance with the preferred embodiment;

[0020] FIG. 8 is a flow diagram of a method for designing devices in accordance with the preferred embodiment;

[0021] FIG. 9 is a schematic view of a prior art logic gate; and

[0023] FIG. 10 is a timing diagram for the logic gate of FIG. 9

[0024] The preferred embodiment toggling reduction device reduces power consumption by reducing unneeded node toggling that commonly occurs in many types of logic circuits. The preferred embodiment reduces unneeded node toggling in a circuit by holding a portion of the device at the previous output until the all the inputs have stabilized to their final value during each clock cycle. This reduces power consumption in the device that would normally occur due to unnecessary node toggling.

[0025] Turning now to FIG. 1, an exemplary device 100 in accordance with the preferred embodiment is illustrated. Device 100 includes a circuit 102 having a plurality of inputs (A, B and C) and an output. The circuit 100 also includes an enable signaler 104 for controlling the enabling and disabling the circuit 102.

[0026] Circuit 102 can comprise any type of circuit in which unnecessary node toggling is to be prevented. Thus, circuit 102 can comprise one or more logic gates commonly used in digital devices. Circuit 102 can also comprise complex devices, such as circuits typically found in integrated devices such as arithmetic logic units (ALU), adders, multiplier, bus multiplexors, barrel shifters, etc. In the case of complex circuits the present invention can be applied at many points in the circuit, from the input stage to the output stage. Thus, in this application, the circuit 100 is defined to include of any of the types of circuits in which unnecessary node toggling can occur. Additional, a minimum toggle circuit is defined as one designed to facilitate disabling and enabling the output in accordance with the preferred embodiment.

[0027] In the preferred embodiment, the circuit 102 is enabled and disabled by enable signaler 104. In particular, when the circuit 102 is disabled by enable signaler 104, the output of the circuit 102 is temporarily held at its previous value. When the circuit 102 is enabled by the enable signal 104, the inputs of the circuit 102 are propagated to the output. Thus, by selectively enabling and disabling the circuit 102, excessive node toggling is reduced.

[0028] In the preferred embodiment, the circuit 102 is disabled by enable signaler 104 at the beginning of each clock cycle, and is enabled for that clock cycle only after all inputs the circuit 102 have stabilized. By disabling and enabling the circuit 102 during each clock cycle, the false toggles that would normally occur are eliminated. In addition to eliminating the unnecessary toggles of the circuit 102 output, the preferred embodiment also eliminates the toggles of those nets connected to the circuit 102 output. Because a single circuit can feed the inputs of many different elements, this can result in significant power savings.

[0029] In the preferred embodiment, the circuit 102 is enabled immediately following the stabilization of its last input. This allows the circuit 102 to provide the correct output as soon as possible while still reducing unnecessary node toggling.

[0030] Turning now to FIGS. 2 and 3, and the operation of an exemplary circuit in accordance with the preferred embodiment is illustrated. In FIG. 2, the exemplary circuit comprises an AND-OR-INVERTER logic gate 202. Again, in accordance with the preferred embodiment a enable signaler 104 is used to reduce unnecessary node toggling. In FIG. 3, a timing chart 310 illustrates the operation of logic gate 202 in the context of the preferred embodiment. The timing chart 310 illustrates how unnecessary node toggling is reduced by disabling the logic gate 202 until all the inputs to the logic gate have stabilized. At the beginning of the clock cycle, at time T₀, the logic circuit 202 has an a low output. In accordance with the preferred embodiment, the logic circuit 202 is disabled shortly after the start of clock cycle, time T₁, by providing a low enable signal. When the logic circuit 202 is disabled, the output of the logic circuit 202 is held at its previous value. Partially into the clock cycle, at time T₂, the input B change arrives. In the prior art, this change would be immediately propagated to the output, resulting in an unwanted and unnecessary node toggle. In the preferred embodiment, the output of the logic gate 202 is unchanged as a result of the low enable signal. At time T₃, input A change arrives. Again, in the prior art this would result in an unnecessary toggle, but in the preferred embodiment the output again remains unchanged. At time T₄, the input C change arrives. In the embodiment illustrated in FIG. 2, this is the last input to arrive. Thus, in the preferred embodiment, the logic circuit 202 is then enabled by activating the enable signal. This occurs at time T₅. Ideally, the enable signal should arrive as soon as possible after the last input has stabilized while assuring it does not arrive before. So preferably, T₅occurs on or shortly after T₄. With the logic gate enabled, the output of the logic gate 202 switches to its final value. Thus, the preferred embodiment prevents two unnecessary toggles in this example, while providing the correct output with minimal, if any, delay. In this application, the time between when the circuit is disabled (i.e., time T₁) and then enabled again (i.e., time T₅) will be referred to as the hold time.

[0031] Of course, it should be noted that the logic circuit 202 and the timing chart 310 are just exemplary of the type of circuits in which unnecessary node toggling can occur, and one specific example of how inputs could be received. The present invention is equally applicable to other types of circuits, and to other input characteristics.

[0032] Turning now to FIGS. 4-5, an exemplary enable signaler 400 in accordance with the preferred embodiment is illustrated in FIG. 4, and a exemplary timing chart 490 for the enable signaler 400 is illustrated in FIG. 5. The enable signaler 400 is designed to provide two enable signals at two different times during the clock cycle. Of course, outputs from the enable signaler 400 can be added or deleted as needed for a particular application. The enable signaler 400 includes a latch 402, an inverter 403, a delay 404, a delay 406, an exclusive-NOR (XNOR) gate 408, and an XNOR gate 410.

[0033] The latch 402 can be any type of latch that will propagate from the input to the output when the clock cycles. The latch 402 receives the clock signal into its clock input. In FIG. 5, the start of the first illustrated clock cycle is time T₁. The output of the latch 402 is fed back to its data input through inverter 403. This causes the output of latch 402 to toggle at the beginning of each clock cycle, with a short propagation delay caused by latch 402. Thus, in FIG. 5, the output of latch 402 (Node A) toggles at time T₂. The output change of latch 404, which is fed back to the input of latch 402 (Node B) though the inverter 403, will cause the latch 402 to toggle again at the beginning of the next clock cycle.

[0034] The output change of latch 402 also propagates to the XNOR gates, where it causes the XNOR gate outputs to go low after a short delay. Thus, in FIG. 5, enable signal 1 and enable signal 2 toggle at time T₃. The low output of the XNOR gates serves to disable the circuits which are connected to enable signal 1 and enable signal 2. At the same time, the output of latch 402 starts to propagate through the delays 404 and 406. After a time period approximately equal to that of delay 404, the latch output propagates to the second input of XNOR gate 408. Thus, in FIG. 5, the second input of XNOR gate 408 (Node C) goes high at time T₅. At XNOR 408, the delayed signal causes the output of XNOR gate 408 to again go high. Thus, in FIG. 5 the enable signal 1 goes high again at time T₆. The enable signal 1 is thus disabling the corresponding circuits from shortly after the start of the clock cycle (i.e., time T₃) to a time into the clock cycle approximately equal to that of the delay through latch 402 and delay 404 (i.e., time T₆).

[0035] The output of delay 404 also propagates through delay 406 to XNOR gate 410. Thus, in FIG. 5, the second input of XNOR gate 410 (Node D) goes high at time T₇. At XNOR gate 410, the twice-delayed signal causes the output of XNOR gate 410 to again go high. Thus, in FIG. 5, enable signal 2 goes high again at time T₈. Thus, the enable signal 2 is disabling its corresponding circuits from shortly after the start of the clock cycle (i.e., time T₃) to a time into the clock cycle approximately equal to that of the delay of latch 402 plus delay 404 plus the delay 406 (i.e., time T₈).

[0036] The same pattern occurs for each subsequent clock cycle. For example, at the next clock cycle (beginning at time T₉), the enable signal 1 is low between times T₁₁and T₁₃, and enable signal 2 is low between times T₁₁and T₁₅.

[0037] Thus, by appropriately selecting delay 404 and delay 406, two enable signals can be provided with two different hold times. Thus, different circuits, or the same circuit in different places can be disabled and enabled using a single signal enabler. Furthermore, additional delays and additional XNOR gates can be used to provide additional enable signals with different hold times.

[0038] Turning now to FIG. 6 a prior art implementation of an AND-OR-INVERTER logic gate 500. This shows a typical CMOS implementation of the logic gate. Turning now to FIG. 7, an AND-OR-INVERTOR 600 is shown with modifications for use in the preferred embodiment. In particular, transistors 602, 604, 606, and 608 have been added to facilitate the use of the enable signal to disable/enable the ANDOR-INVERTOR each clock cycle. When the enable signal is low, the output of the AND-OR-INVERTOR 600 is tri-stated, holding the output to its previous value. When the enable signal is high, the AND-OR-INVERTER 600 operates as the regular AND-OR-INVERTOR 500 illustrated in FIG. 6. Thus, the preferred embodiment can be easily implemented into existing designs by replacing the AND-OR-INVERTOR 500 with the AND-OR-INVERTOR 600 in places where it is expedient to do so. Of course, this is just one example of how one type of logic gate could be implemented for use with the preferred embodiment of the present invention.

[0039] Turning now to FIG. 8, a method 700 for design devices using the preferred embodiment is illustrated. The method results in the selective replacement of circuits in the design with minimum toggle circuits to reduce unwanted node toggling. The method starts out using design netlist data 750 and a simulation test suite 760 to perform a logic simulation in step 702. The design netlist data 750 preferably includes a gate level listing of all the elements in circuit and a listing of how those elements are interconnected. The simulation test suite 760 provides the data needed to perform a simulation of the circuit described by design netlist data 750. Thus, the test suite 760 preferably includes simulation vectors that approximate the typical operation of the device such that the switching factors reflect average operating conditions.

[0040] During the simulation of step 702, the switching factor is determined for each net, where the switching factor is proportional to the percentage of clock cycles during which the corresponding net switches. Thus, nets that are actively switching during most clock cycles would have a higher switching factor than nets that only actively switch a small portion of the clock cycles.

[0041] It should be noted that if switching factors from the logic simulation are not available, mathematical techniques can be used whereby statistical or probabilistic models can be used to generate switching factors from design netlist data 750. This can be down with tools such as IBM's Power Calc power calculator. This technique, however, is generally not as accurate as simulation.

[0042] Also during the simulation of step 704, the glitches per net is determined for each net. The glitches per net is proportional to the number of intermediate and unwanted toggles that occur each clock cycle the net is active. Thus, the glitches per net is proportional to the number of times that different input arrival times causes unwanted toggles. The number of glitches per net can be determined using a program that processes the waveform output generated during step 704 on a net by net basis.

[0043] It should be noted that instead of determining the glitches per net by simulation, the value could be estimated using circuit analysis techniques. This approach is not likely to be as accurate as performing the simulation, but it may be acceptable in some circumstances.

[0044] With the switching factor and glitches per net determined, the next step 704 is to perform a physical design analysis to determine the capacitance coupled to each net. This would typically involve measuring the capacitance of the net and all downstream logic. This can be done using any known analysis technique, such as tracing the logic network fed by the net using a network tracing program and adding up the capacitances of all the downstream nets. Such network tracing is usually available in schematic editors such as IBM's Wizard Tools and Cadence's Design Framework II. The capacitance attached to each net is an important factor because the power consumed by unwanted toggles is proportional to the capacitance of the attached net. The larger the capacitance, the larger the consumed power.

[0045] Preferably, the physical design capacitance is calculated from the final design, after it has been placed and routed with physical design tools such as IBM's Chipbench tool or Cadence's Cell Ensemble. If such physical design capacitances are not available, the capacitance per net can be estimated by using a capacitance load fanout model on the design netlist data 750.

[0046] The next step 706 is to evaluate the switching factor, glitches, and capacitance of each net to determine if the corresponding circuit should be replaced with a minimum toggle circuit. In the preferred embodiment this is done by computing an overall effect value for each net. For example, the overall effect can be computed as follows:

[0047] OE=αS+βG+γC  (1)

[0048] where OE is the overall effect, S is the switching factor, G is the glitches per cycle and C is the capacitance, and alpha, beta and gamma are constants used to adjust the relative effect of those factors.

[0049] If the overall effect value exceeds a predetermined amount, the corresponding circuit should be replaced with a minimum toggle circuit. If the overall effect value is less than the predetermined amount, the regular circuit is used. The predetermined amount could be determined by a variety of factors, such as the relative need for power efficiency balanced against the need to achieve high density. For example, if the final density of the device is of significant concern, the predetermined value can be set higher to assure that a relatively small number of standard circuits are replaced with relatively larger minimum toggle circuits.

[0050] With the nets evaluated, the next step 708 is to replace those circuits having the specified overall effect greater than the predetermined amount with minimum toggle circuits. This step would preferable use a database 770 of minimum toggle circuits that contains a minimum toggle circuit for each of the types of circuits in the design netlist. In the preferred embodiment, those circuits having the largest overall effect are replaced first until all the remaining silicon die is used or until all the circuits having the minimum overall effect have been replaced. At each step in this process, the power consumption an be incrementally re-calculated based upon the new logic network.

[0051] The next step 710 is to provide enable signalers as needed to provide enable signals with the appropriate hold time. This is preferably done by using a static timing analysis tool, such as IBM's Einstimer to determine the typical arrival times of all the inputs to the circuit. The enable signalers will then be used to selectively disable and enable the minimum toggle circuits during each clock cycle to minimize unnecessary node toggling.

[0052] In the preferred embodiment, the addition of the enable signalers and the conversion from standard circuits to minimum toggle circuits is done with extension language routines available under a logic synthesis program such as IBM's Booledozer. The extension language provides mechanisms for the addition or deletion of circuits as well as the ability to change circuit connections.

[0053] With the enable signalers provided, the result is a design netlist 780 that has minimum toggle characteristics, resulting in improved power consumption. Thus, the preferred embodiment of the present invention provides a device and method for reducing power consumption by reducing unneeded node toggling. The preferred embodiment reduces unneeded node toggling in a circuit by holding portions of the logic circuit at their previous values until all the inputs to the logic circuit have stabilized to their final value. This results reducing the number of unnecessary node toggling that occurs each cycle, reducing power.

[0054] The preferred embodiment can be used in a wide variety of applications. For example, in a digital signal processor the preferred embodiment can be implemented in the decode logic unit at a natural pinch point, where a handful of nets end up controlling thousands of gates every cycle. In the prior art, many unnecessary toggles occurred at the pinch point, causing excessive node toggling of the downstream logic. By using the preferred embodiment, this node toggling can be significantly reduced.

[0055] As another example, the preferred embodiment can be used by incorporating it in an input stage for a multiplier. The preferred embodiment blocks propagation of the input data from going into the multiplier until the data at its inputs is stable. Without this, the multiplier would multiply several times in a cycle as the value at the data input changes. The preferred embodiment can also be used inside the multiplier to further reduce unnecessary toggles, although this power savings is not likely to be as significant.

[0056] While the invention has been particularly shown and described with reference to a preferred exemplary embodiment thereof, it will be understood by those skilled in the art that various changes in form and details may be made therein without departing from the spirit and scope of the invention. It will be also understood that, while various of the conductors are shown in the drawing as single lines, they are not so shown in a limiting sense, and may comprise plural conductors, as is understood in the art.