Individual source line to decrease column leakage

[0002] 1. Field of the Invention

[0003] This invention relates generally to the art of microelectronic integrated circuits. More specifically, this invention relates to flash Electrically Erasable Programmable Read Only Memory (EEPROM) devices. Even more specifically, this invention relates to an architecture of flash Electrically Erasable Programmable Read Only Memory (EEPROM) devices and a method to read the flash Electrically Erasable Programmable Read Only Memory (EEPROM) devices to reduce column leakage during read.

[0004] 2. Discussion of the Related Art

[0005] A class of non-volatile memory devices known as “flash” EEPROM (Electrically Erasable Programmable Read Only Memory) devices combines the advantages of EPROM density with the electrical erasability of an EEPROM. One feature that distinguishes flash EEPROM memory cells from standard EEPROM memory cells is that unlike standard EEPROM memory cells, flash EEPROM memory cells do not contain a select transistor on a one-for-one basis with each floating gate memory cell. A select transistor is a transistor that allows the selection of an individual memory cell within the memory device and is used to selectively erase a specific memory cell. Because flash EEPROMs do not have a select transistor for each floating gate transistor, flash EEPROM memory cells cannot be individually erased and therefore must be erased in bulk, either by erasing the entire chip or by erasing paged groups or banks of cells. Elimination of the select transistor allows for smaller cell size and gives the flash EEPROM an advantage in terms of manufacturing yield (in terms of memory capacity) over comparably sized standard EEPROMs.

[0006] Typically, a plurality of flash EEPROM cells is formed on a semiconductor substrate, which is also known as a silicon wafer. FIG. 1A illustrates a single conventional flash EEPROM memory cell having a double-diffused source region. As shown in FIG. 1, flash memory cell 100 is formed on a p-type substrate 110 and includes an n type double-diffused source region 102 and an n+ drain region 104. The drain region 104 and the source region 102 are spaced apart from each other forming a channel L_CHANNEL122. A source electrode 114 and a drain electrode 112 are connected to the source region 102 and the drain region 104, respectively. A substrate electrode 105 is connected to the substrate 110.

[0007] The double-diffused source region 102 is formed of a lightly doped n region 128 (phosphorous doped) and a more heavily doped but shallower n+ region 130 (arsenic doped) embedded within the deep n region 128. The phosphorus doping within the n region 128 reduces the horizontal electric field between the source region 102 and the substrate 110.

[0008] The floating gate 106 is disposed a short distance above the source region 102, the drain region 104 and the channel L_CHANNEL122, and over a dielectric layer 118, which is also known as a tunnel oxide region. Above the floating gate 106 and disposed over the dielectric layer 116 is a control gate 108. The dielectric layer 116 is typically formed of an oxide/nitride/oxide layer known in the semiconductor manufacturing art as an ONO layer. A control gate electrode 120 is attached to control gate 108. The dimension L_GATE132 represents the gate length for the gates contained in flash memory cell 100.

[0009] In a conventional method of operation, the programming of a flash EEPROM memory cell is achieved by inducing “hot electron” injection from a section of the channel 122 near the drain 104 into the floating gate 106. The injected electrons cause the floating gate 106 to carry a negative charge. Grounding the source region 102, biasing the control gate 108 to a relatively high positive voltage and biasing the drain region 104 to a moderate positive voltage induce the hot electrons.

[0010] For example, to program the flash memory cell 100 the source electrode 114 is connected to ground, the drain electrode 112 is connected to a relatively high voltage (typically +4 volts to +9 volts) and the control gate electrode 120 is connected to a relatively high voltage level (typically +8 volts to +12 volts). Electrons are accelerated from source region 102 to drain region 104 via the channel 122 and the “hot electrons” are generated near the drain region 104. Some of the hot electrons are injected through he relatively thin gate dielectric layer 118 and become trapped in the floating gate 106 thereby giving floating gate 106 a negative potential.

[0011] After sufficient negative charge accumulates on floating gate 106 the negative potential of floating gate 106 raises the threshold voltage of the stacked gate transistor and inhibits current flow through the channel 122 during a subsequent “read” mode. The magnitude of the read current is used to determine whether a memory cell has been programmed.

[0012] Conversely, to erase a flash memory device electrons are typically driven out of the floating gate 106 by biasing the control gate 108 to a large negative voltage and biasing the source region 102 to a low positive voltage in order to produce a sufficiently large vertical electric field in the tunnel oxide. The large vertical field in the tunnel oxide produces Fowler-Nordheim (F-N) tunneling of electrons stored in the floating gate 106 through the tunnel oxide into the source region 102. The charge removed from the floating gate 106 produces a threshold voltage shift.

[0013] For example, during erasure a relatively low positive voltage (typically from +0.5 volts to +5 volts) is applied to source electrode 114 and a relatively large negative voltage (typically from −7 volts to −13 volts) is applied to control gate electrode 120. The voltage of the substrate electrode 105 is grounded and the drain electrode 112 is allowed to float. The vertical electric filed established between the control gate 108 and the source region 102 induces electrons previously stored in floating gate 106 to pass through dielectric layer 118 and into source region 102 by way of Fowler-Nordheim tunneling.

[0014] In order to produce a sufficient electric field in the tunnel oxide, it is typically necessary to bias the control gate 108 to a large enough negative voltage such that the floating gate 106 reaches a voltage of approximately −5.5 volts. A typical potential difference V_SFbetween the source region 102 and floating gate 106 is on the order of 10 volts and accordingly, when the source voltage V_sis made less positive the control gate voltage V_CGshould be made more negative. Once the source to floating voltage V_SFis selected, the remaining factors are preferably constrained according to the equation:

[0015] V_FG=α_CG(V_CG−ΔV_T)+α_SV_S+α_BV_B

[0016] where:

[0017] V_FG=the floating gate voltage;

[0018] V_CG=the control gate voltage;

[0019] V_S=the source voltage;

[0020] V_B=the substrate or p-well bias;

[0021] ΔV_T=the threshold voltage difference arising from negative charge added to the floating gate as measured from the control gate;

[0022] α_CG=the capacitive coupling coefficient from the control gate to the floating gate;

[0023] α_S=the capacitive coupling coefficient between the source and the floating gate;

[0024] α_B=the capacitive coupling coefficient between the substrate or p-well and the floating gate.

[0025] The cell is read by applying typically 4 to 5 volts to the control gate, approximately 1 volt or less to the bitline to which the drain is connected, grounding the source, and sensing the bitline current. If the cell is programmed and the threshold voltage is relatively high (≈4 volts), the bitline current will be zero or at least relatively low. If the cell is not programmed or erased, the threshold voltage will be relatively low (≈2 volts), the control gate voltage will enhance the channel, and the bitline current will be relatively high.

[0026] To have high enough read current, the voltage at the gate is required to be 4 to 5 volts. Because the source is grounded (0 volts), this relatively large potential difference exists across the tunnel oxide in the vicinity of the source region and causes a stress field across the tunnel oxide in the vicinity of the source region during the duration of the read pulse. Because all of the sources have a common terminal, this stress field is applied across all the bits on the selected wordline. Due to oxide integrity weakness from bit-to-bit, some bits will gain charge and disturb the state of the bits. Blank “1” cells could be programmed and turn to a “0” causing a failure of the flash device after many read cycles. The field across the tunnel oxide is highest close to the source junction. The “thin” tunnel oxide at the source side experiences most of the degradation during cycling, becoming weak thereby allowing conduction through it at lower applied electric fields. In addition, because the bitline to which the cell being read has a voltage applied to it all of the cells connected to that bitline will have a potential difference between the drain and the source because all of the sources are connected to a common terminal. As discussed above, if the threshold voltage of an unselected cell or a number of unselected cells has decreased, the leakage current may mask the expected read current and a faulty read will occur. This will result in failure of the entire memory device.

[0027] Therefore, what is needed is a method of reading the memory device to minimize the number of times the relatively large potential difference is applied across each individual cell during read and to decrease the leakage current in the bitlines during read.

[0028] According to the present invention, the foregoing and other objects and advantages are obtained by a memory device and a method of reading the memory device that reduces the leakage current in the bitline of the cell being read.

[0029] In accordance with one aspect of the invention, the memory device has a source line control circuit connected to a source line that is connected to all the sources of memory cells in a row. During read only the source line connected to the source of the selected memory cell to be read is attached to ground. The source lines connected to the sources of unselected cells are left open.

[0030] In accordance with another aspect of the invention, the source line control circuit is controlled by the voltage applied to the wordline that is attached to the control gate of the selected cell to be read.

[0031] The described method thus provides a memory device and a method of reading the memory device that reduces the leakage current in the bitlines to which the selected cell to be read is attached.

[0032] The present invention is better understood upon consideration of the detailed description below, in conjunction with the accompanying drawings. As will become readily apparent to those skilled in the art from the following description, there is shown and described an embodiment of this invention simply by way of illustration of the best mode to carry out the invention. As will be realized, the invention is capable of other embodiments and its several details are capable of modifications in various obvious aspects, all without departing from the scope of the invention. Accordingly, the drawings and detailed description will be regarded as illustrative in nature and not as restrictive.

[0033] The novel features believed characteristic of the invention are set forth in the appended claims. The invention itself, however, as well as a preferred mode of use, and further objects and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

[0034] FIG. 1 shows the architecture of a typical flash memory cell with a double diffused source region;

[0035] FIG. 2A shows the architecture of a portion of a typical flash memory device;

[0036] FIG. 2B shows the voltages applied to the selected and unselected wordlines, bitlines and sources during a read operation of the flash memory device shown in FIG. 2A;

[0037] FIG. 2C is a simplified electrical schematic diagram of a column of flash EEPROM cells illustrating the leakage currents from overerased or low threshold voltage memory cells;

[0038] FIG. 3A shows a the architecture of a portion of a flash memory device in accordance with the⁴present invention; and

[0039] FIG. 3B shows the voltages applied to the selected and unselected wordlines, bitlines and sources during a read operation of the flash memory device shown in FIG. 3A.

[0040] Reference is now made in detail to specific embodiments of the present invention that illustrate the best mode presently contemplated by the inventors for practicing the invention.

[0041] FIG. 2A shows the basic configuration of a portion 200 of a NOR type flash Electrically Erasable Programmable Read-Only Memory (EEPROM) of a typical flash memory device. The portion 200 of the flash memory device comprises a plurality of core or memory cells, which are arranged in a rectangular matrix or array of rows and columns. Each row is associated with a wordline (WL), whereas each column is associated with a bitline (BL).

[0042] Assuming that there are n columns and m rows, the bitlines are designated as BL₀to BL_n, and the wordlines are designated as WL₀to WL_m. Appropriate voltages are applied to the bitlines by a bitline driver (not shown), whereas appropriate voltages are applied to the wordlines by a wordline driver (not shown).

[0043] A memory cell is located at each junction of a wordline and a bitline. Each cell includes a Metal-Oxide-Semiconductor (MOS) Field Effect Transistor (FET) having a source and drain formed in a semiconductor substrate, a floating gate, and a control gate separated from the floating gate by a layer of oxide. As should be appreciated, the cells of a flash EEPROM differ from conventional FETs in that they include the floating gate and tunnel oxide layer disposed between the control gate and the semiconductor substrate in which the source and drain are formed.

[0044] The cells illustrated in FIG. 2A are designated using the notation T_n,m, where m is the row (wordline) and n is the column (bitline). The control gates of the cells are connected to respective wordlines and the drains of the cells are connected to respective bitlines as illustrated. The sources of all of the cells are connected to the common terminal at V_s.

[0045] FIG. 2B lists the voltages applied to the selected and unselected wordlines and bitlines and shows the voltage applied to the common source terminal. In accordance with the values listed in FIG. 2B, if transistor T_2,2is to be read, a voltage of approximately 1 volt is applied to BL₂and because all of the sources are connected to ground at terminal V_Sthere will be a potential difference (drain to source) V_DSacross all of the transistors connected to BL₂and each of these transistors could contribute to the leakage current sensed on BL₂that could mask the proper read current. In addition, because a voltage of approximately 4 to 5 volts is applied to WL₂and all of the sources are connected to ground at terminal V_S, all of the cells connected to WL₂will have a potential difference (gate to source) V_GSof approximately 4 to 5 volts. As discussed above, this potential difference can cause stress of the tunnel oxide in the region of the source. This stress will decrease the reliability of the memory device.

[0046] The undesirable effect of leakage current is illustrated in FIG. 2C, which is a simplified electrical schematic diagram of a column 202 of flash EEPROM cells, 204, 206, 208 and 210. The sources of the column 202 of transistors are all connected to a source supply voltage V_s. A read voltage is applied to the control gate of the transistor 206, which turns it on. A current I₂flows through the transistor 206 from ground through its source, channel (not shown) and drain. Ideally, the bitline current I_BLis equal to 12. However, if one or more of the unselected transistors, for example transistors 204, 208 or 210 as illustrated in FIG. 2C, are overerased or slightly overerased, their threshold voltages will be very low, zero or even negative, and background leakage currents I₁,I₃. and I₄could flow through the transistors 202, 208 and 210, respectively. The bitline current I_BLwould then be equal to the sum of 12 and the background leakage currents I₁,I₃and I₄. In a typical flash EEPROM, the drains of a large number of memory transistor cells, for example 512 transistor cells are connected to each bitline. If a substantial number of cells on the bitline are drawing background leakage current, the total leakage current on the bitline can exceed the cell read current. This makes it impossible to read the state of any cell on the bitline and therefore renders the memory inoperative.

[0047] FIG. 3A shows the basic configuration of a portion 300 of a NOR type flash Electrically Erasable Programmable Read-Only Memory (EEPROM) of a flash memory device in accordance with the present invention. The portion 300 of the flash memory device comprises a plurality of core or memory cells, which are arranged in a rectangular matrix of rows and columns. Each row is associated with a wordline (WL), whereas each column is associated with a bitline (BL).

[0048] Similar to the prior art device shown in FIG. 2A, assuming there are n columns and m rows, the bitlines are designated as BL₀to BL_n, and the wordlines are designated as WL₀to WL_m. A bitline driver (not shown) applies appropriate voltages to the bitlines and a wordline driver (not shown) applies appropriate voltages to the wordlines.

[0049] A memory cell is located at each junction of a wordline and a bitline. Each cell includes a Metal-Oxide-Semiconductor (MOS) Field Effect Transistor (FET) having a source and drain formed in a semiconductor substrate, a floating gate, and a control gate separated from the floating gate by a layer of oxide. As should be appreciated, the cells of a flash EEPROM differ from conventional FETs in that they include the floating gate and tunnel oxide layer disposed between the control gate and the semiconductor substrate in which the source and drain are formed.

[0050] The cells illustrated in FIG. 3A are designated using the notation T_n,m, where m is the row (wordline) and n is the column (bitline). The control gates of the cells are connected to respective wordlines and the drains of the cells are connected to respective bitlines as illustrated. Each wordline is connected to a respective source line control circuit. For example, wordlines WL₂and WL₃are connected to source line control circuit 302 and wordlines WL₄and WL₅are connected to source line control circuit 304. Each source line control circuit connects a respective source line to a source terminal V_S. As an example, source line control circuit 302 controls the connection of source line SL₂to terminal V_S. The source line control circuit 302 includes a first transistor 306 that is turned on by wordline WL₂and thereby connects source line SL₂to terminal V_S. The source line control circuit 302 also includes a second transistor 308 that is turned on by wordline WL₃and thereby connects source line SL₂to terminal V_S. In the present configuration, the wordlines control the state of the associated source line control circuit.

[0051] FIG. 3B lists the voltages applied to the selected and unselected wordlines and shows the voltage applied to the source of the selected cell. In accordance with the values listed in FIG. 3B, if transistor T₂,₂is to be read, a voltage of approximately 1 volt is applied to BL₂and a voltage of approximately 4-5 volts is applied to WL₂that causes transistor 306 to turn on and connects source line SL₂to V_S, which is set to ground. The unselected source lines are set to either open or a high enough voltage so that there is no potential difference VDs across unselected cells on BL₂. The absence of the potential difference V_DSprevents leakage current from the unselected cells.

[0052] In summary, the present invention overcomes the limitations of the prior art and reduces the amount of leakage current present in the sensed bitline current during a read operation.

[0053] The foregoing description of the embodiment of the invention has been presented for purposes of illustration and description. It is not intended to be exhaustive or to limit the invention to the precise form disclosed. Obvious modifications or variations are possible in light of the above teachings. The embodiment was chosen and described to provide the best illustration of the principles of the invention and its practical application to thereby enable one of ordinary skill in the art to utilize the invention in various embodiments and with various modifications as are suited to the particular use contemplated. All such modifications and variations are within the scope of the invention as determined by the appended claims when interpreted in accordance with the breadth to which they are fairly, legally, and equitably entitled.