Driver circuit and method for controlling transition time of a signal

[0002] The present invention relates, in general, to integrated circuits and, more particularly, to driver circuits for integrated circuit pads.

[0003] Integrated circuits have metal pads for interconnection to circuitry external to the integrated circuit. The metal pads of the integrated circuit are coupled for sending and receiving input and output signals. The metal pads are the interface circuitry between circuitry external and internal to the integrated circuit.

[0004] Integrated circuits have output driver circuitry for transmitting output signals from the integrated circuit. The output driver circuitry is necessary because of capacitance loads that appear at the metal pad when the integrated circuit is interconnected with other circuitry. The output driver charges and discharges the capacitive load to a predetermined voltage level within a specified time interval.

[0005] A conventional output driver has two series connected transistors, a pull-up transistor and a pull-down transistor. The pull-up transistor is used to drive the pad to a logic high voltage level, referred to as a logic 1. The pull-down transistor is used to drive the pad to a logic low voltage level, referred to as a logic 0. For sub-micron semiconductor devices employing a conventional output driver, many factors can adversely affect the transition times, i.e., the rise and fall times, of the output signal between binary logic voltage levels. These factors include the process used for fabrication (e.g., bipolar vs. Complementary Metal Oxide Semiconductor (CMOS)), operating temperatures, load capacitance, and power supply voltages. Any variations in one of these factors, such as a change in the load capacitance, will cause the rise and fall times of the output signal to vary. The transition time of a signal is also referred to as a slew rate of the signal.

[0006] Accordingly, it would be advantageous to have an output driver for sub-micron semiconductor devices that generates output signals having controlled rise and fall times. It would be of further advantage for the output driver to be area efficient and compatible with standard semiconductor processes.

[0007] FIG. 1 is a schematic diagram of an output circuit coupled to an output pad;

[0008] FIG. 2 is a graph of a first reference signal and an output signal of the output circuit of FIG. 1; and

[0009] FIG. 3 is a graph of a second reference signal and the output signal of the output circuit of FIG. 1.

[0010] FIG. 1 is a schematic diagram of an output circuit 10, also referred to as an output driver circuit, coupled to an output pad 11. Output circuit 10 receives an input signal labeled V_INat an input terminal 12 and provides an output signal labeled V_OUTat pad 11. Signals V_INand V_OUTmay contain data for transmission to circuitry external to circuit 10 and therefore can be referred to as data signals.

[0011] Output circuit 10 includes slope generators 16 and 17. Slope generators 16 and 17 affect the slope of signal V_OUT. In particular, slope generator 16 affects the rise time of signal V_OUTand is referred to as a positive slope generator. Slope generator 17 affects the fall time of signal V_OUTand is referred to as a negative slope generator.

[0012] Slope generator 16 includes a p-channel Field Effect Transistor (FET) 18 and an n-channel FET 19. The gate electrodes of FETs 18 and 19 are coupled for receiving signal V_IN. The source electrode of FET 18 is coupled to a power supply terminal 13 for receiving a source of operating potential or power supply voltage such as, for example, supply voltage V_DD, via a current source 14. The source electrode of FET 19 is coupled to a power supply terminal 15 for receiving a power supply voltage such as, for example, supply voltage V_SS. By way of example, supply voltage V_DDis approximately five volts and supply voltage V_SSis approximately zero volts. The drain electrode of FET 18 is connected to the drain electrode of FET 19. Slope generator 16 further includes a capacitor 26. Capacitor 26 has a first terminal connected to the drain electrodes of FETs 18 and 19 and a second terminal coupled for receiving power supply voltage V_SS.

[0013] Slope generator 17 includes a p-channel FET 21 and an n-channel FET 22. The gate electrodes of FETs 21 and 22 are coupled for receiving signal V_IN. The source electrode of FET 21 is coupled to a power supply terminal 23 for receiving power supply voltage V_DD. The source electrode of FET 22 is coupled to a power supply terminal 25 for receiving power supply voltage V_SSvia a current source 30. The drain electrodes of FETs 21 and 22 are connected to each other. Slope generator 17 further includes a capacitor 27. Capacitor 27 has a first terminal connected to the drain electrodes of FETs 21 and 22 and a second terminal coupled for receiving power supply voltage V_SS.

[0014] Although transistors 18, 19, 21, and 22 are shown as FETS, this is not a limitation of the present invention. For example, transistors 18, 19, 21, and 22 can be bipolar transistors. Transistors used in output circuit 10 are understood to provide a conduction path between first and second conduction electrodes when a control signal is applied to a control electrode. It should be noted that the gate electrode of a FET is referred to as a control electrode and the drain and source electrodes of a FET are referred to as current carrying electrodes or conduction electrodes. Likewise, the base of a bipolar transistor is referred to as the control electrode and the collector and emitter electrodes of the bipolar transistor are referred to as conduction electrodes.

[0015] Output circuit 10 further includes amplifiers 28 and 29, switches 31 and 32, and FETs 36-39. An inverting input terminal of amplifier 28 is connected to the first terminal of capacitor 26 and a noninverting input terminal of amplifier 28 is connected to pad 11 via a feedback path 51. FET 36 is an n-channel FET having a gate electrode connected to the first terminal of capacitor 26, a drain electrode coupled for receiving supply voltage V_DD, and a source electrode connected to pad 11. FET 37 is a p-channel FET having a gate electrode connected to the output terminal of amplifier 28, a drain electrode coupled for receiving supply voltage V_DD, and a source electrode connected to pad 11. Switch 31 is connected between the gate of FET 37 and supply voltage V_DD.

[0016] An inverting input terminal of amplifier 29 is connected to the first terminal of capacitor 27 and a noninverting input terminal of amplifier 29 is connected to pad 11. FET 38 is a p-channel FET having a gate electrode connected to the first terminal of capacitor 27, a drain electrode coupled for receiving power supply voltage V_SS, and a source electrode connected to a pad 11. FET 39 is an n-channel FET having a gate electrode connected to the output terminal of amplifier 29, a drain electrode coupled for receiving power supply voltage V_SS, and a source electrode connected to pad 11. Switch 32 is connected between the gate electrode of FET 39 and power supply voltage V_SS.

[0017] Output circuit 10 can be fabricated using a semiconductor process that can integrate both bipolar and Metal Oxide Semiconductor (MOS) transistors on the same semiconductor die. The principles of the present invention are not limited to such a process, but can equally be applied to other semiconductor processes as well.

[0018] FETs 18 and 19 charge and discharge capacitor 26 based on the voltage level of signal V_IN. When the voltage of input signal V_INat input terminal 12 switches from a logic high voltage level, e.g., voltage V_DD, to a logic low voltage level, e.g., voltage V_SS, FET 18 is switched on and FET 19 is switched off. Thus, FET 18 is conductive, i.e., a conduction path from the source electrode of FET 18 to the drain electrode of FET 18 is enabled. Therefore, a charging current flowing through FET 18 charges capacitor 26, thereby increasing the voltage of a reference signal V_REF1. As capacitor 26 is charged, the voltage of signal V_REF1, rises from approximately voltage V_SSto approximately voltage V_DDThe operation of output circuit 10 is further described with reference to FIG. 2.

[0019] FIG. 2 is a graph of signals V_REF1and V_OUTof output circuit 10. It should be understood that the same reference numerals are used in the figures to denote the same elements. Although not shown in FIG. 2, the voltage of signal V_INremains at a logic low voltage level between times T₁and T₅so that FET 18 (FIG. 1) is on and FET 19 is off. What is shown in FIG. 2 is signal V_REF1rising from an initial voltage level of V_SSat time T₁to a final voltage level of V_DDat time T₅. The time it takes for signal V_REF1to rise from an initial voltage level of V_SSto a final voltage level of V_DDis referred to as the rise time of signal V_REF1. The rise time of signal V_REF1is the time between times T₁and T₅. Those skilled in the art will understand that rise time may also mean the time it takes for a signal to rise from ten percent of its final voltage level to ninety percent of its final voltage level. The rise time of signal V_REF1, is set by a charging current through FET 18 and the capacitance of capacitor 26. In other words, the rise time of signal V_REF1is equal to the amount of time it takes to charge capacitor 26 to a final voltage level of approximately V_DD. Thus, the rise time of signal V_REF1is a function of the capacitance of capacitor 26 and the amount of charging current supplied by current source 14. For example, increasing the capacitance of capacitor 26 and/or decreasing the amount of charging current supplied by current source 14 can increase the rise time of signal V_REF1. On the other hand, decreasing the capacitance of capacitor 26 and/or increasing the amount of charging current supplied by current source 14 can decrease the rise time of signal V_REF1. It should be understood that the gate electrode of FET 36 has capacitance that will affect the rise time of V_REF1.

[0020] Referring to FIGS. 1 and 2, at time T₂, the voltage of signal V_REF1increases to a level greater than the threshold voltage of FET 36 (denoted as VT₃₆in FIG. 2), and FET 36 turns on and is conductive. The voltage of signal V_OUTbegins to rise from an initial voltage level of approximately V_SS. FET 36 is operated as a voltage follower. In this embodiment, FET 36 is a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) configured as a source follower, wherein the gate electrode or input is coupled to the first terminal of capacitor 26 and the source electrode or output provides a follower voltage at output pad 11. Alternatively, transistor 36 can be another type of device that performs a voltage follower function. For example, transistor 36 can be implemented as a bipolar transistor operating as an emitter follower, wherein the base electrode of the bipolar transistor serves as an input and the emitter electrode serves as the output for providing a follower voltage. FET 36 is configured to charge a capacitive load (not shown) at output pad 11 with little or no delay so that the follower voltage at the output of FET 36, i.e., signal V_OUT, closely tracks the voltage at the input of FET 36, i.e., signal V_REF1.

[0021] Preferably, amplifier 28 is enabled or active after the voltage of V_REF1rises above the threshold voltage of FET 36 at time T₂. The bandwidth and the input common mode range of amplifier 28 can be modified to delay enabling amplifier 28 and to increase stability of the loop formed by amplifier 28 and FET 37.

[0022] In this embodiment, amplifier 28 is enabled at time T₃. When amplifier 28 is enabled, amplifier 28 compares the voltage at its inverting and noninverting input terminals to generate a compare signal at its output terminal for enabling a conduction path between the source and drain electrodes of FET 37. FET 37 alters the voltage of signal V_OUTso that the transition time of signal V_OUTis substantially equal to the transition time of the signal V_REF1.

[0023] At time T₃, amplifier 28 compares signal V_REF1received at its inverting input terminal to signal V_OUTreceived at its noninverting input terminal. Signal V_OUTis received at the noninverting input terminal of amplifier 28 via feedback path 51. Since the voltage of signal V_REF1, is greater than the voltage of signal V_OUT, a logic low voltage is transmitted from the output terminal of amplifier 28 to the gate electrode of FET 37. Therefore, FET 37 is on and conducts a current through FET 37 for charging the load capacitance at output pad 11, thereby increasing the voltage of signal V_OUTtowards the voltage of signal V_REF1.

[0024] Between times T₃and T₄the voltages of signals V_REF1and V_OUTincrease towards supply voltage of Between times T₄and T₅the voltage of signal V_OUTis substantially equal to the voltage of signal V_REF1. At time T₅, the voltages of signals V_REF1and V_OUTare approximately equal to supply voltage V_DD.

[0025] Amplifier 28 and FET 37 regulate the voltage of signal V_OUTso that the voltages of signals V_REF1and V_OUTremain substantially equal after time T₄. That is, after time T₃, amplifier 28 continuously compares signals V_REF1and V_OUTand generates a compare signal at the output terminal of amplifier 28 for turning FET 37 on as long as amplifier 28 is active. When the voltage of signal V_REF1is greater than the voltage of signal V_OUT, amplifier 28 transmits a logic low voltage from the output terminal of amplifier 28 to the gate electrode of FET 37, which turns FET 37 on and increases the voltage of signal V_OUT.

[0026] Since the voltage of signal V_OUTtracks the voltage of signal V_OUTand amplifier 28 and FET 37 regulate the voltage of signal V_OUT, the rise time of signal V_OUTis substantially equal to the rise time of signal V_REF1. Therefore, similar to the rise time of V_REF1discussed hereinbefore, the rise time of signal V_OUTis a function of the capacitance of capacitor 26 and the amount of current supplied by current source 14. Thus, a circuit designer can control or predetermine the rise time of signal V_OUTwith current source 14 and the capacitance of capacitor 26, independent of the capacitive load at pad 11.

[0027] FIG. 3 is a graph of signals V_REF1and V_OUTof output circuit 10. Referring to FIGS. 1 and 3, signal V_INis at a logic low voltage level prior to time T₆. Thus, FET 21 is conductive and FET 22 is nonconductive. A current flowing through FET 21 charges capacitor 27 and increases the voltage of signal V_REF2to a voltage approximately equal to supply voltage V_DD. As discussed hereinbefore, the voltage of signal V_OUTrises to a voltage level equal to approximately supply voltage V_DDwhen signal V_INis at a logic low voltage level.

[0028] At time T₆, V_INswitches from a logic low voltage level to a logic high voltage level. FET 22 is switched on and FET 21 is switched off. A current flowing through FET 22 discharges capacitor 27, which causes the voltage of signal V_REF2to decrease from supply voltage V_DD, towards supply voltage V_SS. The voltage of signal V_INremains at a logic high voltage level between times T₆and T₁₀so that FET 22 remains conductive and FET 21 remains nonconductive.

[0029] Between times T₆and T₁₀, the voltage of signal V_REF2decreases from supply voltage V_DDto supply voltage V_SS. The time it takes for signal V_REF2to decrease from supply voltage V_DDto supply voltage V_SSis referred to as the fall time of signal V_REF2. Therefore, the fall time of signal V_REF2is the time between times T₆and T₁₀. Those skilled in the art will understand that fall time may also mean the time it takes for a signal to fall from ninety percent of its final voltage level to ten percent of its final voltage level. The fall time of signal V_REF2is set by the discharging current through FET 22 and the capacitance of capacitor 27. In other words, the fall time of signal V_REF2is equal to the amount of time it takes to discharge capacitor 27 to a final voltage level of approximately V_SS. Thus, the fall time of signal V_REF2is a function of the capacitance of capacitor 27 and the amount of current sunk by current source 30. For example, increasing the capacitance of capacitor 27 and/or decreasing the amount of discharging current through FET 22 using current source 30 can increase the fall time of signal V_REF2. On the other hand, the fall time of signal V_REF2can be decreased by decreasing the capacitance of capacitor 27 and/or increasing the amount of discharging current through FET 22 using current source 30. It should be understood that the gate electrode of FET 38 has capacitance that will affect the fall time of V_REF2.

[0030] At time T₇, the voltage of signal V_REF2decreases to a level less than the threshold voltage of FET 38 (denoted as V_DD−V_T38in FIG. 2), and FET 38 turns on and is conductive. The voltage of signal V_OUTbegins to decrease from voltage V_DD.

[0031] Preferably, amplifier 29 is enabled or active after the voltage of V_REF2falls below the threshold voltage of FET 38 at time T₇. The bandwidth and the input common mode range of amplifier 29 can be modified to delay enabling amplifier 29 and to increase stability of the loop formed by amplifier 29 and FET 39.

[0032] In this embodiment, amplifier 29 is enabled at time T₈. When amplifier 29 is enabled, amplifier 29 compares the voltage at its inverting and noninverting input terminals to generate a compare signal at its output terminal for enabling a conduction path between the drain and source electrodes of FET 39. At time T₈, amplifier 29 compares signal V_REF2received at its inverting input terminal to signal V_OUTreceived at its noninverting input terminal. Signal V_OUTis received at the noninverting input terminal of amplifier 29 via feedback path 51. Since the voltage of signal V_OUTis greater than the voltage of signal V_REF2, a logic high voltage is transmitted from the output terminal of amplifier 29 to the gate electrode of FET 39. Therefore, FET 39 is on and conducts a current through FET 39 for discharging the load capacitance at output pad 11, thereby decreasing the voltage of signal V_OUTtowards the voltage of signal V_REF2.

[0033] Between times T₈and T₉, the voltages of signals V_REF2and V_OUTdecrease towards supply voltage V_SS. Between times T₉and T₁₀, the voltage of signal V_OUTis substantially equal to the voltage of signal V_REF2. At time T₁₀the voltages of signals V_REF2and V_OUTare approximately equal to supply voltage V_SS.

[0034] Amplifier 29 and FET 39 regulate the voltage of signal V_OUTso that the voltages of signals V_REF2and V_OUTremain substantially equal after time T₉. That is, after time T₈, amplifier 29 continuously compares signals V_REF2and V_OUTand generates a compare signal at the output terminal of amplifier 29 for turning FET 39 on as long as amplifier 29 is active.

[0035] As shown in FIG. 3, the fall time of signal V_OUTis approximately equal to the fall time of signal V_REF2. Therefore, similar to the fall time of V_REF2discussed hereinbefore, the fall time of signal V_OUTis a function of the capacitance of capacitor 27 and the amount of discharge current through FET 22. Thus, a circuit designer can control or predetermine the fall time of signal V_OUTwith the capacitance of capacitor 27 and current source 30.

[0036] Without amplifier 28 and FET 37 regulating the voltage of signal V_OUT, the maximum voltage level of signal V_OUTwould be limited to the supply voltage V_DDminus the threshold voltage of FET 36. Similarly, without amplifier 29 and FET 39, the minimum voltage level of signal V_OUTwould be limited to the supply voltage V_SSplus the threshold voltage of FET 38. An advantage of circuit 10 is that it provides an output signal that has an output voltage swing between the supply voltages V_DDand V_SS. This is desirable in applications such as CMOS logic applications that require a rail-to-rail output voltage swing. A rail-to-rail output voltage swing means that the maximum and minimum voltage levels of the output signal are substantially equal to the power supply voltages of the integrated circuit.

[0037] Optionally, switches 31 and 32 are included in output circuit 10. Switch 32 is preferably closed when signal V_INis at a logic low voltage so that the gate electrode of FET 39 is pulled to supply voltage V_SSand FET 39 is non-conductive. Switch 31 is preferably closed when signal V_INis at a logic high voltage so that the gate electrode of FET 37 is pulled to supply voltage V_DDand FET 37 is non-conductive.

[0038] Amplifiers 28 and 29 can be current comparators for high speed applications, e.g., applications having transition times of three to five nanoseconds.

[0039] Current sources 14 and 30 can be designed to be temperature independent current sources by using a bandgap generated current reference. Further, the current sources can be matched using current mirror circuits.

[0040] By now it should be appreciated that a driver circuit and a method for controlling transition times of an output signal of the driver circuit have been provided. An advantage of the present invention is that it provides a circuit and method for generating signals having predetermined transition times that are not affected by variations in temperature, load capacitance, power supply voltages, or fabrication process. Another advantage of the present invention is that it provides a circuit for high speed applications. In addition, the present invention provides a circuit for generating output signals that have an output voltage swing between the power supply voltages of the circuit.