Method for fabricating floating gate semiconductor devices with trench isolation structures and self aligned floating gates

[0002] This application is a division of application Ser. No. 09/148,845, filed on Sep. 4, 1998, which is a continuation-in-part of application Ser. No. 08/909,713, filed Aug. 12, 1997, U.S. Pat. No. 6,054,733, which is a division of application Ser. No. 08/532,997, filed Sep. 25, 1995, U.S. Pat. No. 5,767,005, which is a continuation-in-part of application Ser. No. 08/098,449, filed Jul. 27, 1993, abandoned.

[0003] This invention relates generally to semiconductor manufacture, and more particularly to an improved method for fabricating floating gate semiconductor devices with trench isolation structures and self aligned floating gates. The method is particularly suited to the formation of non-volatile read only memories, such as flash EEPROMs.

[0004] Semiconductor memory arrays can be fabricated using floating gates (i.e., unconnected gates) that control current flow through the devices of the array. One type of floating gate device used to construct memory arrays is referred to as a flash EEPROM (electrically erasable programmable read only memory).

[0005] A flash EEPROM memory array includes multiple cells that can be erased using a single erasing operation. Typically, a flash EEPROM cell includes a floating gate, that controls current flow through a channel region of a field effect transistor (FET). The floating gate is separated from a source and drain of the FET by a thin gate oxide layer. The flash EEPROM cell also includes an elongated control gate located in a direction transverse to the source and drain of the FET. The control gates can be the word lines, and the sources and drains of the FETs can be the bit lines of the memory array.

[0006] In operation of the flash EEPROM cell, the presence of electrons in the floating gate alters the normal operation of the FET, and the flow of electrons between the source and drain of the FET. Programming of the flash EEPROM can be accomplished by hot-electron injection into the floating gate. With one type of EEPROM cell, the erasing mechanism can be electron tunneling off the floating gate to the substrate. In a memory array with this type of EEPROM cell, the individual cells are electrically isolated from one another such that the individual cells can be selectively erased.

[0007] Conventional floating gate arrays, such as flash EEPROM arrays, utilize a thermally grown field oxide (FOX) to electrically isolate adjacent cells in the array. One problem with a thermally grown field oxide is that the surface of the field oxide has a non-planar topography. With a non-planar topography, the size and spacing of features on subsequently deposited and patterned layers, such as interconnect layers, is limited by the depth of focus of conventional photolithography exposure tools. This limits the feature sizes of the array.

[0008] Another problem with field oxide isolation is that the source and drain regions of the FETs of the array can be degraded due to exposure to temperature cycles during growth of the field oxide. This can cause the source and drain regions to become less efficient in the generation of hot electrons for injection through the gate oxide layer into the floating gate.

[0009] Another consideration in the formation of floating gate devices is the alignment of the floating gates relative to other elements of the device. For example, one type of flash EEPROM cell has a floating gate which extends across the channel region of an FET. Alignment of the floating gate to the channel region requires a critical alignment step. Consequently the floating gates of flash EEPROMs have sometimes been made larger than necessary to insure alignment of the floating gates with the channel regions. In addition to alignment, a thickness of the floating gates is a critical dimension that can affect capacitive coupling between the floating gates and the control gates of flash EEPROMs. In the past the thickness of the floating gates has been difficult to control, and the floating gates have been made thicker than necessary.

[0010] The present invention is directed to a method for fabricating floating gate devices in which trench isolation, such as shallow trench isolation (STI), rather than a thermally grown field oxide, is used to electrically isolate adjacent cells. In addition, the method employs chemical mechanical planarization (CMP) to self align the floating gates relative to other elements of the devices.

[0011] In accordance with the present invention, a method for fabricating a floating gate semiconductor device, and an improved floating gate semiconductor device, are provided. In an illustrative embodiment the method is used to fabricate a flash EEPROM cell, and a flash EEPROM memory array.

[0012] The method, simply stated, comprises: providing a semiconductor substrate; forming active areas in the substrate; forming trench isolation structures on the substrate for isolating the active areas; forming a gate dielectric layer on the active areas; forming floating gates on the gate dielectric layer by chemically mechanically planarizing a blanket deposited conductive layer to an endpoint of the trench isolation structures; and then forming a control gate dielectric layer and control gates on the floating gates.

[0013] Initially, a semiconductor substrate (e.g., silicon) can be provided and active areas formed in the substrate. Each active area can include elements of a field effect transistor (e.g., source, drain, channel region). Following formation of the active areas, a sacrificial oxide layer, and a mask layer, can be formed on the substrate. The mask layer can then be patterned using a resist mask, to form a hard mask, which can be used to etch isolation trenches in the substrate.

[0014] Next, a trench fill material, such as SiO₂, can be deposited into the isolation trenches to form electrically insulating plugs. Following formation, the trench fill material can be removed to an endpoint of the mask layer preferably using chemical mechanical planarization (CMP). The mask layer can then be removed, leaving the trench fill material in each trench. With the mask layer removed, the trench fill material within each trench is higher than a surface of the substrate, such that recesses are formed which at least partially enclose each active area.

[0015] Following formation of the trench isolation structures, a gate dielectric layer can be formed on the active areas. In addition, a first conductive layer can be blanket deposited on the gate dielectric layer and partially removed and planarized preferably using CMP, to an endpoint of the trench fill material. The planarized conductive layer partially defines floating gates on the gate dielectric layer which are self aligned to the active areas. Next, a control gate dielectric layer can be deposited on the floating gates and on the trench fill material. A second conductive layer can then be deposited on the control gate dielectric layer and patterned to form control gates. During patterning of the second conductive layer, the planarized conductive layer can also be patterned to complete the floating gates.

[0016] The completed memory array includes rows and columns of flash EEPROM cells. Each flash EEPROM cell includes a FET with a source and drain, a gate dielectric layer on the source and drain, a self aligned floating gate on the gate dielectric layer, a control gate dielectric layer on the floating gate, and a control gate on the control gate dielectric layer. Trench isolation structures electrically isolate adjacent cells, and the floating gates of adjacent cells. In addition, the sources and drains of the FETs form the bit lines of the memory array, and the control gates form the word lines of the memory array.

[0017] Alternately the control gate dielectric layer can be deposited on the conductive layer prior to the chemical mechanical planarization step. The chemical mechanical planarization step can then be performed to planarize the control gate dielectric layer and the conductive layer.

[0018] FIGS. 1A-1G are schematic cross sectional views illustrating steps in a method for fabricating a flash EEPROM cell in accordance with the invention;

[0019] FIG. 2 is a schematic cross sectional view taken along section line 2—2 of FIG. 1B;

[0020] FIG. 3 is a schematic cross sectional view taken along section line 3—3 of FIG. 1D;

[0021] FIG. 4 is a schematic cross sectional view taken along section line 4—4 of FIG. 1F;

[0022] FIG. 5 is a schematic cross sectional view taken along section line 5—5 of FIG. 1G;

[0023] FIG. 5A is a cross sectional view taken along section line 5A—5A of FIG. 5;

[0024] FIG. 6 is an electrical schematic of a flash EEPROM memory array constructed in accordance with the invention;

[0025] FIG. 7 is a schematic cross sectional view of the flash EEPROM cell during a write operation; and

[0026] FIG. 8 is a schematic cross sectional view of the flash EEPROM cell during an erase operation.

[0027] Referring to FIGS. 1A-1G, steps in the method of the invention are illustrated for forming a floating gate device comprising a flash EEPROM cell.

[0028] Initially, as shown in FIG. 1A, a semiconductor substrate 10 can be provided. Preferably, the substrate 10 comprises monocrystalline silicon. The substrate 10 includes a pattern of active areas 12 comprising spaced apart source/drain regions 14. The active areas 12 and source/drain regions 14 can be formed by implanting one or more dopants into the substrate 10 using techniques that are known in the art (e.g., masking and ion implantation).

[0029] As also shown in FIG. 1A, a sacrificial oxide layer 22 can be formed on the substrate 10. One suitable material for the sacrificial oxide layer 22 comprises SiO₂deposited using a CVD process with a silicon containing precursor such as TEOS (tetraethyl orthosilicate). A representative thickness for the sacrificial oxide layer 22 can be from 50 Å to 2000 Å.

[0030] As also shown in FIG. 1A, a mask layer 16 can be formed on the sacrificial oxide layer 22. One suitable material for the mask layer 16 comprises silicon nitride (Si₃N₄) deposited by CVD. A representative thickness for the mask layer 16 can be from 300 Å to 3000 Å.

[0031] Next as shown in FIG. 1B, the mask layer 16 can be patterned and etched to form a hard mask 16A. A photo patterned layer of resist (not shown) can be used to pattern and etch the mask layer 16 to form the hard mask 16A. The hard mask 16A includes a pattern of openings 18 that are sized and shaped for etching isolation trenches 20 in the substrate 10.

[0032] Following formation of the hard mask 16A, the isolation trenches 20 can be etched into the substrate 10 to a desired depth “D”. One method for etching the isolation trenches 20 comprises an anisotropic dry etch process, such as reactive ion etching (RIE), using a suitable etchant, such as a species of Cl. In FIG. 1B, the isolation trenches 20 have sloped sidewalls as is consistent with an anisotropic etch process. Rather than dry etching the isolation trenches 20, an isotropic wet etch with a wet etchant can be employed. A suitable wet etchant for a silicon substrate comprises a mixture of HF, HNO₃, and H₂O.

[0033] The etch process can be controlled to etch the isolation trenches 20 in the substrate 10 to a desired depth D. Preferably, the isolation trenches 20 comprise shallow trenches (i.e., D is less than about 1 μm). However, the isolation trenches 20 can also comprise moderate depth trenches (i.e., D is from about 1 to 3 μm), or deep trenches (i.e., trenches greater than about 3 μm). A peripheral shape and location of the trenches 20 is controlled by a peripheral shape and location of the openings 18 in the hard mask 16A. As shown in FIG. 2, the isolation trenches 20 can be elongated, parallel, spaced rectangles. Alternately the isolation trenches can be any other required shape (e.g., squares, elongated ovals).

[0034] Following etching of the isolation trenches 20, and as shown in FIG. 1C, an insulating layer 24 can be formed within the isolation trenches 20. One suitable material for the insulating layer 24 comprises SiO₂formed using a thermal oxidation process (e.g., heating in an oxygen containing ambient). The insulating layer 24 can remove damage caused by high energy ion bombardment during the trench etching step. In addition, the insulating layer 24 can round sharp corners at the bottoms of the isolation trenches 20. A representative thickness for the insulating layer 24 can be from 50 Å to 1000 Å.

[0035] As also shown in FIG. 1C, the isolation trenches 20 can be filled with a trench fill material 26 to form insulating plugs. One suitable material for the insulating layer 24 comprises SiO₂deposited using a CVD process with a silicon containing precursor such as TEOS (tetraethyl orthosilicate). Alternately the trench fill material 26 can comprise BPSG, a nitride or other suitable electrically insulating material. In addition to filling the isolation trenches 20, the trench fill material 26 also fills the openings 18 in the hard mask 16A.

[0036] As also shown in FIG. 1C, following deposition thereof, the trench fill material 26 can be planarized to an endpoint of the hard mask 16A using chemical mechanical planarization (CMP). Following the CMP process, a surface 28 of the trench fill material 26 and hard mask 16A are substantially co-planar to one another.

[0037] One suitable CMP apparatus for performing the CMP step comprises a Model 372 manufactured by Westech. By way of example, the following parameters can be maintained during the CMP process:

[0038] Referring to FIG. 1D, following planarization of the trench fill material 26, the hard mask 16A can be stripped. A hard mask 16A comprised of Si₃N₄can be stripped using a wet etchant, such as H₃PO₄.

[0039] The sacrificial oxide 22 can also be stripped. For a sacrificial oxide 22 comprised of SiO₂, a solution of HF can be used to strip the sacrificial oxide 22. With the sacrificial oxide 22 stripped, a gate dielectric layer 38 can be formed on the substrate 10. For example, the gate dielectric layer 38 can comprise SiO₂having a thickness of about 30 Å to 800 Å and formed using a CVD or thermal growth process. Alternately, instead of SiO₂, the gate dielectric layer 38 can comprise a nitride (e.g., Si₃N₄), an oxynitride (e.g., NO) or another oxide (e.g., Ta₂O₅).

[0040] The completed trench isolation structures 30 have a height “H” measured from a surface 32 of the gate dielectric layer 38. Stated differently, the trench isolation structures 30 are higher than the surface 32. In addition, the height “H” is approximately equal to a thickness “T” (FIG. 1C) of the planarized hard mask 16A.

[0041] As also shown in FIG. 1D, adjacent trench isolation structures 30 form a recess 34. As shown in FIG. 3, the recess 34 at least partially encloses the active area 12 located between adjacent trench isolation structures 30.

[0042] Referring to FIG. 1E, a first conductive layer 36 can be blanket deposited over the gate dielectric layer 38 and over the trench isolation structures 30. In addition, the first conductive layer 36 extends into the recesses 34 defined by the parallel spaced trench isolation structures 30. The first conductive layer 36 can comprise doped polysilicon deposited to a desired thickness using CVD. Alternately, the first conductive layer 36 can comprise a metal such as titanium, tungsten, tantalum, molybdenum or alloys of these metals. Preferably, the first conductive layer 36 has a thickness “T1” that is equal to or less than a height “H” of the trench isolation structures 30.

[0043] Referring to FIG. 1F, following blanket deposition, the first conductive layer 36 can be planarized to an endpoint 40 of the trench isolation structures 30 to form a planarized first conductive layer 36A. As shown in FIG. 4, the planarized first conductive layer 36A substantially covers the recesses 34. In addition, the planarized first conductive layer 36A can be considered as self aligned to the active areas 12 which are located under the recesses 34. However, the first conductive layer 36 has been removed from the trench isolation structures 30. During a patterning step to be subsequently described, the self aligned and planarized first conductive layer 36A will be patterned to form floating gates 50 (FIG. 5).

[0044] Planarization of the first conductive layer 36 can be accomplished using a chemical mechanical planarization process, substantially as previously described. Endpoint detection can be accomplished by techniques that are known in the art, such as direct measurement, or approximations based on experimental data, and known process conditions.

[0045] Referring to FIG. 1G, a control gate dielectric layer 42 can be deposited on the planarized first conductive layer 36A. The control gate dielectric layer 42 can comprise SiO₂deposited to a desired thickness using a CVD or thermal growth process as previously described. A representative thickness for the control gate dielectric layer 42 can be from 10 Å to 1000 Å. Alternately, instead of SiO₂, the control gate dielectric layer 42 can comprise a nitride (e.g.,Si₃N₄), an oxynitride (e.g., NO) or another oxide (e.g., Ta₂O₅).

[0046] Following formation of the control gate dielectric layer 42, a mask (not shown) can be formed on the substrate 10 for removing unwanted portions of the control gate dielectric layer 42. By way of example, the mask (not shown) can comprise a nitride hard mask as previously described formed using techniques that are known in the art. Open areas of the mask (not shown) can align with peripheral devices of the array that do not require a floating gate. The mask (not shown) can be described as a non-critical mask because satisfactory alignment of the relatively large areas involved can be effected without introducing alignment errors. A suitable wet etchant such as HF can be used to remove unwanted portions of the control gate dielectric layer 42.

[0047] Alternately, the control gate dielectric layer 42 can be deposited prior to chemical mechanical planarization of the first conductive layer 36. In this case the control gate dielectric layer 42 would then be chemically mechanically planarized with the first conductive layer 36.

[0048] As also shown in FIG. 1G, a second conductive layer 44 can be deposited on the first conductive layer and on the patterned control gate dielectric layer 42. The second conductive layer 44 can comprise polysilicon deposited using a CVD process as previously described. Alternately the second conductive layer 44 can comprise a metal as previously described.

[0049] Following deposition, the second conductive layer 44 can be patterned and etched to form control gates 48 (FIG. 5) and word lines WL (FIG. 5). At the same time that the second conductive layer 44 is patterned and etched, the planarized first conductive layer 36A can also be patterned and etched to define floating gates 50 (FIG. 5A). A dry etch process using a mask (not shown) and a suitable etching species can be used to etch the control gates 48 and the floating gates 50. As shown in FIG. 5A, the active areas 12 on the substrate 10 include the control gates 48 and the floating gates 50, separated by the control gate dielectric layer 42. Conventional semiconductor processes (i.e., forming interconnect and passivation layers) can now be used to complete the device.

[0050] Referring to FIG. 6, a memory array 46 constructed using the method outlined in FIGS. 1A-1G is illustrated. The memory array 46 includes rows and columns of floating gate cells 56. In the illustrative embodiment, each floating gate cell 56 comprises a flash EEPROM. Each floating gate cell 56 comprises an FET 52 formed by an active area 12 (FIG. 1A) on the substrate 10.

[0051] Each FET 52 includes a source “S”, and a drain “D”, formed by the source/drain regions 14 (FIG. 1A) on the substrate 10. In addition, each FET 52 in the memory array 46 includes a floating gate 50 and a control gate 48. The planarized first conductive layer 36A (FIG. 1F) forms the floating gates 50. The patterned second conductive layer 44 forms the control gates 48 and the word lines (WL0, WL1, WL2 . . . ) of the memory array 46. The sources S and drains D of the FETs 52 form the bit lines (BL0, BL1 . . . ) of the memory array 46.

[0052] Referring to FIGS. 7 and 8, operational characteristics of a floating gate cell 56 are illustrated. FIG. 7 illustrates the floating gate cell 56 during a WRITE operation. During a WRITE, a high programming voltage (e.g., V_pp=12V) is placed on the control gate 48. The high programming voltage forms an inversion region 54 in the substrate 10 which in the illustrative embodiment comprise P-silicon. At the same time the drain voltage (V_D) is increased to about half the programming voltage (e.g., V_D=0.5 V_pp=6V), while the source is grounded (0 volts). With the inversion region 54 formed, the current between the drain D and source S increases. The resulting high electron flow from source S to drain D increases the kinetic energy of electrons 58. This causes the electrons 58 to gain enough energy to cross the gate dielectric layer 38 and collect on the floating gate 50.

[0053] After the WRITE is completed, the negative charge on the floating gate 50 raises the cell's threshold voltage (V_T) above the word line logic 1 voltage. When a written cell's word line is brought to a logic 1 during a READ, the cell will not turn on. Sense amps (not shown) associated with the memory array 46 amplify the cell current and output a 0 for a written cell.

[0054] FIG. 8 illustrates the floating gate cell 56 during an ERASE operation. In this mode Fowler-Nordheim tunneling removes charge from the floating gate 50 to bring it to the erased state. Using a high-voltage source erase, the source is brought to a high voltage (V_pp=12V), the control gate 48 is grounded (0 volt) and the drain D is left unconnected. The large positive voltage on the source, as compared to the floating gate 50, attracts the negatively charged electrons from the floating gate 50 though the gate dielectric layer 38 to the source. Because the drain D is not connected, the ERASE function is a much lower current per cell operation than a WRITE that uses hot electron injection.

[0055] After the ERASE is completed, the lack of charge on the floating gate 50 lowers the cells V_Tbelow the word line logic 1 voltage. When an erased cell's word line is brought to a logic 1 during a READ, the FET 56 will turn on and conduct more current than a written cell.

[0056] During a READ of a byte or word of data, the addressed row (word line) is brought to a logic 1 level (>V_Tof an erased cell). This condition turns on erased cells which allow current to flow from drain D to source S, while written cells remain in the off state with little current flow from drain D to source S. The cell current is detected by the sense amps and amplified to the appropriate logic level to the outputs.

[0057] Thus the invention provides an improved method for fabricating floating gage semiconductor devices such as flash EEPROMs and flash EEPROM memory arrays. The invention also provides improved floating gate semiconductor devices, and improved memory arrays.

[0058] Although the invention has been described with reference to certain preferred embodiments, as will be apparent to those skilled in the art, certain changes and modifications can be made without departing from the scope of the invention as defined by the following claims.