High speed data interface using TDM serial bus

[0002] 1. Field of the Invention

[0003] This invention relates to an interface for a Digital Subscriber Line. More particularly, it relates to an audio codec capable of interfacing to a multi-megabit per second high speed broad band modem or Digital Subscriber Line by utilizing multiple time slots of a high speed time domain multiplexed data bus.

[0004] 2. Background of Related Art

[0005] Efficient and inexpensive digitization of telephone grade audio has been accomplished for many years by an integrated device known as a “codec.” A codec (short for COder-DECoder) is an integrated circuit or other electronic device which combines the circuits needed to convert analog signals to and from digital signals, e.g., Pulse Code Modulation (PCM) digital signals.

[0006] Early codecs converted analog signals at an 8 KHz rate into 8-bit PCM for use in telephony, and were not capable of handling modem inputs. More recently, the efficiency and low cost advantages of codecs have been expanded to convert analog signals at a 48 KHz sampling rate into 16-bit stereo (and even up to 20-bit stereo) for higher quality use beyond that required for telephony. With higher quality and broader bandwidth capability, today's codecs find practical application with consumer equipment such as voice band modems.

[0007] With the development of codecs for these more sophisticated purposes came the need to improve the analog signal-to-noise (S/N) ratio to at least 75 to 90 dB. One major step toward achieving this high S/N ratio was accomplished more recently by separating the conventional codec into two individual sub-systems: a controller sub-system or integrated circuit (IC) handling primarily the digital interface to a host processor, and an analog sub-system or IC handling primarily the interface to, mixing and conversion of analog signals. This split digital/analog architecture has been documented most recently as the “Audio Codec '97 Component Specification”, Revision 1.03, Sep. 15, 1996 (“the AC '97 Specification”). The AC '97 Specification in its entirety is expressly incorporated herein by reference.

[0008] The modem capability of today's audio codecs such as those defined by the AC '97 Specification is limited in bandwidth to support only modems in the voice band having a sampling rate not exceeding 48 KHz (48 Kilosamples per second Ks/s). However, there is a growing consumer need for audio codecs to handle high capacity modem data. The current audio codecs, particularly the two sub-system audio codec defined by the AC '97 Specification, provide only an interface to a lower speed voice band modem using a single 16-, 18- or 20-bit time slot in a TDM serial data stream, at a maximum sampling rate of 48 Ks/s. The AC '97 Specification does not provide the capability to handle multi-megabit per second modem data sources such as from a high speed wide band modem.

[0009] FIG. 5 shows a conventional split-architecture audio codec interfacing to a low speed voice band modem 510 such as that defined by the AC '97 Specification. An AC controller sub-system 500 interfaces to an AC analog sub-system 502 via a five-wire time division multiplexed (TDM) bus referred to as the AC link 504. The five-wire TDM bus of the AC link 504 comprises a sync signal 512, a reset signal 520, a serial TDM data stream SDATA_OUT 516 from the AC controller sub-system 500 to the AC analog sub-system 502, a bit clock signal BIT_CLK 514, and a serial TDM data stream SDATA_IN 518 from the AC analog sub-system 502 to the AC controller 500. The bit clock signal BIT_CLK 514 is derived by a clock 506 utilizing an external crystal 508. The frequency of the external crystal 508 is divided in half by the clock 506 to provide a bit clock signal BIT_CLK 514 which is half of the frequency of the external crystal 508.

[0010] The AC analog sub-system 502 includes a single bi-directional modem interface capable of handling a low speed voice band modem 510 at a 16-, 18- or 20-bit per sample, 48 Ks/s maximum rate. This translates to a maximum 0.96 Mb/s conversion data rate of analog-to-digital converter (ADC) 522 and digital-to-analog converter (DAC) 524. There is no provision in the conventional split-architecture audio codec for handling a high speed broad band modem or any device having a sampling rate higher than 48 K/s or a data rate exceeding that of a voice band modem.

[0011] The circuitry in the conventional AC analog sub-system 502 which interfaces to the low-speed voice band modem includes ADC 522 and DAC 524. ADC 522 samples the analog modem signal input to the AC analog sub-system 502 and provides 16-, 18-, or 20-bit data at 48 K/s to the AC link 504 for insertion into time slot 5 of the serial TDM data stream SDATA_IN 518 input to the AC controller sub-system 500. Conversely, DAC 524 receives 16-, 18-, or 20-bit data from the serial TDM data stream SDATA_OUT 516 from the AC controller sub-system 500 of the AC link 504 and converts the same into an analog signal output to the low-speed voice band modem 510. Conventional demodulation and modulation techniques such as quadrature amplitude modulation (QAM) or Carrierless Amplitude and Phase (CAP) may be performed by a digital signal processor (DSP) and/or other processor in conjunction with the ADC 522 and DAC 524.

[0012] FIG. 6 depicts a conventional sync signal 512, serial TDM data stream SDATA_OUT 516, and serial TDM data stream SDATA_IN 518, in a twelve slot TDM bi-directional data stream between the analog and controller sub-systems 502,500 of a split-architecture audio codec such as in accordance with the AC '97 Specification. The twelve time slots 1 to 12 of the serial TDM data streams SDATA_OUT 516 and SDATA_IN 518 are framed by a sync signal 512. The sync signal 512 is derived from a TAG Phase 600 during time slot 0. All time slots are 20 bits wide.

[0013] Time slots 1 and 2 of the serial TDM data stream SDATA_OUT 516 from the AC controller sub-system 500 to the AC analog sub-system 502 comprise command addresses 601 and command data 602. Status addresses 621 and status data 622 are passed in time slots 1 and 2 of the serial TDM data stream SDATA_IN 518 from the AC analog sub-system 502 to the AC controller sub-system 500. Time slots 3 and 4 of the serial TDM data stream SDATA_OUT 516 and serial TDM data stream SDATA_IN 518 comprise the stereo pulse code modulated (PCM) audio data between the AC analog sub-system 502 and the AC controller sub-system 500.

[0014] Time slot 5 of the serial TDM data stream SDATA_IN and SDATA_OUT 518, 516 contains the data from and to the low speed voice band modem 510 (FIG. 5). Time slot 6 of the serial TDM data stream SDATA_IN 518 contains microphone PCM data. The remaining time slots 7 through 12 of both the serial TDM data stream SDATA_IN and SDATA_OUT 518, 516 and time slot 6 of the serial TDM data stream SDATA_OUT 516 are unused in the conventional split-architecture audio codec.

[0015] FIG. 7 depicts in more detail the bit clock signal BIT_CLK 514 and serial TDM data stream SDATA_OUT 516 with reference to the sync signal 512. The conventional bit clock signal BIT_CLK 514 is a fixed 12.288 MHz clock signal derived in the clock 506 from the external 24.576 MHz crystal oscillator 508 (FIG. 5).

[0016] Thus, conventional split-architecture audio codecs provide limited capacity to handle high data rate modems.

[0017] The present invention provides an audio codec comprising a controller sub-system and an analog sub-system. The time division multiplexed serial data bus between the two sub-systems, known as the AC link in prior art systems, is expanded by the present invention to utilize more than one time slot to carry data to and from an interface to an analog source, e.g., a broad band modem. The digital-to-analog converter and analog-to-digital converter in the analog sub-system convert between the analog signal of the analog source and a plurality of time slots used in the TDM serial data bus.

[0018] An interleaver in the analog sub-system interleaves and passes data between the different word widths and different sampling speeds of (1) the plurality of utilized time slots of the TDM serial data bus; and (2) the converted data from the analog source.

[0019] In another embodiment, the clock in the analog sub-system of a split-architecture audio codec comprises a programmable divider or other multiplier to effectively multiply the oscillator frequency of an external crystal by any one of a plurality of predetermined values, and output the same as a bit clock signal.

[0020] Features and advantages of the present invention will become apparent to those skilled in the art from the following description with reference to the drawings, in which:

[0021] FIG. 1 shows a split-architecture audio codec including an interleaver which interfaces to a high speed broad band modem according to the present invention.

[0022] FIG. 2 depicts a bi-directional audio frame between analog and digital sub-systems of an audio codec according to an embodiment of the present invention.

[0023] FIG. 3A depicts the result of the interleaving of the data from a high speed digital subscriber line and a fixed rate data stream formed by a plurality of time slots of a TDM bus.

[0024] FIG. 3B is a detailed depiction of the interleaving between seven 20-bit time slots and 12.73 11-bit samples in a 48 KHz frame of data.

[0025] FIG. 4 shows a programmable clock in the AC analog sub-system of a split-architecture audio codec according to the present invention.

[0026] FIG. 5 shows a conventional split-architecture audio codec such as that defined by the AC '97 Specification interfacing to a low speed voice band modem.

[0027] FIG. 6 depicts the time slots of a conventional split-architecture audio codec bidirectional TDM audio frame such as that of the AC link of the AC '97 Specification.

[0028] FIG. 7 depicts the bits of an audio output frame of a conventional split-architecture audio codec such as that of the AC link of the AC '97 Specification.

[0029] FIG. 1 shows a split-architecture audio codec according to a first embodiment of the present invention.

[0030] An AC controller sub-system 100 communicates with an AC analog sub-system 102 through an AC link 104. A five-wire TDM serial data bus separates the AC controller sub-system 100 from the AC link 104 of the AC analog sub-system 102. Although the present invention is not limited to a TDM serial data bus having five wires only, it is the presently preferred embodiment for maximum conformity with the current AC '97 standard. It is recognized and appreciated that the standard may and will change over time, and may even be disbanded. For instance, an extension to the AC '97 standard is anticipated and expected to be released in the future. Thus, although the disclosed embodiment is described with respect to the AC '97 standard, it is not so limited.

[0031] The split-architecture audio codec of the present invention provides an interface to a high speed, broad band modem 132 capable of data rates in excess of 1 Mb/s. Examples of such a broad band modem 132 include High data rate Digital Subscriber Line (HDSL), Symmetric DSL (SDSL), and Asymmetric DSL (ADSL), which are collectively and generically referred to as “xDSL”. HDSL and SDSL typically operate at T1 rates (1.544 Mb/s) or E1 rates (2.048 Mb/s). ADSL typically operates at 1.5 to 9 Mb/s in a downstream direction. Of course, the present invention is applicable with any type of broad band modem, not just those in the xDSL family of research.

[0032] The interface of the AC analog sub-system 102 to the high speed broad band modem 132 includes an ADC 122 and a DAC 124 both suitably fast and accurate to convert the analog signal from the high speed broad band modem 132 to and from a digital data stream.

[0033] The current AC '97 standard limits each 48 KHz frame to containing a single 20-bit wide sample within the boundaries of a single time slot. The present embodiment loosens the restriction of the barriers of a single 20-bit wide time slot by allowing efficient placement of a plurality of shorter or longer samples within each 48 KHz frame. For instance, because the present embodiment provides up to 7×20 bits=140 bits per 48 KHz sample, more than twelve 11-bit samples can be handled in each 48 KHz frame. Thus, the present invention provides a greater flexibility in the prevention of aliasing.

[0034] Based on the present invention, the data rate of the serial TDM data stream input and output from an interleaver 130 to the AC link 104 can be as fast as 6.72 Mb/s using seven time slots of the AC link 104 as in the present embodiment of the invention. The data rate is limited only by the number of TDM slots utilized in the five-wire TDM serial data bus 112-120 of the AC link 104. The seven time slots of the TDM serial data bus 112-120 used by the present embodiment are not used by the conventional AC link 504 (FIG. 5) and thus the present embodiment remains in conformance with the AC '97 Specification. Each of these seven time slots is structured as a 20-bit TDM time slot and has a frame or sampling frequency of 48 KHz.

[0035] Additional time slots of the AC link 104 may be utilized in some circumstances by interleaver 130 to increase the data transfer rate between the AC controller sub-system 100 and the AC analog sub-system 102, but at the sacrifice of some compatibility with the AC '97 specification and subsequent versions of the same. Additionally, the AC link 104 may be expanded to include additional serial TDM data streams to provide additional capacity. Table I shows the conversion data rates of a split-architecture audio codec based on the number of time slots utilized and the following formula:

[0036] #timeslotsused×(20bits/timeslot)×48KHz=ConversionDataRate

[0037] FIG. 2 depicts in more detail the seven utilized time slots in the serial TDM data streams SDATA_OUT 116 and SDATA_IN 118 of the AC link 104 (FIG. 1). The particular time slots used in the particular split-architecture audio codec may be different from those of the present embodiment. Those of ordinary skill in the art will easily recognize that the present invention is fully applicable to any split-architecture audio codec which utilizes more than one 16-, 18-, or 20-bit time slot to pass high speed broad band modem data between sub-systems.

[0038] Because the data rate of high speed broad band modems in general is not in conformance with the exact data rates of the TDM serial data bus 112-120 of the conventional AC link 504 (FIG. 5), and because the sample width of ADC 122 and DAC 124 is not necessarily the same as the width of an individual time slot, an interleaving or rate adaption function must be performed between ADC and DAC 122, 124 and the AC link 104 of the AC analog sub-system 102. This interleaving function is performed in the disclosed embodiment by an interleaver 130.

[0039] In the direction from the high speed broad band modem 132 to the AC link 104, interleaver 130 receives data samples from the ADC 122 on a continuous basis and at a data rate and sample size suitable for the high speed broad band modem 132. For instance, in the disclosed embodiment of a 6.6. Mb/s high speed broad band modem 132 the received data samples are 11-bits each. When utilizing seven time slots of the serial TDM data bus of the AC link 104, interleaver 130 rate adapts between the continuous, 6.6 Mb/s, 11-bit samples of the data stream from the ADC 122, and the seven intermittent, 6.72 Mb/s, 20-bit time slots of the data stream of the AC link 104. In the disclosed embodiment, the 11-bit converted data samples from ADC 122 are re-packaged by the interleaver 130 into 20-bit samples for placement in seven time slots of the serial TDM data stream of the AC link 104. Thus, all 11 bits of an 11-bit first sample and the first 9 (e.g., the highest significant) bits of a second 11-bit sample would be placed in a first one of seven 20-bit time slots (e.g., time slot 6) of the AC link 104. Similarly, the last two (e.g., the least two significant) bits of the second 11-bit sample, all 11-bits of a third 11-bit data sample, and the first 7 bits of a fourth 11-bit data sample would be placed for passage in the second of the seven utilized time slots, e.g., time slot 7, of the serial TDM data bus of the AC. link 104, and so on.

[0040] The interleaver 130 is bi-directional. Thus, it also receives 20-bit data samples from each of the seven time slots in the serial TDM data bus of the AC link 104, and parses the same into 11-bit samples for conversion by the DAC 124.

[0041] Accordingly, at the example high speed broad band modem 132 data rate of 6.6 Mb/s, and utilizing seven time slots of the AC link 104, the interleaver 130 adapts data during each 48 KHz frame of the AC link 104 between data in seven utilized time slots of the AC link 104 and approximately 12.73 converted 11-bit samples of the ADC 122 and DAC 124 as follows. $\frac{7\mathrm{timeslots}\times 20\mathrm{bits}/\mathrm{timeslot}}{11\mathrm{bits}/\mathrm{sample}}=12.73\mathrm{samples}/\mathrm{frame}$  (12.73samples/frame)×(48,000frames/sec)=610,909samples/sec

[0042] The interleaver 130 outputs data each frame so that no more than one frame delay, i.e., approximately 20.8 microseconds, is incurred by the interleaving function. Buffering of significantly more data is possible but is less desirable in the interleaver 130 because it would create substantial latency in the serial TDM data stream.

[0043] The interleaver 130 may be implemented by a first-in, first-out type (FIFO) memory and FIFO controller, or other data storage circuit. By interleaving the data stream from the high speed broad band modem 132 into a plurality of time slots of a TDM data stream, the interleaver 130 adjusts between the fixed data rate of the five-wire TDM serial data bus of the AC link 104 and the actual conversion data rate of the ADC 122 and DAC 124.

[0044] FIG. 3A depicts the resultant interleaved output of interleaver 130. Waveform (a) in FIG. 3A depicts a continuous 6.6 Mb/s digital data stream from the high speed broad band modem 132 (shown in FIG. 1). Waveform (b) in FIG. 3A depicts the TAG phase representing time slot 0 of the AC link 104 when the SYNC signal 112 is high. Waveform (c) in FIG. 3A depicts the rate-adapted, interleaved output from interleaver 130 placed in 6.72 Mb/s data stream formed by seven time slots of the serial TDM data streams SDATA_OUT and SDATA_IN signals 116, 118.

[0045] FIG. 3B is a more detailed depiction of the interleaving between the seven time slots of the serial TDM data streams SDATA_OUT and SDATA_IN of the AC link 104, and the continuous data stream of the high speed broad band modem 132.

[0046] The clock 106 in the first embodiment of the present invention is the same as that in the prior art, i.e., as is described in the AC '97 Specification. FIG. 4 shows a second embodiment of the present invention wherein a programmable clock 106areplaces clock 106 shown in FIG. 1 and is otherwise as shown and described with reference to FIG. 1. The conventional clock 106 of a split-architecture audio codec multiplies the frequency of an external crystal oscillator 108 to obtain a bit clock signal BIT_CLK 114 (FIG. 5) of the desired frequency, preferably an integer multiple of the 12.288 MHz defined in the AC '97 Specification. The present invention provides programmability in the clock 106 with respect to the division of the frequency of the external crystal oscillator 108. In the present embodiment, the programmable clock 106ais set by a control register in the AC analog sub-system 102 to multiply the frequency of the external crystal oscillator 108. The frequency of the external oscillator 108 is either divided by two (as in the prior art) or by one (i.e., no division). A division by one effectively doubles the rate of the bit clock signal BIT_CLK 114. Moreover, a voltage controlled oscillator (VCO) with a phase-locked loop (PLL) can be implemented to multiply the frequency of the external crystal oscillator by an integer value of more than one.

[0047] The split-architecture audio codec including a programmable clock 106aaccording to the present embodiment allows for the implementation of three general modes of operation: (1) conventional AC '97 (or compatible) operation; (2) high speed broad band modem interface mode; and (3) multiple high speed broad band modem interface mode.

[0048] (1) conventional AC '97 (or compatible) operation

[0049] With programmable clock 106aset or programmed to multiply the frequency of the external crystal oscillator 108 (FIG. 1) by one-half to form the bit clock signal BIT_CLK 114, the split-architecture audio codec operates as specified in the AC '97 specification without interfacing to a high speed broad band modem 132.

[0050] (2) high speed broad band modem interface mode

[0051] With programmable clock 106aset to multiply the frequency of the external crystal 108 by one-half to form the bit clock signal BIT_CLK 114, and with the AC analog sub-system 102 interfaced to a high speed broad band modem 132, the split-architecture audio codec operates as described with respect to the first embodiment with time slots which sample at 48 K/s.

[0052] (3) multiple high speed broad band modem interface mode

[0053] With programmable clock 106aset to multiply the frequency of the external crystal 108 by one or more than one, and with the AC analog sub-system 102 interfaced to a high speed broad band modem 132, the split-architecture audio codec samples at 96 Ks/s, 192 Ks/s, etc., thus doubling, quadrupling, etc the data rates over the five-wire TDM data bus (AC link 104)(FIG. 1).

[0054] This mode of operation is particularly useful when the required data rate of the high speed broad band modem 132 exceeds that provided by the available TDM time slots of the AC link 104. For instance, seven time slots of the TDM serial streams in the AC link 104 can provide up to 1.2 Ms/s sampling with the clock doubled (clock 106aprogrammed to divide by one), as shown in the following Table II. Data rates through the high speed broad band modem 132 are thus doubled over the first embodiment to provide up to 13.44 Mb/s using seven time slots of the AC link 104.

[0055] While the invention has been described with reference to the exemplary preferred embodiments thereof, those skilled in the art will be able to make various modifications to the described embodiments of the invention without departing from the true spirit and scope of the invention.