2.5V, 30-100 MHz 7th order equiripple delay continuous-time filter and variable gain amplifier

[0002] This application claims priority under 35 U.S.C. §119(e)(1) of provisional application No. 60/069,475, filed Dec. 15, 1997.

[0003] This invention relates to an integrated circuit and more particularly to an integrated circuit with a continuous-time filter and variable gain amplifier.

[0004] Present computer systems typically use hard-disk drive systems for mass storage. An exemplary hard disk drive read channel of the prior art is shown at FIG. 1. A magnetic surface of the hard disk 101 induces electrical signals in the read head 103. The data rate of these signals varies with each zone of the hard disk drive. These read signals are amplified by preamplifier circuit 105 and applied to variable gain amplifier 109 and programmable analog filter 111 of the read channel analog front end 107. The programmable filter performs anti-aliasing and channel equalization for analog-to-digital (ADC) circuit 113. This ADC circuit subsequently produces digital signals suitable for digital processor 115.

[0005] Conventional design techniques may not be adequate for state-of-the-art read channel applications for several reasons. First, a native tolerance of resistor-capacitor (RC) products is typically ±40%. Such variation is incompatible with a required filter group delay accuracy of ±5% at a high corner frequency of 100 MHz. Second, variable gain amplifier (VGA) gain and bandwidth requirements for conventional techniques may require a relatively large unity-gain bandwidth of 5.85 GHz. Finally, conventional attempts to avoid gain-bandwidth limitations may result in an increase in power dissipation.

[0006] These problems are resolved by a circuit comprising a first transconductor circuit with a first input terminal coupled to receive a voltage signal, a second input terminal coupled to receive a control signal and an output terminal. The first transconductor circuit has a gain responsive to the control signal. A first integrator circuit has an input terminal coupled to the first transconductor circuit output terminal and an output terminal. A second transconductor circuit has an input terminal coupled to the first integrator circuit output terminal and an output terminal. A second integrator circuit has an input terminal coupled to the second transconductor circuit output terminal and has an output terminal.

[0007] The present invention avoids conventional gain-bandwidth limitations by incorporating a variable gain amplifier within a cascade filter.

[0008] A more complete understanding of the invention may be gained by reading the subsequent detailed description with reference to the drawings wherein:

[0009] FIG. 1 is a block diagram of a typical hard-disk drive read channel of the prior art;

[0010] FIG. 2 is a block diagram of a filter circuit of the present invention;

[0011] FIG. 3A is a block diagram of a first section of the filter circuit of FIG. 2;

[0012] FIG. 3B is a block diagram of the second and following sections of the filter circuit of FIG. 2;

[0013] FIG. 4A is a specification for the VGA and 7^thorder equiripple delay low-pass filter of the present invention

[0014] FIG. 4B is a specification for each section of the 7^thorder equiripple delay low-pass filter of the present inventions,

[0015] FIG. 5A is a schematic diagram of an integrator circuit of the prior art;

[0016] FIG. 5B is a gain/phase diagram of the integrator circuit of FIG. 5A;

[0017] FIG. 6A is a schematic diagram of a biquadratic circuit of the present invention;

[0018] FIG. 6B is a gain/phase diagram of the signal V_Aof FIG. 6A;

[0019] FIG. 6C is a gain/phase diagram of the signal V_OUTof FIG. 6A;

[0020] FIG. 7 is a simulation of the biquadratic circuit of FIG. 6A;

[0021] FIG. 8A is a schematic diagram of integrator circuit 319 of the biquadratic circuit of FIG. 3B;

[0022] FIG. 8B is a schematic diagram of transconductor circuit 811 of the integrator circuit 319 of FIG. 8A;

[0023] FIG. 9 is a detailed schematic diagram of biquadratic circuit 203 of the filter circuit of FIG. 2;

[0024] FIG. 10 is a schematic diagram of transconductor circuit 903 of the biquadratic circuit of FIG. 9;

[0025] FIG. 11 is a detailed schematic diagram of transconductor circuit 909 of the biquadratic circuit of FIG. 9;

[0026] FIG. 12 is a detailed schematic diagram of the operational amplifier circuit of integrator circuit 905 of the biquadratic circuit of FIG. 9;

[0027] FIG.13 simulation of the gain and group delay of the filter circuit of FIG. 2; and

[0028] FIG. 14 is a schematic diagram of an embodiment of a boost circuit of the biquadratic circuit 207 of FIG. 2.

[0029] A block diagram of an integrated variable gain amplifier and 7^thorder filter of the present invention as shown in FIG. 2 will be described in detail. First order section 201 as shown in FIG. 3A receives an input signal on lead 301 that is summed with a feedback signal from output lead 307 and applied to integrator circuit 305. The output signal on lead 307 is applied to biquadratic circuits 203, 205 and 207 connected in cascade. Each biquadratic circuit (FIG. 3B) includes series connected integrator circuits 315 and 319 with respective feedback signals applied to summation terminal 313. The final biquadratic circuit 207 produces a boosted output signal of the present invention on lead 211 as will be described in detail. A specification for the VGA and 7^thorder equiripple delay low-pass filter of the present invention is given at FIG. 4A. In particular, the filter specification requires a −3 dB bandwidth from 30 MHz to 100 MHz and a boost range from 0 dB to 12 dB. A respective resonant frequency and Q for each section of the 7^thorder equiripple delay low-pass filter of the present invention is given at FIG. 4B.

[0030] Referring now to FIG. 5A, there is a schematic diagram of an integrator circuit of the prior art with a corresponding gain/phase diagram at FIG. 5B. The circuit includes transconductor circuit 501 connected in series with operational amplifier 503. Feedback capacitors 504 produce a right half-plane zero in the closed loop transfer function that may lead to an abrupt phase change 505 at a unity gain frequency f_T. This abrupt phase change will lead to significant phase errors in view of typical ±40% variation of RC time constants and operating conditions.

[0031] Turning now to FIG. 6A, there is a schematic diagram of a biquadratic circuit of the present invention. The biquadratic circuit includes transconductor circuit 601 connected in series with operational amplifier 603. The feedback path through capacitors 607 is made unidirectional by coupling input terminals of source follower circuits 605 to the operational amplifier output terminals and coupling the source follower output terminals to the capacitors. This arrangement usually over compensates the right half-plane zero by moving it into the left half-plane and produces a large phase error lead 620 at unity gain frequency f_Tas shown in FIG. 6B. A trimming circuit including input resistors 609, feedback resistors 611, feedback transistors 613 and operational amplifier 615 is connected to the output terminals of the integrator circuit. This trimming circuit has a typical gain of unity. Application of control signal V_freqmodulates the conductivity of transistors 613, thereby providing a variable shunt for the feedback resistors and producing an automatic compensation for process and operating conditions. This control signal V_freqis preferably developed by a servo-loop that constrains the filter conductance with an external trimming resistor. The resulting gain and phase diagram of FIG. 6C shows that the integrator of FIG. 6A has a nearly ideal phase of −90° at the unity gain frequency f_T(630). A simulation in FIG. 7 of the biquadratic circuit of FIG. 6A shows the effectiveness of the biquadratic circuit in producing a small phase error at the unity gain frequency f_Tof 100 MHz for typical process variations. This is highly advantageous in eliminating significant phase errors of the prior art.

[0032] Referring now to FIG. 8A-FIG. 8B, another embodiment of the biquadratic circuit of the filter circuit of FIG. 2 will be described in detail. The filter specification of FIG. 4A of the present invention requires a −3 dB bandwidth from 30 MHz to 100 MHz as previously disclosed. This requires a programmability range of up to 333%. Taken together with the −40% tunability requirement to compensate for process, temperature and RC tolerance, this would require a variation in unity gain frequency f_Tof the integrators of about 8:1. Integrating capacitors at such high frequencies, however, are quite small. Moreover, inherent parasitic circuit capacitance becomes significant compared to the small integrating capacitance. A capacitor array based on such physical limitations is impractical, therefore, due to the size limitation of the capacitors as well as their relative size to parasitic capacitance of the circuit.

[0033] A solution to this problem is implemented in integrator 319 of the biquadratic circuit (FIG. 3B) as shown in detail in FIG. 8A. The integrator includes transconductor circuit 811 connected in cascade with an integrator including operational amplifier 815 and feedback capacitors 813. The output signal of the integrator is applied to the tunable-gain amplifier 824. A schematic diagram of transconductor circuit 811 of the integrator circuit 807 of FIG. 8B is shown at FIG. 8C. The transconductor circuit 811 is implemented as three separate transconductor circuits 825-827 connected in parallel. The transconductor circuits are preferably identical and require only one-third the area and power of a comparable single transconductor circuit. Each of these transconductor circuits 825-827 is selectively enabled by a respective control signal on leads 828-830. This arrangement provides a coarse 3:1 programmability over the frequency range of interest. This highly advantageous implementation overcomes the practical limitation of capacitor array programmability and conserves power.

[0034] Turning now to FIG. 9, there is a detailed schematic diagram of biquadratic circuits 203 and 205 of the filter circuit of FIG. 2. The biquadratic circuit includes two integrator circuits in cascade. Each integrator circuit includes an input transconductor circuit (903, 909), an operational amplifier (905, 911) with capacitive feedback and a tunable-gain amplifier (907, 913). An output signal from first and second integrator circuits is fed back through transconductor circuits 921 and 917, respectively, to input terminals of the integrating operational amplifier circuit 905. A transfer function of the biquadratic circuit with parameters and component values of FIG. 9 is: $H_{\mathrm{lp}}\left(s\right)=\frac{V_{\mathrm{lp}}\left(s\right)}{V_{\mathrm{in}}\left(s\right)}=\frac{K}{{\left(\frac{s}{{\omega }_0}\right)}^2+\left(\frac{s}{{\omega }_{0}Q}\right)+1}\mathrm{where}{\omega }_0=\frac{a{G}_m}{C}$

[0035] Scaling the gain of input transconductor circuit 903 by a factor K, therefore, introduces the same scaling factor K in the overall transfer function without affecting the shape or group delay of the biquadratic circuit. This is highly advantageous for several reasons. First, the gain of the biquadratic circuit is not determined by conventional voltage-to-current-to-voltage conversion. Thus, it is not constrained by conventional cascade gain-bandwidth limitations. Second, this configuration consumes no additional power. Finally, the overall gain of the filter circuit may be distributed among the biquadratic circuits.

[0036] The schematic diagram of FIG. 10 illustrates the operational principle of transconductor circuit 903 of the biquadratic circuit of FIG. 9. The transconductor circuit includes a first series circuit including a current source 1001, an input transistor 1007 and another current source 1019. A second series circuit includes current sources 1003 and 1021 and input transistor 1009. Shunt transistors 1011 and 1013 are coupled between the first and second series circuits and have control gate coupled to input transistors 1007 and 1009, respectively. A control transistor 1015 is connected in parallel with the shunt transistors. In operation, a difference voltage V_inis applied to input leads 901. This difference voltage modulates the conductivity of respective input and shunt transistors, thereby steering a corresponding current through output terminals 1005. Application of control signal V_VGAmodulates the conductivity of control transistor 1015. This change in conductivity alters the current flow through output terminals 1005, thereby producing a variable gain.

[0037] A detailed schematic diagram of transconductor circuit 909 of the biquadratic circuit of FIG. 9 is illustrated in FIG. 11. Transconductor circuit 909 operates in a manner similar to that previously described for transconductor circuit 903 of FIG. 10 with the exception of the variable gain feature. In operation, transconductor circuit 909 receives a difference voltage signal at input transistors 1123 and 1127 and produces a corresponding output current signal at terminals 1131. Output terminals 1119 and 1121 drive a common-mode feedback circuit including feedback transistors 1109, 1113 and 1115. A further high-frequency feedback path is provided through capacitor 1107 to obtain an adequate closed-loop bandwidth for the common-mode feedback loop. Resistor 1105 separates the low-frequency feedback path from the high-frequency feedback path to provide adequate phase margins. This feedback circuit is highly advantageous for providing a closed loop bandwidth of over 200 MHz with more than a 60° phase margin for worst case process variation.

[0038] Turning now to FIG. 12, there is a detailed schematic diagram of the operational amplifier circuit of integrator circuit 905 of the biquadratic circuit of FIG. 9. The operational amplifier circuit receives a differential voltage across input terminals 1229 and 1235 and produces a corresponding output voltage at terminals 1223. A low-frequency common-mode feedback circuit including transistors 1209 and 1211 is driven by a signal from a common terminal of a voltage divider formed by equal-valued resistors 1225 and 1227. A high-frequency common-mode feedback path is provided through capacitor 1215. The low-frequency and high-frequency feedback paths are separated by resistor 1205 to provide a closed loop bandwidth similar to that of the transconductor circuit of FIG. 11. A simulation of the gain and group delay of the filter circuit of FIG. 2 with process variation is shown in FIG. 13. The circuit has a −3 dB bandwidth set at 100 MHz. The group delay has a maximum variation of ±4% from 0-150 MHz.

[0039] Referring now to FIG. 14, there is a schematic diagram of a novel embodiment of a boost circuit of the biquadratic circuit 207 of FIG. 2 as specified in FIG. 4A. This boost function is implemented for pulse slimming at high data rates by adding zeros to the low-pass filter transfer function. The overall transfer function to be implemented for the low-pass filter with boost is: $H_{\mathrm{lp}-\mathrm{Boost}}\left(s\right)=\frac{V_{\mathrm{Boost}}\left(s\right)}{V_{\mathrm{in}}\left(s\right)}=\frac{{a\left(\frac{s}{{\omega }_0}\right)}^2+b\left(\frac{s}{{\omega }_{0}Q}\right)+1}{{\left(\frac{s}{{\omega }_0}\right)}^2+\left(\frac{s}{{\omega }_{0}Q}\right)+1}$

[0040] When expanded, the transfer function has the form: $H_{\mathrm{lp}-\mathrm{Boost}}\left(s\right)=a+\left(b-a\right)\frac{\left(\frac{s}{{\omega }_{0}Q}\right)}{{\left(\frac{s}{{\omega }_0}\right)}^2+\left(\frac{s}{{\omega }_{0}Q}\right)+1}+\left(1-a\right)\frac{1}{{\left(\frac{s}{{\omega }_0}\right)}^2+\left(\frac{s}{{\omega }_{0}Q}\right)+1}$

[0041] Programmable constants a and b are chosen so that a maximum boost increases the gain at the original −3 dB frequency by 12 dB. The first term of the expanded transfer function represents the input signal at lead 1401 scaled by a. The second term of the expanded transfer function represents the bandpass filter output signal at lead 1407 scaled by (b−a). The final term of the expanded transfer function represents the lowpass filter output signal at lead 1415 scaled by (1−a). These scale factors are implemented by the programmable resistive network including resistors 1419, 1421 and 1423 to produce the boosted output signal at lead 1425. This implementation of the boost function is highly advantageous, since it requires no additional signals to perform a weighted sum of existing signals.

[0042] Although the invention has been described in detail with reference to its preferred embodiment, it is to be understood that this description is by way of example only and is not to be construed in a limiting sense. It is to be further understood that numerous changes in the details of the embodiments of the invention will be apparent to persons of ordinary skill in the art having reference to this description. It is contemplated that such changes and additional embodiments are within the spirit and true scope of the invention as claimed below.