US 6,266,760 B1Grant
Intermediate-grain reconfigurable processing device
Issue Date:2001-07-24
•30 Claims
•20 Drawing Sheets
Abstract
A programmable integrated circuit utilizes a large number of intermediate-grain processing elements which are multibit processing units arranged in a configurable mesh. The coarse-grain resources, such as memory and processing, are deployable in a way that takes advantage of the opportunities for optimization present in given problems. To accomplish this, the interconnect supports three different modes of operation: a static value in which a value set by the configuration data is provided to a functional unit, static source in which another functional unit serves as the value source, and a dynamic source mode in which the source is determined by the value from another functional unit.
Metadata
Assignee
- Massachusetts Institute of Technology
Inventors
- André DeHon
- Ethan Mirsky
- Thomas F. Knight, Jr.
Application Information
Application Number:US 09/292,497
Filing Date:1999-04-15
Priority Date:1996-04-11
Art Unit:7
Classifications
IPC:
G06F 1516
Field of Search:
712 1712 11712 15
Patent Drawings (20 sheets)
Description
Related Application
[0002] This application is a Continuation of U.S. application Ser. No. 08/632,371, filed Apr. 11, 1996, now U.S. Pat. No. 5,956,518, the entire teachings of which are incorporated herein by reference.
Background of the Invention
[0004] Continuing advances in semiconductor technology have greatly increased the amount of processing that can be performed by single-chip, general-purpose computing devices. The relatively slow increase in inter-chip communication bandwidth requires that modern high performance devices use as much of the potential on-chip processing power as possible. This results in large, dense integrated circuit devices and a large design space of processing architectures.
[0005] One way of viewing this design space is in terms of granularity. Designers have the option of building very large processing units, or many smaller ones, in the same space. Traditional architectures are either very coarse grain, such as microprocessors, or very fine grain, such as field programmable gate arrays (FPGAs). Both architectures have advantages and disadvantages.
[0006] Microprocessors incorporate very few large processing units that operate on wide data-words, and each unit is hardwired to perform defined instructions on these data-words. Usually each unit is optimized for a different set of instructions, such as integer and floating point, and the units are generally hardwired to operate in parallel. The hardwired nature of these units allows very rapid instructions. In fact, a great deal of area on modern microprocessor chips is dedicated to cache memories in order to support a very high rate of instruction issue. Thus, the devices efficiently handle very dynamic instruction streams.
[0007] Very fine grain devices, such as FPGAs, incorporate a large number of very small processing elements. These elements are arranged in a configurable interconnect network. The configuration data used to define the functionality of the processing units and network can be thought of as a very large, semantically powerful, instruction word. Nearly any operation can be described and mapped to hardware.
Summary of the Invention
[0008] Unfortunately, because microprocessors are highly optimized for simple, wide-word, dynamic instructions, they are relatively inefficient when performing other kinds of operations. For example, many cycles are required to build up complex operations that are not part of the processor's pre-selected instruction set. Also, when performing short-word operations, much of the processing unit is not being used, and when the instructions being issued are very regular, the large instruction caches are unnecessary. Thus, very coarse-grain microprocessors are not equipped to take the maximum advantage of these cases.
[0009] The size of the “instruction word” creates a number of problems with fine-grain FPGA devices, however. Reloading new instructions takes a relatively long time, making dynamic instruction streams very difficult for these devices. Moreover, if the operation being performed is, in fact, a wide word operation, a great deal of this “instruction word” must be dedicated to re-describing the operation for each of the small processing elements. Thus, fine grain processing elements are not well equipped to take advantage of a large number of common computing operations.
[0010] The present invention utilizes a large number of intermediate-grain processing elements which are arranged in a configurable mesh. Thus, the regularity and rapid instruction issue features of coarse-grain units are exploited, but a reconfigurable or programmable interconnect allows these units to be connected in an application-specific manner. This means that coarse-grain resources, such as memory and processing, can be deployed in a way that takes advantage of the opportunities for optimization present in any given problem. In addition, configuration memories may be deployed to take advantage of application specific redundancy.
[0011] In general according to one aspect, the invention features a programmable integrated circuit that comprises a logic units that perform operations on data in response to instructions and memories that store and retrieve addressed data. A configurable or programmable interconnect provides a mode of signal transmission between the logic units and memories. Configuration control data defines data paths through the interconnect, which can be address inputs to memories, data inputs to memories and logic units, and instruction inputs to logic units. Thus, the interconnect is configurable to define an interdependent functionality of the functional units. A programmable configuration storage stores the configuration control data.
[0012] Thus the present invention may be configured to operate according to a number of traditionally distinct computing architectures. For example, a centrally located functional unit may be assigned the role of arithmetic logic unit (ALU) with memories of surrounding functional units being configured to act as instruction caches, register files, and program counters. Wider data paths are accommodated by tying near-neighbor ALUs to each other. Wider instructions are achieved by configuring instruction memories of separate functional units as if they were a single memory. For a different problem, the same integrated circuit may be reconfigured to emulate a single instruction multiple data (SIMI) architecture. The logic units of rows of functional units are tied together to create wider data paths, and the rows perform separate serial tasks.
[0013] In specific embodiments, functional units may provide at least part of the instructions to logic units of other functional units. Also, the configuration storage may hold multiple contexts of configuration control data for reconfiguration of the programmable interconnect.
[0014] In other embodiments, the interconnect may support three different modes of operation: a static value in which a value set by the configuration data is provided to a functional unit or static source in which another functional unit serves as the value source. A dynamic source mode can be included in which the source is determined by the value from another functional unit.
[0015] In still other embodiments, each logic unit can also have programmable logic arrays on data paths between functional units which perform bit level logic operations. Additionally, reduction logic can be added that performs logic operations on the output of the logic units and passes a result to other functional units as control information. Network drivers are assigned to each unit to transmit received signals to other functional units. The sources of the signals received by the drivers may also be dynamic so that the sources are programmable by other functional units.
[0016] In general according to another aspect, the invention features an integrated reconfigurable computing device, which has functional units of multi-bit arithmetic logic units and memories. A configurable interconnect that connects the units includes function ports which determine the source of the instructions to the logic units. Network ports of the units are configurable by the functional units and determine the source of addresses to the memories and the source of data to the logic units and memories.
[0017] In general according to still another aspect, the invention can also be characterized in the context of a method for organizing signal transmission within an array of functional units. Data read from the memories of functional units may be transmitted as instructions to the logic units of other functional units. Also, data read from logic units may be transmitted as addresses for the memories of other functional units. Finally, the data read from functional units can also be used as data inputs for the logic units of other functional units.
[0018] In specific embodiments, the paths of the data and instructions are dynamic in response to control from the functional units. More specifically, static values, values from other functional units, and values from sources may be transmitted between functional units.
[0019] The above and other features of the invention including various novel details of construction and combinations of parts, and other advantages, will now be more particularly described with reference to the accompanying drawings and pointed out in the claims. It will be understood that the particular method and device embodying the invention are shown by way of illustration and not as a limitation of the invention. The principles and features of this invention may be employed in various and numerous embodiments without departing from the scope of the invention.
Brief Description of the Drawings
[0020] In the accompanying drawings, reference characters refer to the same parts throughout the different views. The drawings are not necessarily to scale; emphasis has instead been placed upon illustrating the principles of the invention. Of the drawings:
[0021] FIG. 1 shows a programmable integrated processing device of the present invention, which has been configured as an 8-bit microprocessor;
[0022] FIG. 2 shows a SIMD processor configuration for the processing device according to the invention;
[0023] FIG. 3 shows a 32-bit processor configuration for the processing device according to the invention;
[0024] FIG. 4 shows a very long instruction word (VLIW) processor configuration for the processing device according to the invention;
[0025] FIG. 5 shows multiple instruction multiple data (MIMD) processor configuration for the processing device according to the invention;
[0026] FIG. 6 is a block diagram showing the architecture of a basic functional unit (BFU) core of the present invention;
[0027] FIG. 7 is a block diagram showing the inter-BFU connectivity provided by the level-i network connections;
[0028] FIG. 8 is a block diagram showing the BFU interconnection provided by the level-2 network connections;
[0029] FIG. 9 is a block diagram showing the network switch architecture for a BFU of the present invention;
[0030] FIG. 10 is a block diagram illustrating the function switch architecture of the present invention;
[0031] FIG. 11 is a block diagram showing the address/data and network switch architecture of the present invention;
[0032] FIG. 12 is a block diagram illustrating the floating port architecture of the present invention;
[0033] FIG. 13 is a block diagram showing the level-1 network drivers of the present invention;
[0034] FIG. 14 shows the level-2 drivers of the present invention;
[0035] FIG. 15 shows the level-3 drivers of the present invention;
[0036] FIG. 16 shows BFU input registers of the present invention;
[0037] FIG. 17 shows the reduction logic in the BFU control architecture of the present invention;
[0038] FIG. 18 is an example of multi-BFU reduction performed by the reduction logic of the present invention;
[0039] FIG. 19 is a block diagram illustrating the operation of the distributed programmable logic array (PLA) associated with each BFU according to the invention;
[0040] FIG. 20 is a block diagram showing the control logic for a single BFU;
[0041] FIG. 21 shows an alternative embodiment of the configuration memory supporting multiple contexts;
[0042] FIG. 22 is a block diagram of the configurable logic device of the present invention in the form of an integrated chip;
[0043] FIG. 23 is a block diagram showing the input/output port architecture for the chip of the present invention;
[0044] FIG. 24 is a block diagram showing the structure of an I/O register according to the invention;
[0045] FIG. 25 is a block diagram of a programmable logic array for customizing the chip's interface;
[0046] FIG. 26 is a block diagram showing the movement of data from the BFU core off-chip according to the invention;
[0047] FIG. 27 is a block diagram of a selector switch that chooses the core outputs to be driven on an output wire according to the invention;
[0048] FIG. 28 is a block diagram showing a tri-state buffer used in the selector switch of FIG. 20;
[0049] FIG. 29 is a block diagram illustrating how data enters the BFU core from off-chip;
[0050] FIG. 30 is a block diagram showing the selector switch that selects among incoming data bytes from I/O ports and PLAs according to the invention;
[0051] FIG. 31 is a block diagram of a C/R input architecture according to the invention;
[0052] FIG. 32 is a block diagram showing the construction of the controller switches of the level-3 network lines according to the invention;
[0053] FIG. 33 is a block diagram illustrating the dynamic control of the controller switches, which is shared between pairs of controllers at each column, according to the invention;
[0054] FIG. 34 shows the architecture of one of the dynamic control switches according to the invention;
[0055] FIG. 35 is a block diagram showing the connectivity of BFUs in a systolic-type configuration according to the invention;
[0056] FIG. 36 shows the configuration of the BFUs for a microcoded-type implementation for the convolution problem according to the invention;
[0057] FIG. 37 shows the organization of the BFUs for a VLIW, horizontal microcode-type implementation according to the invention; and
[0058] FIG. 38 shows the organization of the BFUs for a VLIW/MSIMD-type implementation according to the invention.
Detailed Description of the Preferred Embodiments
[0059] FIG. 1 shows a multi-bit microprocessor configuration of a reconfigurable processing device, which has been constructed and programmed according to the principles of the present invention. A two-dimensional array of basic functional units 100 are located in a programmable interconnect 101. Five of the BFUs 100 and the portion of the reconfigurable interconnect connecting the BFUs have been configured to operate as a microprocessor 102.
[0060] Each of the BFUs 100 preferably has addressable memory resources and logic resources, such as an 8-bit arithmetic logic unit (ALU). One of the BFUs 100, denoted ALU, utilizes its logic resources to perform the logic operations of the microprocessor 102 and utilizes its memory resources as a data store and/or extended register file. Another BFU operates as a function store F that controls the successive logic operations performed by the logic resources of the ALU. Two additional BFUs, A and B, operate as further instruction stores that control the addressing of the memory resources of the ALU. A final BFU, PC, operates as a program counter for the various instruction BFUs F, A, B.
[0061] As shown in FIG. 2, the same reconfigurable processing array, however, may be reprogrammed to function as a SIMD system, and as described below, this reconfiguration can occur on a cycle-by-cycle basis. The functions of the program counter PC and instruction stores A, B and F have been again assigned to different BFUs 100, but the ALU function has been replicated into 12 BFUs. Each of the ALUs is connected via the reconfigurable interconnect 101 to operate on globally broadcast instructions from the instruction stores A, B, F. These same operations are performed by each of these ALU, or common instructions may be broadcast on a row-by-row basis.
[0062] FIG. 3 shows how wider data paths can be constructed in the programmable device. This 32-bit microprocessor configured device has the same instruction stores A, B, F and program counter as described in connection with FIG. 1. Four BFUs, however, have been assigned an ALU operation, and the ALUs are chained together to act as a single 32-bit wide microprocessor in which the interconnect 101 supports carry-in and carry-out operations between the ALUs.
[0063] FIG. 4 shows how the device can be configured to operate as a very long instruction word (VLIW) system. The various instruction stores A, B, F are defined to encompass multiple BFUs 100 to accommodate the desired instruction word width.
[0064] FIG. 5 shows the configuration of the present system to operate as a multiple instruction multiple data (MIMD) system. The 8-bit microprocessor configuration 102 of FIG. 1 is replicated into an adjacent set of BFUs to accommodate multiple, independent processing units within the same device. Of course, wider data paths could also be accommodated by chaining ALUs of each processor 102 to each other.
[0065] 1. Basic Functional Unit Architecture
[0066] FIG. 6 shows the moderately coarse grain, preferably 8-bit, BFU core. Primarily, the BFU core has memory block 110, basic ALU core 120, and configuration memory 105.
[0067] The main memory block 110 is a 256 word×8 bit wide memory, which is arranged to be used in either single or dual port modes. In dual port mode, the memory size is reduced to 128 words in order to be able to perform the two simultaneous read operations without increasing the read latency of the memory. The memory mode is controlled by control logic 114 accessed through a Memory/Mux function port 112, and the write enable can be controlled either through the memory/mux function port 112 or by the control logic 134 accessed through ALU function port 132. Control logic is hardwired and also controls the ALU functions.
[0068] In single port mode, the memory 110 uses the A_ADR port for an address and outputs the selected value to both A_PORT and B_PORT. In dual port mode, the A_ADR port selects a value for A_PORT only, and B_ADR port selects a value for the B_PORT.
[0069] In either mode the read operation takes place during the first half of the clock cycle, and the values are latched for the rest of the cycle. Write operations take place on the second half of the cycle via the DATA memory port. Writes are always done to the current A_ADR address.
[0070] A feedback path 118 shown as a dashed line may be used. The BFU core performs “A op B→A” in one cycle. Two cycles are needed to perform “A op B→C” operations. In this case, the feedback is performed by the normal Level-1 network described in more detail later.
[0071] The configuration memory 105 stores configuration words that control the configuration of the interconnect. It also stores configuration information for a control architecture. Optionally, it can also be a multi-context memory that receives a globally broadcast 2-bit global context selecting signal. The memory is addressed via network port A 122 and receives data from port B 124. The write enable WE is issued by the control logic 114.
[0072] The ALU 120 is a basic 8-bit arithmetic logic processing unit. The following operations are supported:
[0073] Input Invert
[0074] Prior to performing any of the following operations either, or both of the ALU inputs, A_in or B_in, can be inverted.
[0075] Pass
[0076] Passes either A_in or B in to Out. With the input inversion, this operation can be a NOT.
[0077] NAND
[0078] Performs bitwise operation: (A NAND B). With input inversions this can be an OR.
[0079] NOR
[0080] Performs bitwise operation: (A NOR B). With input inversions this can be a AND.
[0081] XOR
[0082] Perform bitwise operation: (A XOR B). With input inversions this can be a XNOR.
[0083] Shift
[0084] Shifts A or B either left or right one bit.
[0085] Add
[0086] Performs (A+B+C_in). C_in can be selected from 0, 1, or C_out of an adjacent cell. Combined with the input inversion a subtract can be made:
[0087] (A−B)−(A+{overscore (B)}+1).
[0088] Multiply
[0089] Performs (A*B). Can also perform (A*B+X) and (A*B+X+Y), where X and Y are special inputs. These operations are needed to create pipelined multiply structures. Multiply operations require two cycles to fuilly complete. The low byte is available on the first cycle and the high byte is available on the second.
[0090] The two network ports 122,124 feed addresses to memory ports A_ADR and B_ADR. Data is feed to the memory 110 from Network port B via the memory DATA port. A data multiplexor 126 selects either the feedback back path 118 or the network port B output. Network ports A and B 122, 124 outputs can feed directly to the ALU 120 by configuring ALU input multiplexors 128,130. The memory function port 112 controls the operation of the data and ALU input multiplexors 126,128,130 via the control logic 114.
[0091] The BFU core is designed to be smoothly chained to other BFUs to form wider-word ALU structures by properly configuring the control logic 134 via the ALU function port Fa. In order to accomplish this, the user must specify the carry-chain of z each of datapath element as it travels through multiple BFUs by setting the following bits in each of the BFUs:
[0092] LSB
[0093] Set to “1 ” marks the least-significant-byte position.
[0094] MSB
[0095] Set to “1” marks the most-significant-byte position.
[0096] Rightsource
[0097] Specifies the direction to the next least-significant-byte, which can also be set to receive a carry from another source.
[0098] Leftsource
[0099] Specifies the direction to the next most-significant-byte, which can also be set to receive a carry from another source.
[0100] The source selection can be one of the following:
[0101] North
[0102] North BFU.
[0103] East
[0104] East BFU.
[0105] South
[0106] South BFU.
[0107] West
[0108] West BFU.
[0109] Local
[0110] The local BFU's carry from the previous cycle.
[0111] Control Bit
[0112] The local Control Bit.
[0113] Zero
[0114] Constant Zero.
[0115] One
[0116] Constant One.
[0117] In addition, pipeline stages can be inserted into the carry chain by specifying CarryPipeline to be “1”. This will register the incoming carry prior to its being used. This is important for addition operations, because the carry-chain is limited by the clock period and the speed of the adder.
[0118] Based on this local information, the actual Shift and Add operations of the ALU 120 have different effects. There are two main shift functions: Left and Right. Left shift moves the bits towards the MSB, and right shifts move the bits towards the LSB. Normally, the carry-in value is used to fill the newly-created opening, but if the cell is an LSB or MSB, the new bit is deternined by additional information contained the chosen shift instruction. For left shifts, the LSB position will be different, while for the Right Shifts it will be the MSB position. The options are:
[0119] Force Carry
[0120] This option will override the LSB/MSB setting and force the shift to use the carry-in from its designated source (Left/Rightsource). This is useful for shift-rotations.
[0121] Skip Bit
[0122] This option will keep the same LSBit/MSBit, essentially duplicating the low/high bit of the shifted number.
[0123] Insert 0
[0124] This will insert a zero into the LSBit/MSBit.
[0125] Insert 1
[0126] This will insert a one into the LSBit/MSBit.
[0127] There are three addition functions: Add, Add-0, and Add-1. Add will perform a normal add-with-carry (A+B+C_in), in all cases. Add-0 will perform a normal add-with-carry, except that the Carry-In of the LSB block will be forced to zero. Add-1 is similar, except that the LSB Carry-In is forced to one.
[0128] Note that a “normal” addition operation is usually performed with the Add-0 function. The basic Add operation is primarily intended for performing “block serial” addition in which addition is performed over multiple cycles on the same set of BFUs. The sequence would be an Add-0, followed by however many Adds are needed to complete the Addition.
[0129] Subtractions are performed using the Add-l operation and inverting the B input value B, i.e., a 2's complement subtract.
[0130] There are four multiplication functions: Mull, Mult-Add, Mult-Add-Add and Mult-Cont. The first three initiate a multiply operation, performing A*B, A*B+X, or A*B+X+Y, respectively. The low byte of the product is available at the end of the current cycle. Mult-Cont is then issued in order to output the high byte. Mult-Cont does not have to be issued but must immediately follow a Mult, Mult-Add, or a Mult-Add-Add. The inputs to the multiply are latched on the cycle the Mult, Mult-Add or Mult-Add-Add is issued, so that the inputs to the BFU 100 may be changed during the Mult-Cont function, without affecting the final value.
[0131] The source for X and Y, if used, is special. There are two configuration bits associated with these inputs: MAdd1source and MAdd2source. If these are set to “0”, the X and Y inputs are hardwired for use in pipelined multipliers. In this case the X input is connected to the nearest North neighbor (L1_N1), and the Y input is hardwired to the output of the NorthWest neighbor (L1_NW) of the previous clock cycle. If the MAddsource bits are set to “1” they allow floating port FP1 and floating port FP2 described later) to select X and Y, respectively.
[0132] Multiple-BFU multiplication operations are more complex than multi-BFU addition or shifting, and will be treated as an application.
[0133] 2. Network Architecture
[0134] The network that joins the BFU cores into a complete array is a three-level interconnect structure, incorporating regular neighbor mesh, longer switchable lines, and long broadcast lines.
[0135] a) Level 1
[0136] FIG. 7 illustrates the connectivity provided by the Level-1 network structure. The output of every BFU core is passed to its nearest neighbors in all directions North, South, East, West, North-East, South-East, South-West, and North-West and its neighbors 2 cells away in the cardinal directions. As a result every cell receives 12 Level-1 inputs. This network is intended to provide fast connections between tightly packed cells.
[0137] b) Level 2
[0138] FIG. 8 shows the Level-2 network structure. This level provides length-4 broadcast lines between rows and columns of cells 200 containing a 5×5 array of BFUts 100. Blocks 213 represent two Level-2 network drivers. Each line shown is a 2-directional broadcast line where the starting drivers 213 are the source of the broadcast.
[0139] Level-2 drives operate in two modes: Source and Pass. Each switch 213 takes in the local BFU output, a byte from the control logic, the Level-1 and Level-3 network lines, as well as other Level-2 lines and selects one. In Source mode, this data is then registered and broadcast on the line on the next cycle. The register is used to add a pipeline stage in network.
[0140] In Pass mode, the data is broadcast without the pipeline stage. This allows longer chains of network lines. At some point, a pipeline stage must be inserted (by using a Source-mode switch) to keep the clock period small. The possible number of links in these chains depends on particular implementations of this design as well as the internal clock speed.
[0141] The two types of switches 136 on this network (vertical and horizontal broadcast) are arranged in a checkerboard pattern of BFUs, so that the same pattern can be found by moving north, east, south, or west two steps. This is important to consider for creating macrocell designs.
[0142] c) Level 3
[0143] The Level-3 network is intended to carry data long distances as rapidly as possible. It consists of 4 shared network lines spanning every row and column. Each BFU cell gets to drive up to 4 inputs onto the Level-3 network. In addition, every BFU has access to every Level-3 line crossing it.
[0144] The delay across Level-3 is also one clock cycle per step, except that steps at this level are up to a full-chip long. Thus it is possible to get from any BFU to any other BFU in the array in 2 clock cycles.
[0145] The control logic for the Level-3 bus line is located at the perimeter of the device's core. The select is broadcast down columns, then a next cycle the value broadcast is used to control the line.
[0146] 3. Network Switches and Ports
[0147] FIG. 9 illustrates the BFU cell 100, which is the smallest logic unit from which more complex processing units can be built. It provides the switching system that controls that data flow between BFUs on the reconfigurable interconnect.
[0148] Four switches, Address/Data A and B ADA, ADB, ALU Function Fa, and Memory Function Fm, feed data into the BFU core via the network ports 122, 124, ALU function port 132, and memory/mux function port 112, respectively, shown in FIG. 1. Four other switches, Floating Port switches FP1 FP2, and Network Switches N1, N2, feed data into the level-2 and -3 network drivers 136. When not being used as network selectors, floating ports FP1 and FP2 can serve to control the dynamic switching capability of the Address/Data A,B and Network Switches.
[0149] Each switchlport selects from its inputs to produce a single byte of output. Each type of switch/port, however, uses a slightly different mechanism for selecting this byte.
[0150] Also shown is CIR logic I and II 202, 203 and OR plane 210. These sections are part of a control architecture that generates a control byte 215 that may be selected as the output of the switches or a control bit 217 that is used to change the configuration bytes controlling the switches' functionality as part of local context control.
[0151] a) Function Ports
[0152] FIG. 10 shows the architecture for each of the two function switches Fa and Fm that control, respectively, a BFU's ALU 120 and memory/multiplexors. The switches Fa,Fm take in 30 byte-sized values from the network at port multiplexor 150. These include the local BFU's output 118, all local Level-1 lines, all crossing Level-2 and Level-3 lines, and the single control byte 215 that is generated by the OR plane 210.
[0153] The selected output of the port multiplexor 150 is provided to a value/source multiplexor 152 which is used to select either the output of the port multiplexor or a static value determined by configuration.
[0154] The port multiplexor 150 and value/source multiplexor 152 are controlled by a 9 bit configuration word. This word is interpreted one of two ways based upon the value of its 9th bit, which controls the value/source multiplexor 152. In Static-Value (Constant) mode, the lower eight bits of the configuration word are passed directly to the BFU via the value/source multiplexor 152. This allows the port's value to be pre-programmed. In the other mode, Static-Source, the lower 5 bits of the configuration word control the port multiplexor 150 to select from the 30 incoming lines and the value on this line is propagated to the BFU 100 through the value/source multiplexor 152.
[0155] The port takes in two configuration words, A and B, and uses a local control bit generated by the distributed compare/reduce logic 203 to select between the words at a local context multiplexor 156. This allows the control architecture to control the operation of the switch to operate in one of two locally generated contexts.
[0156] Finally, the output of the port passes through a register 154 clocked by a global clock. This provides the implicit pipeline stage of the architecture, ie., entering a BFU constitutes a single pipeline stage.
[0157] b) Address/Data and Network Switch Ports
[0158] FIG. 11 illustrates the architecture of the address/data and network switch ports ADA, ADB, N1, and N2. The architecture is very similar to the function port Fa,Fm that is described in connection with FIG. 10, except that in addition to Static-Value and Static-Source modes, it also provides a Dynamic-Source mode in which a floating port output FPout may be used to control the port multiplexor 158.
[0159] In more detail, the mode of the switch ADA, ADB, N1, N2 is determined by configuration word A or configuration word B from the configuration memory 105 based upon the control bit 217. The control bit is received at a selector port of local context multiplexor 166. One bit of the selected configuration word is received at the selector port of dynamiclstatic multiplexer 160. If this multiplexor selects the output of the associated floating port FPout, the port will function in a dynamic mode in which one of the 30 byte-sized values, a local output, 12 level-1, 8 level-2, 8 level-3 and the control byte 215 from the OR plane 210 of the distributed PLA, will be controlled dynamically by the floating port. Alternatively, however, the selection performed by the port multiplexor 158 can be determined by the selected configuration word; this is termed static source mode because the selected value is determined by configuration. Finally, the select bit can also control the value/source multiplexor 160 to pass a value determined by configuration. That is, instead of selecting the output of the port multiplexor 158, the value/source multiplexor 160 can select 8 bits determined by the selected configuration word. Thus, the switch's value can be fixed by the configuration word, come from a fixed source or come from a source that can be selected on a cycle-by-cycle basis.
[0160] Which floating port FP1 or FP2 is the source of FPout depends on the switch port involved. Floating port 1 FP1 controls network switch 1 N1 and address/data A ADA; floating port 2 FP2 controls network switch 2 N2 and address/data B ADB.
[0161] The register 162 on the output again provides the implicit pipelining for the Address/Data ports, but is not used for the Network ports.
[0162] c) Floating Ports
[0163] FIG. 12 shows the floating port architecture FP1,2, which is functionally similar to the function ports Fa,Fm. The floating ports FP1 and FP2 can be programmed to serve a number of different roles. First of all, they can serve as additional switching for the higher-level (Levels 2 and 3) network. They can also serve to control the dynamic source for the address/data ports ADA,ADB and the network switches N1, N2. Finally, they can also provide input to the OR Plane 210 of the control architecture.
[0164] These ports FP1, FP2 are physically identical to the function ports described above in connection with FIG. 10. A port multiplexor 168 selects from the 30 inputs based upon configuration data. A fixed value may be selected by value/source multiplexor 170. A local context multiplexor 172 selects the source of the 9 bit configuration word between words A and B based upon the control bit from the compare/reduce logic 203 or the OR plane 210. Different from the function ports Fa,Fm, however, there is no register on the output. This allows this port's output to be used by other ports immediately without pipeline delay, which is important if the floating port is providing dynamic control to another port.
[0165] d. Network Drivers
[0166] FIG. 13 shows the Level-1 driving network that distributes the BFU output Out from the ALU 120 to the near neighbors as shown in FIG. 7. In an effort to conserve power, it is possible to turn off network wires that are not being used in a particular user's design. Each cardinal direction North, South, East and West has its own driver 174, 176, 178, 180, respectively, which can be disabled independently from other drivers via N-, S-, E-, and W-enable signals. The diagonals are joined with their clock-wise neighbor: North-West with North, North-East with East, South-East with South, and South-West with West. The Level-1 drivers 174-180 for each direction are preferably not tri-state, but instead pull each line to ground when disabled.
[0167] FIG. 14 shows an exemplary Level-2 driver 136 for a single Level-2 network wire. The Level-2 driver 136 is more complicated because there are four switches (N1,N2,FP1,FP2) that can drive to the line via the multiplexor 182.
[0168] One of the four switches FP1, FP2, N1, and N2 is selected to drive each line by the multiplexor 182. In the event that the line is not used, it can be completely disabled in the same way as the Level-1 lines by turning-off or disabling the buffer amplifier 184. Finally, the Level-2 network driver contains an optional register 186, which sets the Source/Pass mode of this L2 cell.
[0169] FIG. 15 shows a Level-3 driver 137, which is similar to the Level-2 version. A multiplexor 188 determines which of the floating ports or network switches FP1, FP2, N1, and N2 drives the line through buffer amplifier 190. The Level-3 network drivers are tristate, and are controlled globally. The register 192 is mandatory here.
[0170] Each BFU cell 100 contains two Level-2 drivers 136 (as shown previously in FIG. 8) and eight Level-3 drivers.
[0171] e. Registers and Time-Switching
[0172] FIG. 16 shows a modification to the input registers 154, 162 of the function, network and address/data switches shown in FIGS. 10 and 11 to incorporate optionally a time-switching capability. If the basic configuration bit in each BFU, TSenable, is set to “1”, then a globally-broadcast 4 bit word 192 selects which step the chip is on. If the broadcasted value 192 matches a 4bit configuration word 194, comparison logic 198 controls the register 162, 154 to latch its values on that cycle in response to a one bit enable signal. Otherwise the register 162, 154 does nothing. This architecture can be used to time-multiplex use of the network wires.
[0173] In total, each BFU 100 requires 8 of these 4bit configuration words. These registers control ports 122, 124, 134, and 112 of the BFU core along with: Control C/R, Control FP1, Control FP2, Write Enable, MAdd-1, and MAdd-2.
[0174] Time-switched control of the write enable means that write-enable only happens if WE is asserted (by whichever port is currently responsible) and if the global step matched the configured TS word.
[0175] 4. Control Architecture
[0176] The control architecture of the embodiment of the invention is designed to be a general-purpose structure that can be programmed to fit the control requirements of a user's application. There are two main types of control: a fast reduction operation and a distributed PLA. Both will be described below. The bit-level details of these modules are listed in Appendix C.
[0177] Referring back to FIG. 9, the output of the BFU core Out first passes through compare/reduce logic 202 before being received by the level-1 network drivers for distribution to the level-1 network.
[0178] FIG. 17 shows the reduction logic 202 in the control architecture, which serves as general-purpose “condition codes” for the outputs of a BFU. The 9-bit output of the BFU 100 (data plus carry-out) is compared to one of two programmed configuration words: Word 1, Word 2. The Control Context Select, which is part of the ALU function, determines which word is used. These words can contain “don't care” bits, so it is possible to test any part of the BFU output. For example, a zero-detect function would test all of the data bits for zeros, but ignore the carry, while a sign-check would i look only at the 8th (high) bit of the data and ignore the rest.
[0179] The result of this comparison 202 is passed to all the BFUs neighbors in the same style as the Level-l network shown in FIG. 7, i.e., all adjacent BFUs and BFUs one removed along the cardinal directions. The Compare/Reduce (C/R) process continues on the all the incoming local C/R values.
[0180] FIG. 18 shows an example of a multi-BFU reduction. The reduction logic I 202 outputs of BFUs I and III are passed to BFU II, where another C/R operation is performed in the BFU II's receiving reduction logic II 203. The final result is the local Control Bit 217 which is used to change the functionality of BFU II's ports and switches via the multiplexors 156,166,172 (see FIGS. 10-12). Note that there is a delay of one cycle for the Level-1 network connection provided by registers 200, just as data is delayed one cycle across the Level-1 network.
[0181] Referring back to FIG. 9, each of the BFUs also has an OR-plane 210 which performs a logic operation defined by the data stored in the configuration memory 105. The OR plane receives, as an input, the 8-bit output from each of the floating ports FP1,2. The logic operation of the OR plane is applied to this output to generate the control byte that is received by each of the port multiplexors 150, 158, 168 of the function switches Fa, Fm, address/data switches ADA, ADB, the floating ports FP1,2, and the network switches N1, N2 (see FIGS. 10-12). The OR plane 210 may also be used to generate the control bit that is also received by the switches, instead of the C/R logic 203.
[0182] FIG. 19 shows the use of a distributed programmable logic array (PLA) of OR planes 210 for more complex control operations that can not be handled by the C/R logic 202, 203. In the example, the BFU output from BFU I gets passed to an OR plane 210A, which is half of a PLA. The fact that a floating port FP1,2 is used to switch BFU Output allows any of the other floating port's inputs to serve as the initial data source. The register 212 after the floating port provides the necessary pipeline stage if the data used is coming off a long network line.
[0183] The OR plane 210A serves as one stage of a multi-level logic finction. Therefore, its eight outputs 214 can be thought of as product-terms of a standard PLA. These product terms are then passed to a Level-2 or Level-3, network as the control byte input to a floating port FP1,2, or network switch N1,N2.
[0184] After the one cycle delay from crossing the network via a second register 216, one of BFU II's floating ports FP1,2 switches the product terms to its OR plane 210B. This plane 210B performs the second stage of the multi-level logic function. If more stages were required to achieve the desired logic operations, the 8 new product terms 215 could be sent to another BFU to continue the operation. In the example shown, only two levels from BFU I and BFU II are required.
[0185] In the distributed PLA model of the control logic, there are two final results. The first is the same as the C/R logic 202: the local Control Bit 217. However, the PLA 210B can also output a Control Byte 215, which can be inserted into a BFU port via address/data switches ADA,ADB or Function switches Fa,Fm or network switch. This allows the control logic to generate specific constants.
[0186] Note that the distributed PLA control requires three cycles to complete a two-level logic operation indicated by registers 212 and 216 on the paths from the floating ports FP and between BFUs, respectively. The PLA 210, however, is capable of performing complex logic operations as well as distributing this control across large portions of a BFU array via the Level-2 and Level-3 network spans. On the other hand, the C/R 202 logic operates in a single cycle, but is limited in functional complexity and distance.
[0187] FIG. 20 shows the complete control logic for a single BFU to illustrate the interoperability of the C/R logic 202, 203 and the OR plane 210. The Comp/Reduce I 202 is performed as described above where the result is simply passed to neighboring Level-1 BFUs, while the Comp/Reduce II 203 is linked with the OR plane 210. This connection allows these two types of control logic to be mixed. For example, the neighborhood Comp/Reduce can be used as an input to the OR plane 210, or the outputs of the floating ports FP1,2 can used in the Comp/Reduce II operation.
[0188] In order to reduce the size of these reduction operations, a number of pre-selections are made on the incoming data. Comp/Reduce II 203 operates on all 13 C/R inputs from the neighbor CJR logic registered at 200, but can only include one of the Floating Port values selected by multiplexor 218. The OR Plane 210 takes in both floating ports FP1,2 to enable logic combination of the outputs. Only 4 bits of the C/R inputs are received via selector 220, which can select any 4. One final bit of configuration selects the source of the Control Bit, either C/R II 203 or OR plane 210 at the multiplexor 219. The selection of the multiplexors 218, 219 and the select 4 logic 220 is set by the configuration data in configuration memory 105.
[0189] Optionally, the reconfigurable processing device may be adapted to have a global context selection in the style of dynamically programmable gate arrays (DPGA) described in U.S. patent application Ser. No. 08/386,851, having common inventors with this application and entitled “Dynamically Programmable Gate Array with Multiple Contexts”, the teachings of which are incorporated herein by this reference in their entirety. As described in connection with FIGS. 10-12, each of the switches Fa, Fm address/data A, B, and network ports N1, N2 receive a control bit 217 that determines local context selection between configuration word A and B. As a modification, each of the BFUs 100 could be additionally provided with a 2-bit globally broadcast context signal.
[0190] As shown in FIG. 21, the configuration memory 105 is divided into 4 contexts, two of which are programmable 472,474 and two of which are hardwired 476,478. The two bit global context select signal selects which portion of this configuration memory 105 is active and the active context determines the configuration words A,B. The two programmable contexts 472,474 are user programmable. Hardwired contexts 476,478 may not be changed, however. These are most useful in a power up situation to ensure that the device is initially in a known state such as boot strapping.
[0191] 6. Perimeter/Boundary Logic
[0192] FIG. 22 shows a core 6×6 array 300 of BFUs 100 surrounded by 12 I/O ports, 3 to a side. This exact number of BFUs in the core 300 may change for different embodiments, but the structures described here will still apply. Also the number of I/O ports may change in different implementations along with the ratio of BFUs to I/O ports.
[0193] The following description concerns the switching logic that connects the core array 300 to the I/O ports N0-2, S0-2, E0-2, W0-2 and vice-versa. Throughout this section “output” refers to data leaving the chip, and “input” refers to data entering the chip. For simplicity, the remainder of this section will describe the north-side boundary, i.e. output signals going north, input signals going south. The chip boundary is symmetrical so that each of the other sides is an exact, but rotated, duplicate of the north side. Any exceptions to this will be noted. The ports will numbered clockwise, so the west-most port on the north side is Port N0, the east-most is Port N2, and similarly for the remaining sides.
[0194] FIG. 24 shows the architecture of an input/output (I/O) port N0, for example. The port N0 supports an 8-bit I/O databus 310 and two I/O control bits 312,314. The data bus 30, and the two bits 312,314 are controlled by independent Output Enable signals Data_0E, Bit0_0E, and Bit1_0E that control separate buffer amplifiers 320-330, which change the port, and the pads, from input to output mode. All data, in or out is registered using I/O registers 332-342. Note that in output mode, the I/O Input value will be the same as the I/O Output value, after two cycles of delay. The input data, for example, propagates through I/O register 332 to I/O register 334.
[0195] The I/O Registers 332-342 are designed to help synchronize internal signals to an external system. The chip takes in a master clock and uses that clock to generate all its internal clocking. One of those internal clocks is a Pad Clock, which is a half-frequency version of the master clock, one phase of the master clock delayed. This pad clock is used to synchronize the input and output data at the pads. Note that the chip runs internally at twice the rate of data I/O.
[0196] FIG. 24 shows how the I/O Registers 332-342 work. A standard D flip-flop 350 latches on the rising edge of the Master CLK. The latching is enabled with either the pad clock or its inversion in dependence on the configuration bit received at multiplexor 352. This allows a user to latch the signal on either edge of the Pad CLK. The selection is controlled by a user-programmed bit. In the hard-wired programming contexts, this is set so that the input registers trigger when Pad CLK is high, and the output registers trigger when Pad CLK is low. This is equivalent to the rising and falling edges, respectively, of Sync CLK the clock used to signal the external system.
[0197] FIG. 25 is a block diagram of a programmable logic array (PLA) 360 that is used to provide a customizable interface with any or most external systems. This fully programmable logic array (PLA) is placed next to each I/O Port N0-2, S0-2, E0-2, W0-2. The PLA takes in 38 bits of data and the data's inverses and performs a selective AND in AND plane 362, generating 45 product terms. These product terms are then selectively ORed in OR plane 364 to generate 15 final outputs. Eight of these output bits are registered 366 and fed back into the input of the PLA 362 to be used as state bits for an up-to 256-state machine.
[0198] The input bits include the 8 state bits, a special PLA input byte, the I/O Input Data byte from the I/O Port, the Compare/Reduce bits that arrive at the north edge of the core and the two special bits from the I/O Port. The special PLA Input Data is a byte selected from all the network lines arriving at the north edge of the core. This byte is selected in the same manner as the I/O Port Data Outputs described below. The registers 368,370 on the PLA In Data and the C/R Output bits are necessary because of the distance those bits must travel in order to get to the PLA.
[0199] The output bits of the PLA 360 include an 8-bit value 372 used as state bits to implement a finite state machine, a special PLA Output byte used to feed data into the core or both. In addition, the PLA outputs 2 bits 374 to be used as inputs to the C/R network in the core, 2 bits 376 to be output as the I/O Port's special bits, and the 3 I/O Output Enable Bits 378. Note that there are pipeline stages on the PLA Out Data and C/R In bits, but these registers will be included in the input switching.
[0200] FIG. 26 shows a block diagram of how data from the BFU core gets off-chip. Eight databuses 380 arrive at an output multiplexor 384 from the edges of every one of the columns 382 of BFUs. The eight databuses 380 include 2 Level-1 lines, 2 Level-2 lines, and 4 Level-3 lines. Diagonal lines are ignored here because the chip side will be viewed as a whole, and the diagonals are simply duplicates of the Level-l lines. For a 6 column-wide core, this totals 48 byte-sized signals that are vying for 3 I/O ports 386, and 3 Input bytes to PLAs 360. In order to ensure generality, each of these values will be selected from all 48, plus the 3 outputs of the PLAs for the I/O Port inputs.
[0201] This selection is performed in a manner similar to the Level-3 Network lines. An Output Selector 388 for each of these 6 outputs is located at the center of the edge. The selector takes in the outputs of the 2 center BFU's columns 382 and the inputs from the I/O Ports and PLAs and chooses one (or a constant) to control which of the 48 core outputs is to be driven on to that output wire.
[0202] FIG. 27 shows one of these selector switches 388. The output selection may come from either of the two center columns via multiplexor 410 or be set by the configuration via multiplexor 414. The register 412 on the output of the multiplexor 410 is used to synchronize the Output Selection byte to the actual Output Data, which is registered at a tri-state buffer shown in FIG. 28.
[0203] FIG. 29 is a block diagram illustrating how data enters the BFU core from off-chip. At each BFU column 382, 4 values may be inserted: L1_N1, L1_N2, L2_N1, and L2_N2, from the perspective of the top-most BFU in the column 382. From the point of view of a core BFU, these signals will appear to be coming from another BFU in the appropriate position, i.e., the perimeter position is transparent to the BFUs in the core. The diagonal connections assume this logical position, i.e., the NW input of a BFU is the same as the N1 input to its west neighbor. The only exception is the NE input on the east-most BFU. This position has its own switch. Note that the NW input to the west-most BFU will be handled by the west-side switching logic.
[0204] Each of these 4 values can select from 6 incoming data bytes: one from each of the I/O Ports 386 and one from each of the PLAs 360. This selection is made using the Input Selector switch 420.
[0205] FIG. 30 details the input selector 420. Note the pipeline register 422 on the output of the multiplexor 424 is controlled by the three bit configuration word.
[0206] FIG. 31 shows the architecture for switching the C/R inputs to core. One-bit versions 430 of the input selector switches 420, described previously, are used. The C/R selectors 430 can select from any of the 6 C/R inputs from the PLAs.
[0207] The Level-3 network lines are also controlled on the perimeter of the chip. The Level-3 Controllers select which BFU or I/O line drives the line on a given cycle (all 6 input/PLA lines, on both sides of the chip, can feed the Level-3 network). There is one controller per Level-3 line arranged so that there are two controllers at both ends of the rows/columns. On the North and East sides, controller 1 controls the V0 or H0 lines, while controller 2 controls the V1 and H1 lines. On the South and West sides, controller 1 controller V2 or H2, while controller 2 controls V3 or H3.
[0208] These controller switches are similar to the Address/Data and Network Switches in the BFU, in that they operate in constant value, static source, and dynamic source modes. FIG. 32 shows one of these switches 462.
[0209] The multiplexor 450 takes in all of the data outputs arriving at the edge of the that column: 2 Level-1, 2 Level-2 and Level-3 lines, the 6 input/PLA lines, as well as the diagonal connections from neighboring columns except at the comers where those lines do not exist. Multiplexor 452 determines whether the 5 bits of the configuration word sets the output through register 454.
[0210] The dynamic control for these switches comes from a switch that is shared between the pairs of controller at each end of the column. FIG. 33 shows the arrangement at one end of one column in which a dynamic control switch 460 controls adjacent three Level-3 controllers 462. The dynamic control switches are shown in FIG. 34. These switches are essentially static-source only versions of the Level-3 controller switches.
[0211] 7. Usage
[0212] For illustrative purposes, various convolution implementations are shown on the device for a convolution task as follows: Given a set of k weights {w1, w2, . . . wk} and a sequence of samples {x1, x2, . . . }, compute a sequence of results {y1, y2, . . . } according to:
[0213] yi=w1·xi+w2·xi+1+ . . . +wk·xi+k−1
[0214] a. Systolic
[0215] FIG. 35 shows an eight-weight (k=8) convolution of 8-bit samples accumulating a 16-bit result value. The top row simply carries sample values through the systolic pipeline. The middle row performs an 8×8 multiply against the constants weights, w's, producing a 16-bit result. The multiply operation is the rate limiter in this task requiring two cycles to produce each 16-bit result. The lower two rows accumulate yiresults. In this case, all datapaths are wired using static source mode. The constant weights are configured as static value sources to the multiplier BFUs. ALU operations are set in static value mode. Add operations are configured for carry chaining to perform the required 16-bit add operation. For a k-weight filter, this arrangement requires 4k cells and produces one result every 2 cycles, completing, on average, {fraction (k/2+L )}8×8 multiples and {fraction (k/2+L )}16-bit adds per cycle.
[0216] In practice the horizontal level-two bypass lines can be used for pipelining the inputs, removing the need for the top row 510 of BFUs simply to carry sample values through the pipeline.
[0217] The horizontal and vertical level-two by-pass lines re-time the data flowing through the add pipeline so that only a single BFU adder is needed per filter tap stage.
[0218] Three instruction-stores and a program counter (PC) (not shown) control the operation of the multiply and add BFUs, as well as the advance of samples along the sample pipeline.
[0219] The k-weight filter can be implemented with) only 2k+4 cells in practice.
[0220] b. Microcoded
[0221] FIG. 36 shows a microcoded convolution implementation. The k coefficient weights are stored in the register-file memory of the BFU 100 configured to function as the ALU 520. Registers 1 through k hold the coefficient weights and the last k samples are stored in a ring buffer constructed from registers 65 through 64+k. Six other memory location (Rs, Rsp, Rw, Rwp, R1, and Rh) are used to hold values during the computation. The A and B ports of ALU BFU 520 are set to dynamic source mode. The memory blocks of surrounding BFUs are assigned to feed data to ALU 520. BFUs 522,524 control the source of the A and B input to the ALU (two Isrcmemories). The values fed into the A and B inputs of the ALU are provided by BFUs 526 and 528, respectively (Ia,Ib) BFUs 530 and 532 provide the memory function (Imf) and the ALU function (Ialu). The program counter BFU PC 534 is a BFU setup to increment its output value or load an address from its associated memory.
[0222] The implementation requires 8 BFUs and produces a new 16-bit result every 8k+9 cycles. The result is output over two cycles on the ALU's output bus. The number of weights supported is limited to k≦61 by the space in the ALU's memory. Longer convolutions (larger k) can be supported by deploying additional memories to hold sample and coefficient values.
[0223] Custom VLIW (Horizontal Microcode)
[0224] FIG. 37 shows a VLIW-style implementation of the convolution operation that includes application-specific dataflow. The sample pointer (Xptr) and the coefficient pointer (Wptr) are each assigned to BFUs 540,542. Separate ALUs are used for the multiply operation and the summing or add operation BFU 546. This configuration allows the inner loop to consist of only two operations, the two-cycle multiply in parallel with the low and high byte additions. Pointer increments are also performed in parallel. Most of the I-stores used in this design only contain a couple of distinct instructions. With clever use of the control PLA and configuration words, the number of I-stores can be cut in half making this implementation no more costly than the microcoded implementation.
[0225] As shown, the implementation requires 11 BFUs and produces a new 16-bit result every 2k +1 cycles. As in the microcoded example the result is output over two cycles on the ALU output bus. The number of weights supported is limited to k≦64 by the space in the ALU's memory.
[0226] VLIW/SIMD
[0227] FIG. 38 shows a SIMD/VLIW hybrid implementation based on the control structure from the VLIW implementation. As shown in the figure, six separate convolutions are performed simultaneously sharing the same VLIW control developed to perform a single convolution, amortizing the cost of the control overhead. To exploit shared control in this manner, the sample data streams must receive data at the same rate in lock step.
[0228] BPU Details
[0229] A.1 Basic Configuration
[0230] A BFUs basic configuration consists of LSB (I bit), MSB (1 bit), RightSource (3 bits), LeftSource (3 bits), CarryPipeline (1 bit), TSenable (1 bit), MAddlsource (1 bit), and MAdd2source (1 bit) bits. The following tables describe the bit-setting of this configuration in more detail:
[0231] A.2 ALU Port
[0232] The following shows the breakdown of the bits of the ALU Function Port:
[0233] Bit<7>Memory Write Enable (WE)—“1”=Write
[0234] Bit<6>Control Context Select (see Section 5.1)
[0235] Bit<5>
[0236] Invert B input—“1”=Invert
[0237] Shift Input Selection—“1”=B input
[0238] Pass Source Selection—“1”=B input
[0239] Bit<4>
[0240] Invert A input—“1” Invert
[0241] Shift Direction—“1”=Left
[0242] Pass Invert Selection—“1”=Invert
[0243] Bits <3:0>ALU Operation. See Table below:
[0244] Note that Opcode 11 is essentially unused, but if accidently issued will generate an Add-1 function.
[0245] For Shift and Pass operations, the Invert-A, and Invert-B controls have special functions:
[0246] For Shift, Invert-A is used to select the Shift Direction (Left or Right) and Invert-B is used to select the Shift Source (A input or B input). In the current model, there is no way to perform an inversion during a shift operation.
[0247] For Pass, Invert-A is used to invert the Pass value and Invert-B is used to select the Pass Source (A or B input).
[0248] A.3 Memory/Multiplexor Controller Port
[0249] The following shows the breakdown of the bits of the Memory Function Port:
[0250] Bits <1:0>are currently unused.
[0251] B Switcb/Port Configuration Details
[0252] 20 B.1 Switch Mode Selection
[0253] The configuration word used by the switch/ports is either a 9 or 10 bit value. The 9th bit determines whether or not the port has a constant value. The10th bit, if it exists, determines whether the source selection (if used) is static or dynamic.
[0254] Therefore, in the 9 bit case (used by the Function and Floating Ports):
[0255] And in the 10 bit case (used by the Address/Data and Level-2 Network Ports):
[0256] B.2 Constant Value Selection
[0257] The constant value of a pert is determines by the lower 8 bits of configuration (Bits <7:0>).
[0258] B.3 Source Selection
[0259] The source selection is performed by the lower 5 bits of configuration (or FPout value in the Dynamic Source case). The selection is the same for all ports:
[0260] Notes:
[0261] On the Level-2 network, “1” and “2” lines are defined as the distance to the broadcasting L2 switch, divided by 2. Therefore the “1” line could either come from 1 or 2 cells away, and the “2” line could come from either 3 or 4 cells away.
[0262] On the Level-3 network, Vertical is defined as North-South and Horizontal is as defined as East-West. Because they apply uniformly to the entire chip, the numbering (from 1-4) is arbitrary, except that the Vertical-4 lines are the ones used for programming.
[0263] The constant values are a way of inserting constants into BFU, without changing the port configuration. In most cases these insert data values of zero and one. For the Fa (ALU) port, C0 is a plain A_Pass and C1 is a plain B_Pass. For the Fm (Memory) port, both C0 and C1 cause the BFU to ignore its memory and simply pass the inputs to the ALU. The only difference between them is the direction of the carry-in (C0 is from the north—vertical carry chain, C1 is from the east—horizontal carry chain). Thus the C0 and C1 port inputs effectively amount to no-operation instructions.
[0264] B.4 Driver Control
[0265] B.4.1 Level-1
[0266] The Level-1 driver control consists simply of 4 enables: North (including NW), East (including NE), South (including SE), and West (including SW). When these bit are set to “1”, these drivers drive. When set to “0” the network lines are set to ground.
[0267] B.4.2 Level-2 and Level-3
[0268] Each Level-2 driver requires 4 bits of information:
[0269] The Level-3 drivers require only the two bits of switch select information. The Register Enable is unused (always enabled) and the driver enables come from the perimeter logic (See Section 6).
[0270] The switch selectors on the Level-2 and Level-3 drivers use a two-context configuration, similar to the network switches. The driver enables are single context. There are 2 Level-2 and 8 Level-3 drivers in every BFU.
[0271] C Control Configuration Details
[0272] C.1 Compare/Reduce Logic
[0273] The reduction logic configuration is the word that will be compared to the Comp/Reduce block's input. In this word, each bit-position can take four states: Zero, One, Don't Care, or Fail. A 0 succeeds in the Zero state, while a 1 succeeds in the One state. When an incoming bit is compared to a Don't Care, it always succeeds. Conversely, when the bit is compared to a Fail it always fails. Thus, each bit-position of the comparison word must be represented by 2 bits. The first (low) bit is the output of the bit-position if the input is a 0, the second is the output if the input is 1. This is outlined in the following table:
[0274] Based on this, the two Comp/Reduce Block configurations are 18 bits for C/R I and 42 bits for C/R II. The bit-positions for C/R I match the bit-positions of the BFU output, where the carry is the high 9th bit. Note that there are actually two 18 bit words associated with C/R I—one for each of the control contexts (see FIG. 10). The breakdown for the C/R II inputs are as follows:
[0275] C.2 OR Plane
[0276] The OR plane has 20 inputs and 9 outputs. Each of the 20 inputs is inverted and both polarities are used in the array. Each output therefore requires 40 bits of configuration. Each bit of these words selects one input (in positive or inverted form) to be in the OR operation. Each of these 40-bit words is arranged as follows:
[0277] The first (lower) of each of these pairs of bits controls the positive input, while the second controls the inverted input.
[0278] C.3 Comp/Reduce Select-4
[0279] The configuration for the selection of Compare/Reduce inputs to the OR Plane consists of 4 4-bit numbers. Each number selects one of the 4 inputs. The C/R line selected is given on the following table:
[0280] C.4 Multiplexor Selection
[0281] There are two multiplexors in the control logic, labeled as follows:
[0282] Each of these selects consists of one bit and have the following effects:
[0283] D Perimeter Details
[0284] D. I/O Register
[0285] Each I/O register has a single configuration bit which defines which edge of the Pad CLK (Sync CLK) the register uses to latch its data.
[0286] D.2 Port PLAs
[0287] D.2.1 AND Plane
[0288] The AND plane of a Port PLA has 38 inputs and 45 outputs (product terms). Each of the 38 inputs is inverted and both polarities are available in the array. Therefore each output of the AND plane is specified by 76 bits of data. The bit pairs are arranged as follows:
[0289] Each bit represents an input bit, and its inverse, in that order.
[0290] D.2.2 OR Plan
[0291] The OR plane of a Port PLA has 45 inputs (the product terms), and 15 outputs. Unlike for the AND plane, the inputs are not inverted, so that each of the 15 outputs is specified by 45 bits, one for each product tern. The outputs are in the following order:
[0292] D.3 Output Selection
[0293] D.3.1 Data Selection
[0294] Each of the 3 I/O Port Outputs has 51 possible drivers. The 3 PLA Inputs each have 48 possible drivers (they don't get the PLA outputs). A 6-bit output control bus selects one of these, according to the following tables:
[0295] Selector Groups
[0296] Groups 0-5
[0297] Note: The S1 and S2 designations refers to what those signals would be if seen by an extra BFU at the end of the column.
[0298] D.3.2 Selector Switch
[0299] The switch that determines this output selection is a Constant Value/Static Source switch. It takes a 7-bit configuration word, where the 7th bit switches between Constant Value (“0”) and Static Source “1”. The remaining 6 bits either provide the selection word directly, or choose one of the following static sources:
[0300] D.4 Input Selection
[0301] Each of the BFU column input switches takes in 6 possible values. This is controlled by a static 3-bit configuration word. The following table describes the selection:
[0302] The C/R Inputs are also selected using a 3-bit configuration word:
[0303] D.5 Level-3 Network Controllers
[0304] D.5.1 Data Selection
[0305] The output of each Level-3 Network controller determines which Level-3 driver drives that particular line. The selection is perforned by a 5-bit selector:
[0306] D.5.2 Controller Switch Selection
[0307] The Level-3 Controller Switch used to select the source is a Constant Value, Static Source, or Dynamic Source Switch. Its takes a 7-bit configuration word, where the top two bits control the switch mode. See the table in Appendix B. 1. The remaining 5 bits serve as the constant value, or select the static source as follows:
[0308] D.5.3 Dynamic Switch Selection
[0309] The Dynamic Control Switch for the Level-3 Controllers is a fully static source version of the Level-3 Controller described above. It takes a 4 bit configuration word and uses that as the static source selector in the manner described by the table above.
[0310] E. Configuration Details
[0311] This section will detail the address space of the configuration memories of a the chip. The address space is 15 bits wide (the 16th programming address bit selects between the configuration and main BFU memories). Of these 15 bits the high bit selects between the Core (“0”) and the Perimeter (“1”). The breakdown of the remaining 14 bits is shown in FIG. 27.
[0312] Row Address and Column Address are the position of the BFU where BFU(0,0) is at the SW corner of the chip.
[0313] The Side Selection (Perimeter Address) is performed as follows:
[0314] The BFU and Side configurations are described below.
[0315] E.1 BFU Configuration Space
[0316] There are two parts to a BFU's configuration: the main BFU configuration and the OR plane configuration. They are separated because while the main BFU configuration has two global contexts (see Section ??), the OR plane does not.
[0317] The BFU Configuration Address is an 8-bit word. The 8th bit selects between Context 2 (“0”) and Context 3 (“1”). As mentioned above, this does not apply to the OR plane—it is addressed on both settings. The 7th bit selects between the main BFU configuration (“0”) and the OR plane configuration (“1”). The remaining 6 bits are described below.
[0318] E.1.1 Main BFU Configuration
[0319] Note: The “SD” in entries such as F_Port_SD refers to the Static/Dynamic selection bits for that particular port.
[0320] L2_1 is the driver for either the North or East Level-2 line, and L2_2 is the driver for either South or West Level-2 line, depending on the BFU position.
[0321] E. 1.2 OR Plane Configuration
[0322] The OR Plane is configured by a bit stream which is simply the concatenation of the bit vectors for each output. Section C describes these bit vectors. The bit stream is broken into 8-bit chunks, and addresses in sequence. Because each output vector is 40 bits long, this divides evenly.
[0323] The whole stream consists the OR0 output through the OR8 output, where OR07 are the Control Byte outputs and OR8 is the Control Bit output. There are a total of 45 full bytes in the stream (5 for each output).
[0324] E.2 Side Configuration Space
[0325] The Side Configuration Address is 12 bits long. With this much space, it is possible to sparsely encode the data for easy decoding. Any addresses not mentioned here are unused.
[0326] The high bit (<11>) is used to select between the PLA's (“1”) and the rest of the perimeter logic (“0”).
[0327] E.2.1 PLA Configuration
[0328] The PLA configuration is broken down as follows:
[0329] Like the BFU OR Planes, the AND and OR planes of the perimeter PLAs are specified by bit streams, which are concatenation of the bit vectors for each output.
[0330] The AND plane has 45 outputs (product terms), each of which is specified by a 76-bit long vector. Each vector is broken into 10 bytes, where the final byte has 4 unused bits. The vectors are arranged in order, so that Pterm0 is first and Pterm44 is last.
[0331] The OR plane has 15 outputs, each of which is specified by a 45-bit vector. Each vector is broken into 6 bytes, where the final byte has 3 unused bits.
[0332] Note that the PLAs have single context memories.
[0333] E.2.2 Non-PLA Perimeter Configuration
[0334] The remaining perimeter logic is split up as follows:
[0335] All this logic, except the I/O Registers, have two contexts. These contexts are selected via Bit<7>, where 0=Context 2 and 1=Context 3.
[0336] 1. I/O Registers
[0337] There are only three bytes of data associated with the I/O Registers, on for each port (0,1 and 2, addressed accordingly). The bits are arranged as follows:
[0338] 2. Output Switches
[0339] Each output switch is controlled by a 7-bit word. These words are treated as bytes with the high bit ignored, and addressed as follows:
[0340] 3. Input Switches
[0341] Each input switch is controlled by a 3-bit word. These words are treated as bytes with the high 5 bits ignored. Bits <5:3> of the address are treated as a row or column address (depending on the side). Bits <2:0> address the specific switches:
[0342] Note: The switches listed here are for the North side of the chip. Other sides are symmetric. The lines are labeled at the north-most BFU of the column sees them.
[0343] 4. C/R Input Switches
[0344] Each C/R input switch is also controlled by a 3-bit word. Like the Inputs Switches, above, these words are treated as bytes with the high 5 bits ignored. Bits <5:3> of the address are treated as a row or column address (depending on the side). Bits<2:0> address the specific switches as shown in the table above.
[0345] 5. Level-3 Controllers
[0346] The Level-3 controller switches are each controlled by a 7-bit word. The Level-3 dynamic controller switches are each controlled by a 4-bit word. These words are each treated as bytes with the high bit (or 4 bits) ignored. Bits <5:3> of the address are treated as a row or column address (depending on the side). Bits <1:0> address the specific switches:
[0347] Note that Bit<2> isn't used for the Level-3 controllers so that the row/column address is in the same position as the input switches.
[0348] While this invention has been particularly shown and described with references to preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention as defined by the appended claims. For Example, while the ALU 120 and memory block 110 are described as being associated with each other in the BFU, they could be distributed from each other with the interconnect handling all memory-to-ALU communication. Also, in some implementations, the described processing device could be associated with memory or a larger conventional microprocessor as an accelerator, for example.
Claims
We claim:
1. A programmable integrated circuit comprising:
logic units which perform operations on data in response to instructions of a defined set of instructions;
memories which store and retrieve data in response to received addresses;
a configurable interconnect which provides signal transmission between the logic units and memories, the interconnect being configurable from configuration control data to define data paths, originating at logic units and/or memories, through the interconnect as address inputs to memories, data inputs to memories and logic units, and instruction inputs to logic units such that the interconnect is configurable to operate on data addresses or instructions; and
programmable configuration storage for storing the configuration control data.
2. An integrated circuit as claimed in claim 1 wherein at least one memory provides at least part of the instructions to a logic unit.
3. An integrated circuit as claimed in claim 1 wherein the logic units are configurable to receive data directly from associated memories.
4. An integrated circuit as claimed in claim 1 wherein the configuration storage stores multiple contexts of configuration control data for reconfiguration of the programmable interconnect.
5. An integrated circuit as claimed in claim 4 wherein a context selection signal that selects among the multiple contexts is routed by the configurable interconnect.
6. An integrated circuit as claimed in claim 1 wherein the interconnect is configurable to provide a static value to a logic unit or to provide a variable value from a static source.
7. An integrated circuit as claimed in claim 1 wherein the memories are deployable as data memory, register files, program counters, and instruction stores for other logic units.
8. A programmable integrated circuit comprising:
logic units which perform operations on data in response to instructions of a defined set of instructions;
memories which store and retrieve data in response to received addresses;
a configurable interconnect which provides signal transmission between the logic units and memories, the interconnect being configurable from configuration control data to define data paths through the interconnect as address inputs to memories, data inputs to memories and logic units, and instruction inputs to logic units such that the interconnect is configurable to operate on data addresses or instructions; and
programmable configuration storage for storing the configuration control data;
wherein a global context selection signal that selects among multiple contexts is globally broadcast to the programmable configuration storage of the device.
9. A programmable integrated circuit comprising:
logic units which perform operations on data in response to instructions of a defined set of instructions and which are configurable to be chained together to form wider data paths than provided by a single logic unit;
memories which store and retrieve data in response to received addresses;
a configurable interconnect which provides signal transmission between the logic units and memories, the interconnect being configurable from configuration control data to define data paths through the interconnect as address inputs to memories, data inputs to memories and logic units, and instruction inputs to logic units; and
programmable configuration storage for storing the configuration control data.
10. A programmable integrated circuit comprising:
logic units which perform operations on data in response to instructions of a defined set of instructions;
memories which store and retrieve data in response to received addresses;
a configurable interconnect which provides signal transmission between the logic units and memories, the interconnect being configurable from configuration control data to define data paths through the interconnect as address inputs to memories, data inputs to memories and logic units, and instruction inputs to logic units such that the interconnect is configurable, the interconnect being configurable to provide a value to a logic unit or memory from a source, which is determined by a value from another logic unit or memory; and
programmable configuration storage for storing the configuration control data.
11. A programmable integrated circuit comprising:
logic units which perform operations on data in response to instructions of a defined set of instructions;
memories which store and retrieve data in response to received addresses, the logic units being each grouped with memories to form repeating functional units;
a configurable interconnect which provides signal transmission between the logic units and memories, the interconnect being configurable from configuration control data to define data paths through the interconnect as address inputs to memories, data inputs to memories and logic units, and instruction inputs to logic units such that the interconnect is configurable to operate on data, addresses or instructions; and
programmable configuration storage for storing the configuration control data.
12. An integrated circuit as claimed in claim 11 further comprising programmable logic arrays on data paths between functional units which perform bit level logic operations.
13. An integrated circuit as claimed in claim 11 further comprising reduction logic which performs logic operations on the output of the logic units and passes a result to other functional units as control information.
14. An integrated circuit as claimed in claim 11 wherein the interconnect comprises network drivers which transmit received signals between the memories and logic units.
15. An integrated reconfigurable computing device, comprising: an array of functional units comprising:
multibit arithmetic logic units which perform operations on data in response to instructions;
memories which store and retrieve data in response to received addresses;
function switches which determine the source of the instructions to the logic units; and
switches which are configurable by the other functional units and determine the source of addresses to the memories and the source of data to the logic units and memories.
16. An integrated circuit as claimed in claim 15 wherein the logic units are configurable to both operate on data from the associated memories and operate on data received from outside the functional unit via the switches.
17. An integrated circuit as claimed in claim 15 wherein the function switches also determine the configuration of the memories.
18. An integrated circuit as claimed in claim 15 wherein the switches are configurable to provide static values, values from other functional units, and values from sources, which are determined by other functional units.
19. An integrated circuit as claimed in claim 15 wherein in the output from the arithmetic logic units are distributed over a local network to near-neighbor functional units.
20. An integrated circuit as claimed in claim 15 wherein the functional units comprise network drivers which transmit received signals to other functional units.
21. An integrated circuit as claimed in claim 20 wherein sources of the received signals to the network drivers are programmable by other functional units.
22. A method for organizing signal transmission within an array of logic units which perform operations on data in response to instructions and memories which store and retrieve data in response to received addresses, the method comprising:
transmitting data read from the memories as data to the logic units or addresses or data to other memories;
transmitting data generated by the logic units as data to other logic units or addresses or data to the memories; and
transmitting data from logic units or memories as control to other logic units or memories.
23. A method as claimed in claim 22 further comprising reorganizing the paths of the data in response to control from the array.
24. A method as claimed in claim 22 further comprising transmitting static values, values from other memories or logic units, and values from sources determined by the memories or logic units.
25. A method as claimed in claim 22 further comprising performing bit level logic operations to control data paths between memories or logic units.
26. A method as claimed in claim 22 further comprising selecting among multiple contexts using a globally broadcast context selection signal to programmable configuration storage.
27. A method as claimed in claim 26 wherein a global context selection signal that selects among the multiple contexts is globally broadcast to the programmable configuration storage.
28. A method as claimed in claim 22 further comprising configuring the logic units to be chained together to form wider data paths than provided by a single logic unit.
29. A method as claimed in claim 22 further comprising providing a value to a logic unit or memory from a source, which is determined by a value from another logic unit or memory.
30. A method as claimed in claim 22 further comprising grouping each of the logic units with memories to form repeating functional units.
Patent Citations (24)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US4597041 | 1986-06-01 | Guyer et al. | Applicant |
| US4748585 | 1988-05-01 | Chiarulli et al. | Applicant |
| US4754412 | 1988-06-01 | Deering | Applicant |
| US4858113 | 1989-08-01 | Saccardi | Applicant |
| US4870302 | 1989-09-01 | Freeman | Applicant |
| US4873626 | 1989-10-01 | Gifford | Applicant |
| US5020059 | 1991-05-01 | Gorin et al. | Applicant |
| US5218709 | 1993-06-01 | Fijany | Examiner |
| US5233539 | 1993-08-01 | Agrawal et al. | Applicant |
| US5239654 | 1993-08-01 | Ing-Simmons et al. | Applicant |
| US5241635 | 1993-08-01 | Papadopoulos et al. | Applicant |
| US5261077 | 1993-11-01 | Duval | Examiner |
| US5265207 | 1993-11-01 | Zak | Applicant |
| US5301340 | 1994-04-01 | Cook | Applicant |
| US5305462 | 1994-04-01 | Grondalski | Applicant |
| US5327540 | 1994-07-01 | Heil | Examiner |
| US5336950 | 1994-08-01 | Popli et al. | Applicant |
| US5426378 | 1995-06-01 | Ong | Applicant |
| US5457644 | 1995-10-01 | McCollum | Applicant |
| US5557743 | 1996-09-01 | Pombo | Examiner |
| US5684980 | 1997-11-01 | Casselman | Applicant |
| US5901332 | 1999-05-01 | Gephardt | Examiner |
| US5956518 | 1999-09-01 | Dehon | Examiner |
| US6122719 | 2000-09-01 | Mirsky | Examiner |
Non-Patent Literature (36)
- T. Bridges, “The GPA Machine: A Generally Partitionable MSIMD Architecture,” Third Symposium on the Frontier of Massively Parallel Computation Proceedings IEEE pp. 196-203 (1990).Applicant
- P. Clarke, “Pilington Preps Reconfigurable Video DSP,” News (Aug. 7, 1995).Applicant
- D.C. Chen, et al., “A Reconfigurable Multiprocess IC for Rapid Prototyping of Algorithmic-Specific High-Speed DSP Data Paths,” IEEE Journal of Solid-State Circuits, vol. 27, (12):1895-1904 (Dec. 1992).Applicant
- A.K. Young, et al., “TA 6.3: A 2.4GOPS Data-Given Reconfigurable Multiprocessor IC for DSP,” IEEE International Solid-State Circuits Conference, pp. 108-109, 346 (1995).Applicant
- J.E. Brewer, et al., “A Monolithic Processing Subsystem,” IEEE Transactions on Components, Packaging, and Manufacturing Technology—Part B, vol. 17(3):310-317 (Aug. 1994).Applicant
- I. Gilbert, Chapter 11—Mosh Multiprocessing, The Lincoln Laboratory Journal, 1(1):11.1-11.18 (Spring 1988).Applicant
- Ira H. Gilbert, et al., “The Monolithic Synchronous Processor,” Lincoln Laboratory, Massachusetts Institute of Technology, Lexington, MA 02173 (No Date Given).Applicant
- G. Masera, et al., “A Microprogrammable Parallel Architecture for DSP,” IEEE, pp. 824-827, (1991).Applicant
- L. Wang, et al., “Distributed Instruction Set Computer,” Proceedings of the 1988 International Conference on Parallel Processing, vol. 1, pp. 426-429.Applicant
- M. Sowa, et al., “Parallel Execution on the Function-Partitioned Processor with Multiple Instruction Streams,” Systems and Computers in Japan, 22(4):22-27 (Nov. 1991).Applicant
- T. Alexander, et al., “A Reconfigurable Approach to a Systolic Sorting Architecture,” IEEE, pp. 1178-1182 (1989).Applicant
- Z. Blazek, et al., “Design of a Reconfigurable Parallel RTSC-Machine,” North-Holland Microprocessing and Microprogramming21, pp. 39-46, (1987).Applicant
- S. Morton, et al., The Dynamically Reconfigurable CAP Array Chip I, IEEE Journal of Solid-State Circuits, SC21(5) :820-826 (Oct. 1986).Applicant
- L. Snyder, “A Taxonomy of Synchronous Parallel Machines,” Proceedings of the 1988 International Conference on Parallel Processing, pp. 281-285 (Aug. 1988).Applicant
- L. Snyder, “An Inquiry into the Benefits of Multigauge Parallel Computation,” Proceedings of the 1985 International conference on Parallel Processing, pp. 488-492 (Aug. 1985).Applicant
- A DeHon, “DPGA Utilization and Application,” FPGA '96—ACM/SIGDA Fourth International Symposium on FPGAs, Monterey, CA (Feb. 11-13, 1996).Applicant
- D. Epstein, “Chromatic Raises the Multimedia Bar,” Microprocessor Report, pp. 23-27 (Oct. 23, 1995).Applicant
- J. Labrousso, et al., “Create-Life: A Modular Design Approach for High Performance ASIC's,” IEEE CH2843, pp. 427-433 (Jan. 1990).Applicant
- M. Slater, “MicroUnity Lift Veil on MediaProcessor,” Microprocessor Report, pp. 11-18 (Oct. 23, 1995).Applicant
- E. Tau, et al., “A First Generation DPGa Implementation,” FPD '95—Third Canadian Workshop of Field-Programmable Devices Montreal, Canada (May 29-Jun. 1, 1995).Applicant
- S. Kartashev, et al., “A Multicomputer System with Dynamic Architecture,” IEEE Transactions on Computers, vol. C-28, No. 10, pp. 704-721 (Oct. 1979).Applicant
- D. Bursky, “Programmable Data Paths Speed Computations,” Electronic Design, pp. 171-174 (May 1, 1995).Applicant
- V. Bove, Jr., et al., “Cheops: A Reconfigurable Data-Flow System for Video Processing,” IEEE Transactions on Circuits and Systems for Video Technology, pp. 140-149 (1995).Applicant
- M. Schaffner, “Processing by Data and Program Blocks,” Transactions on Computers, vol. C-27, No. 11, pp. 1015-1027 (Nov. 1978).Applicant
- J. Nickolls, “The Design of the MasPar MP-1: A Cost Effective Massively Parallel Computer,” IEEE CH2843, pp. 25-28 (Jan. 1990).Applicant
- B. Narasimha, “Performance-Oriented, Fully Routable Dynamic Architecture for a Field Programmable Logic Device,” UCB/ERL M93/42, University of California, Berkeley, pp. 1-21 (Jun. 1993).Applicant
- M. Bolotski, et al., “A 1024 Processor Sns SIMD Array,” Advanced Research in VLSI 1995, pp. 1-13 (1995).Applicant
- D. Cherepacha, et al., “A Datapath Oriented Architecture for FPGAs,” Second International ACM/SIGDA Workshop on Field Programmable Gate Arrays ACM, pp. 1-11 (Feb. 1994).Applicant
- D. Jones, et al., “A Time-Multiplexed FPGA Architecture for Logic-Emulation,” Proceedings of the IEEE 1995 Custom Integrated Circuits Conference, pp. 495-498 (May 1995).Applicant
- G. Nutt, “Microprocessor Implementation of a Parallel Processor,” Proceedings of the Fourth Annual Symposium on Computer Architecture, pp. 147-152 (1977).Applicant
- W. Kim, “MasPar MP-2 PE Chip: A Totally Cool Hot Chip,” Proceedings of Hot Chips V, pp. 1-5 (Mar. 29, 1993).Applicant
- E. Mirsky, et al., “Matrix: Coarse-Grain Reconfigurable Computing (Abstract)”, Published at the 5th Annual MIT Student Workshop on Scalable Computing, pp. 1-2 (Aug. 1995) (Available on the Internet May 1, 1995).Applicant
- E. Mirsky, et al., “Matrix: A Reconfigurable Computing Architecture with Configurable Instruction Distribution and Deployable Resources,” Published at FCCM'96—IEEE Symposium on FPGA's for Custom Computing Machines, pp. 1-10 (Apr. 17-19, 1996).Applicant
- Takashi Miyamori et al., “A Quantitive Analysis of Reconfigurable Coprocessors for Multimedia Applications,” IEEE Symposium on Field-Programmable Custom Computing Machines Conference (FCCM98), Apr. 15-17, 1998.Applicant
- Charlé Rupp et al., “The Napa Adaptive Processing Architecture” IEEE Symposium on Field-Programmable Custom Computing Machines Conference (FCCM98), Apr. 15-17, 1998, pp. 1-10.Applicant
- Stephen M. Scalera et al., “The Design and Implementation of a Context Switching FPGA”, IEEE Symposium on Field-Programmable Custom Computing Machines Conference (FCCM98), Apr. 15-17, 1998.Applicant