Fabrication method for a dual damascene structure

[0002] This application claims the priority benefit of Taiwan application serial no. 89100399, filed Jan. 12, 2000.

[0003] 1. Field of Invention

[0004] The present invention relates to a fabrication method for a multilevel metal interconnects in a semiconductor device. More particularly, the present invention relates to a fabrication method for a dual damascene structure.

[0005] 2. Description of Related Art

[0006] In the development of the semiconductor industry, a goal of a high operational speed for electronic devices is actively pursued by all semiconductor manufacturers and customers. The factors such as the resistance of conductive lines and the formation of parasitic capacitance caused by unnecessary capacitive coupling between the adjacent conductive wires are decisive for the operational speed of devices. A metal with a low resistance for the decrease of resistance and a dielectric material with a low dielectric constant for the improvement of the issue of parasitic capacitance have been chosen for use in the manufacturing of semiconductor devices.

[0007] The typical metallic interconnect manufacturing process includes forming a metal plug in the dielectric layer. The second aluminum layer of the metal-interconnect structure is electrically connected to the base layer of metal-interconnect structure via the metal plug formed in the dielectric layer. The dual damascene technique includes a metallic interconnect technique with high reliability and low cost, and the metallic interconnect materials are protected from, etching. The dual damascene technique has been widely applied in the manufacturing of copper line to reduce the resistance of conductive lines, and further improve the operational speed and quality of an integrated circuit. In order to accommodate the demand for high operational speed, dielectric layers with a low dielectric constant have been employed in manufacturing dual damascene structures, which have gradually become the metallic interconnect technique in the semiconductor industry.

[0008] FIGS. 1A to 1E are schematic, cross-sectional views showing the dual damascene manufacturing process according to the prior art.

[0009] Referring to FIG. 1A, a dielectric layer 102 is formed on a substrate 100, followed by forming a silicon nitride layer 104 to cover the dielectric layer 102. A patterned photoresist 106 with a via opening pattern 108 is further formed to cover the silicon nitride layer 104.

[0010] Referring to FIG. 1B, the silicon nitride layer 104 is etched with the photoresist layer 106 serving as a mask to transfer the via opening pattern 108 of the photoresist layer 106 to the silicon nitride layer 104. Thus a via opening 110 is formed in the silicon nitride layer 104. Another inter-metal dielectric layer 112 is formed over the substrate 100 and then a patterned photoresist layer 114 with a trench line pattern 116 is formed over the inter-metal dielectric layer 112.

[0011] Referring to FIG. 1C, the portion of the inter-metal dielectric layer 112 uncovered by the patterned photoresist 114 is etched to form a trench line 120. After exposure of the portion of the silicon nitride layer 104 with a via opening 110, etching is further conducted on the exposed dielectric layer 102 under the via opening 110 to form a via 118 in the dielectric layer 102.

[0012] Continuing to FIG. 1D and FIG. 1E, the photoresist layer 114 is removed by ashing using O₂plasma. A metal layer 122 is formed on the substrate 100 and fills the trench 120 and the via 118. Portions of the metal layer 122 which are covering the surface of the dielectric layer 112 are removed by, for example, chemical mechanical polishing (CMP), leaving the metal layer 122 in the trench 120 and in the via 118. At this point, the manufacturing of a dual damascene structure is completed.

[0013] As the integration of the devices increases, the density of wires used to electrically couple the transistors or other devices is increased. The issues of parasitic capacitance between the adjacent conductive wires becomes serious. Therefore, at the stage of deep submicron manufacturing, the dielectric constant of the IMD layer is lowered to reduce the parasitic capacitance and therefore to decrease the resistance-capacitance (RC) time delay when electronic signals are being transmitted between the metal lines.

[0014] However, the photoresist layer usually contains polymer material while a dielectric material having a low dielectric constant, such as organic polymer, is commonly used. According to the above manufacturing process, during the process of removing the photoresist layer 114 by ashing using oxygen plasma, the organic dielectric material 112 and 102 with a low dielectric constant will be damaged by oxygen plasma. Therefore, moisture is adsorbed on the sidewalls of the trench line 120 and the via opening 118, respectively formed in the organic dielectric material 112 and 102 with a low dielectric constant. As shown in FIG. 1D, moisture is adsorbed on the sidewalls labeled 124 and 126. In the subsequent thermal process, the adsorbed moisture escapes from the sidewalls of the trench line 120 and the via 118, so that the performance when filling the via 118 and the trench 120 with the metal layer 122 is poor due to the adsorbed moisture, resulting in a poisoned via and trench effect.

[0015] In addition, according to the prior art, the trench line 120 and via 118 are formed by performing anisotropic etching with the silicon nitride layer 104 serving as an etch-stop layer and as an etching mask, respectively. However, the silicon nitride layer 104 has a dielectric constant of about 7. Effects, such as the increase of the RC delay time contributed by the generation of the parasitic capacitance between the adjacent conductive wires become serious. As a result, the operational speed of a highly integrated circuit is limited.

[0016] The present invention provides a fabrication method for a dual damascene structure that prevents dielectric material with a relatively low dielectric constant from suffering moisture adsorption during the process of removing a photoresist. Therefore, the poisoned via and trench effect can be avoided.

[0017] The present invention further provides a fabrication method for a dual damascene structure that decreases parasitic capacitance between the adjacent conductive wires to accelerate the operation speed of the IC device.

[0018] Accordingly, the present invention provides a fabrication method for a dual damascene structure. The substrate having a first organic dielectric layer with a low dielectric constant, a thermal diffusion layer and a second organic dielectric layer with a low dielectric constant formed thereon is provided. Thereafter, a first and a second etching mask layers with a trench line pattern and a via opening pattern, respectively, are sequentially formed on the substrate. The second organic dielectric layer with a low dielectric constant and the thermal diffusion layer are etched while using the second etching mask layer as a hard mask; then the via opening is formed in the thermal diffusion layer. Thereafter, the second etching mask layer is removed. While using the first etching mask layer and the thermal diffusion layer as hard masks, the second and the first organic dielectric layers with a low dielectric constant are further etched; then a via opening is formed in the first organic dielectric layer and a trench line is formed in the second organic dielectric layer. The via opening and the trench line are then filled with a conductive material and a chemical mechanical polishing process is subsequently performed to remove a portion of the conductive material to form a metal line and via.

[0019] As embodied and broadly described herein, the dual damascene structure is formed by using two patterned photoresist layers serving as mask layers to transfer two patterns onto the etching mask layers. The first etching mask layer possesses a trench line pattern and the second etching mask layer possesses a via opening pattern.

[0020] After the trench line pattern of the first photoresist layer is transferred to the first etching mask layer, the first photoresist layer with a trench line pattern is removed by ashing using oxygen plasma to expose the second organic dielectric layer with a low dielectric constant. During the oxygen plasma process, the surface of the second organic dielectric layer is damaged. However, the damaged portion of the surface is removed in the subsequent etching process to form the trench. Therefore, the process of removing the first photoresist layer does not substantially affect the result of a dual damascene structure.

[0021] Meanwhile, after the via opening pattern of the second photoresist layer is transferred to the second etching mask layer, the second photoresist layer is removed by ashing using oxygen plasma. The exposed surface of the second organic dielectric layer with a low dielectric constant is also damaged by the attack of oxygen plasma. However, the damaged portion of the surface is also removed in the subsequent etching process. In fact, the process of removing the second photoresist layer does not affect the result of a dual damascene structure.

[0022] According to the present invention, before the formation of the via opening and the trench line in the first and the second organic dielectric layer with a low dielectric constant, respectively, the damaged portion of the second organic dielectric layer is already removed in the subsequent etching process. After the formation of the via opening and the trench line in the first and the second organic dielectric layer, respectively, the step of removing the photoresist layer is not included in the manufacturing process. Therefore, the adsorption of the moisture in the sidewalls of the via opening and the trench line formed in the first organic dielectric layer and the second organic dielectric layer can be avoided. Hence, in the subsequent process of the deposition of the metal layer, the poisoned via and trench effect caused by the evaporation of the adsorbed moisture is avoided.

[0023] In addition, according to a preferred embodiment of the present invention, the material of the second etching mask layer is made of silicon nitride with a high dielectric constant, but the silicon nitride layer is removed by conducting the subsequent etching process. Hence, according to the present invention, the dual damascene structure does not comprise a silicon nitride layer. Furthermore, the silicon nitride layer of the prior art method is replaced with the thermal diffusion layer of aluminum nitride with a low dielectric constant and located between the two organic dielectric layers. Therefore, in the present invention, the parasitic capacitance between adjacent conductive wires is reduced and the performance of the devices is improved.

[0024] Meanwhile, the aluminum nitride layer possesses an excellent heat-dissipation characteristic so that the heat produced by the metal lines in the process of high operational speed in the integrated circuits can be dissipated; thus the reliability of devices can be improved.

[0025] It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.

[0026] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,

[0027] FIGS. 1A to 1E are schematic, cross-sectional views showing the dual damascene manufacturing process according to the prior art; and

[0028] FIGS. 2A to 2J are schematic, cross-sectional views showing the dual damascene manufacturing process according to one preferred embodiment of this invention.

[0029] FIGS. 2A to 2J are schematic, cross-sectional views showing the dual damascene manufacturing process according to one preferred embodiment of this invention.

[0030] Referring to FIG. 2A, a substrate 200 is provided with a dielectric layer 202, a thermal diffusion layer 204 and a dielectric layer 206 formed in sequence thereon. Preferably, the dielectric layers 202, 206 with a low dielectric constant comprise spin on organic polymers. The thickness of the dielectric layer 202 is preferably about 2000-5000 angstroms, and the thickness of the dielectric layer 206 is preferably about 2500-5000 angstroms. Preferably, the thermal diffusion layer 204 has excellent heat-dissipation characteristic and a low dielectric constant that is preferably less than 4. In addition, the etching rate of the thermal diffusion layer 204 is different from those of dielectric layers 202 and 206 with respect to a particular etchant. The thermal diffussion layer 204 is, for example, aluminum nitride and is formed by, for example, physical vapor deposition, with a thickness of about 500-2000 angstroms.

[0031] Referring to FIG. 2B, a mask layer 208 is formed on the dielectric layer 206. The etching rate of the mask layer 208 is different from those of the dielectric layers 202 and 206 with respect to a particular etchant. Preferably, the mask layer 208 is, for example, titanium nitride, and is formed by, for example, chemical vapor deposition or physical vapor deposition, with a thickness of about 500-2000 angstroms. The photoresist layer 210 with a trench line pattern 212 is formed on the mask layer 208 to define the mask layer 208.

[0032] Referring to FIG. 2C, a portion of the mask layer 208 uncovered by the photoresist layer 210 is etched while using the patterned photoresist layer 210 as a mask layer and the dielectric layer 206 as an etching stop layer. Then, a trench line 214 is formed in the mask layer 208 and a portion of the dielectric layer 206 is exposed. The photoresist layer 210 is then removed by, for example, ashing and wet etching.

[0033] Continuing with reference to FIG. 2C, the photoresist 210 is removed by ashing using oxygen plasma to expose the patterned mask layer 208. The exposed surface of the dielectric layer 206 under the trench line 214 is uncovered by the patterned mask layer 208, so that the surface of the exposed dielectric layer 206, labeled as 224, is easily damaged by the attack of oxygen plasma. However, the damaged surface 224 is removed by subsequent etching step, so that the formation of the dual damascene structure is not affected.

[0034] Referring to FIG. 2D, a mask layer 216 is formed on the substrate 200 to cover the exposed mask layer 208 and dielectric layer 206. The etching rate of the mask layer 216 is different from those of the dielectric layer 206 and the thermal diffusion layer 204. Preferably, the mask layer 216 is, for example, silicon nitride and is formed by, for example, chemical vapor deposition, with a thickness of about 500-2000 angstroms.

[0035] Then, a photoresist layer 218 with a via opening pattern 220 is formed on the substrate 200 to expose a portion of the mask layer 216 covering the trench line 214.

[0036] Referring to FIG. 2E, using the photoresist layer 218 with a via opening pattern 220 as an etching mask, the exposed mask layer 216 not covered by the photoresist layer 218 is removed by, for example, reactive ion etching to transfer the via opening pattern 220 to the mask layer 216. Therefore, an opening 222 is formed in the mask layer 216, and the patterned photoresist layer 218 is then removed by ashing using oxygen plasma.

[0037] In the same way, the exposed surface of the dielectric layer 206 uncovered by the patterned mask layer 216, labeled as 236, is damaged by the attack of oxygen plasma. However, the damaged surface 236 of dielectric layer 206 is removed by the subsequent etching step, so that the formation of dual damascene structure is not affected.

[0038] Referring to FIG. 2F, with the mask layer 216 serving as a hard mask, anisotropic etching, for example, reactive ion etching is sequentially conducted on the exposed dielectric layer 206 and the thermal diffusion layer 204. The opening 222 pattern is transferred to the dielectric layer 206 and the thermal diffusion layer 204, and a via opening 226 is formed in the thermal diffusion layer 204 and the dielectric layer 206. Furthermore, the damaged surface 236 of dielectric layer 206 is removed by the etching step.

[0039] Referring to FIG. 2G, after removing the mask layer 216, a trench line 214 is formed in the mask layer 208, and a via opening 226 is formed in the dielectric layer 206 and the thermal diffusion layer 204, concurrently. Then, a model of an opening of a dual damascene structure is reached.

[0040] Referring to FIG. 2H, with the mask layer 208 serving as a hard mask and the thermal diffusion layer 204 serving as a hard mask and etching stop layer, anisotropic etching, for example, reactive ion etching is conducted on the portion of the dielectric layer 206 uncovered by mask layer 208 and the portion of the dielectric layer 202 uncovered by thermal diffusion layer 204. Then, the trench line pattern 214 in the mask layer 208 is transferred to the dielectric layer 206 to form a trench line 228 in the dielectric layer 206. A via opening pattern 226 in the dielectric layer 206 and thermal diffusion layer 204 is transferred to the dielectric layer 202 to form a via opening 230 in the dielectric layer 202.

[0041] Briefly, the above method includes only one etching process. The trench line pattern 214 in the mask layer 208 and the via opening pattern 226 in the dielectric layer 206 and the thermal diffusion layer 204 are concurrently duplicated into the dielectric layer 206 and the dielectric layer 202, respectively, to form the trench line 228 and the via opening 230 of dual damascene structure.

[0042] According to the above etching process, the exposed surface of the dielectric layer 206 is damaged during the removal of photoresist layer 210, but the damaged portion of surface 224 is removed by the reactive ion etching. However, the sidewalls of the via opening 230 in the dielectric layer 202 and the trench line 228 in the dielectric layer 206 are not damaged by the attack of oxygen plasma.

[0043] Referring to FIG. 2I, a barrier layer 232 is formed over the substrate 200 to cover the surface of the mask layer 208, the trench 228, and the via opening 230. The barrier layer 232 comprises, for example, titanium nitride, tantalum nitride or the same type of materials and is formed by, for example, chemical vapor deposition. Thereafter, the metal layer 234 is formed on the substrate 200, covering the barrier layer 232 and filling the via opening 230 and the trench line 228. The metal layer 234 is, for example, copper and is formed by, for example, chemical vapor deposition or physical vapor deposition.

[0044] Continuing to FIG. 2J, the dielectric layer 206 serving as a polishing stop layer, the metal layer 234, the barrier layer 232 and the mask layer 208 above the dielectric layer 206 are removed by, for example, chemical mechanical polishing, leaving the metal layer 234aand the barrier layer 232ain the trench line 228 and via opening 230. After that, the process for manufacturing the dual damascene structure is completed.

[0045] The present invention provides a fabrication method for a dual damascene. The trench line pattern and the via opening pattern are transferred by using two photoresist layers 210 and 218 in the photolithography process. The titanium nitride layer 208 with the trench line pattern 214 and the silicon nitride layer 216 with the via opening pattern 222 serving as mask layers.

[0046] The trench line pattern 212 on the photoresist layer 210 is transferred to the titanium nitride mask layer 208, and then the photoresist layer 210 is removed using oxygen plasma to expose the dielectric layer 206 with a low dielectric constant. The exposed surface of the dielectric layer 206 can be damaged by the attack of oxygen plasma, but the damaged surface 224 is removed by the subsequent etching process, and a trench line 228 is formed. Therefore, the dual damascene structure is not changed during the process of removing the photoresist layer 210.

[0047] Meanwhile, the via opening pattern 220 of the second photoresist layer 218 is transferred to the silicon nitride mask layer 216. The second photoresist layer 218 is removed using oxygen plasma to expose the portion of the surface of the organic dielectric layer 206 with a low dielectric constant. The exposed surface of the second dielectric layer 206 can be damaged by the attack of oxygen plasma, but the damaged surface 236 is removed by the subsequent etching process. In fact, the dual damascene structure is not changed during the process of removing the second photoresist layer 218.

[0048] According to the present invention, before the formation of the via opening 230 and the trench line 228 in the first organic dielectric layer 202 and the second organic dielectric layer 206 with a low dielectric constant, respectively, the damaged portions 224, 236 of the second organic dielectric layer are already removed in the subsequent etching process. After the formation of the via opening 230 and the trench line 228 in the first organic dielectric layer 202 and the second organic dielectric layer 206, respectively, the step of removing the photoresist layer is not included in the manufacturing process. Therefore, the adsorption of the moisture by the sidewalls of the via opening 230 and the trench line 228 formed in the first organic dielectric layer 202 and the second organic dielectric layer 206 can be avoided. Hence, in the subsequent process of the deposition of the metal layer 234, the poisoned via and trench effect caused by the evaporation of the adsorbed moisture is avoided.

[0049] In addition, according to the present invention, the material of the second etching mask layer 216 is made of silicon nitride with a high dielectric constant, but the silicon nitride layer 216 is removed by conducting the subsequent etching process. Hence, according to the present invention, the dual damascene structure does not comprise a silicon nitride layer. Furthermore, the silicon nitride layer of the prior art method is replaced with the thermal diffusion layer of aluminum nitride with a low dielectric constant and located between the two organic dielectric layers. Therefore, in the present invention, the parasitic capacitance between adjacent conductive wires is reduced and the performance of the devices is improved.

[0050] Meanwhile, the aluminum nitride layer possesses an excellent heat-dissipation characteristic so that the heat produced by the metal lines due to the high operational speed processing of the integrated circuits can be dissipated, thus the reliability of devices can be improved.

[0051] Accordingly, the invention includes the following advantages:

[0052] 1. According to the present invention, the poisoned via and trench effect can be avoided.

[0053] 2. According to the present invention, the parasitic capacitance between the adjacent conductive lines is reduced and the performance ability of the devices is improved.

[0054] 3. According to the present invention, the heat produced by the metal lines due to the high operational speed processing of the integrated circuits can be dissipated; thus the reliability of devices can be improved.

[0055] It will be apparent to those skilled in the art that various modifications and variations can be made to the structure of the present invention without departing from the scope or spirit of the invention. In view of the foregoing, it is intended that the present invention cover modifications and variations of this invention provided they fall within the scope of the following claims and their equivalents.