Method of forming metal interconnect structures and metal via structures using photolithographic and electroplating or electro-less plating procedures

[0002] (1) Field of the Invention

[0003] The present invention relates to methods used to fabricate semiconductor devices, and more specifically to methods used to create metal interconnect structures, and metal via structures, for semiconductor devices.

[0004] (2) Description of Prior Art

[0005] The semiconductor industry is continually striving to improve the performance of semiconductor devices, while still attempting to decrease the processing costs of semiconductor chips. These objectives have been successfully addressed via micro-miniaturization, or the ability to fabricate semiconductor devices, comprised with sub-micron features. The sub-micron features allow performance degrading capacitances to be reduced. In addition the use of sub-micron features, allow smaller semiconductor chips to be obtained, however still possessing the same, or greater, device densities, as counterparts fabricated using larger features. This results in the attainment of more semiconductor chips, from a specific size, starting substrate, thus reducing the processing cost of the sub-micron, semiconductor chip.

[0006] The success of micro-miniaturization can be attributed to advances in specific semiconductor fabrication disciplines such as photolithography and dry etching. The use of more sophisticated exposure cameras, as well as the use of more sensitive photoresist materials, have allowed sub-micron images in photoresist layers, to be routinely achieved. In addition the development of more advanced dry etching tools and processes, have allowed the sub-micron images, in masking photoresist layers, to be successfully transferred to underlying materials, used to fabricate semiconductor devices. However in addition to the contributions of advanced semiconductor disciplines, specific processing procedures, such as damascene, and dual damascene patterning, have been used to create, high aspect ratio, metal interconnect, and metal via structures, comprised with sub-micron features. However the damascene procedures, entailing forming the damascene, or dual damascene pattern, in. an insulator layer, followed by metal deposition, in the damascene opening, requires the use of “glue”, or adhesive layers, permanently located, underlying the metal structures, formed in the damascene opening. The “glue” or adhesive layer, now part of the metal structure, increases the resistance of the metal structure, for a specific cross-sectional area.

[0007] This invention will teach semiconductor procedures needed to create high aspect ratio, metal interconnect structures, and metal via structures, using electro-plating, or electro-less plating, metal procedures, thus avoiding the need for “glue” or adhesive layers, used with the conventional metal filling of damascene openings. The metal interconnect, and metal via structures, formed via use of this invention, will use a disposable conductive layer, or seed layer, thus not adversely influencing the conductivity of the resulting metal structure. Prior art, such as Brighton et al, in U.S. Pat. No. 4,866,008, describe the formation of metal structures, via electroplating procedures, however the final metal structures include the underlying seed layers, which adversely influence the ability to obtain the desired conductivity, for the metal structures.

[0008] It is object of this invention to fabricate metal interconnect structures, and metal via structures, via the opening of a desired metal structure shape, in a photoresist layer, followed by formation of the desired metal pattern, via a metal electroplating, or electro-less plating procedure, in the opening in the photoresist layer.

[0009] It is another object of this invention to deposit a disposable conductive layer, followed by formation of a defining, overlying shape, such as a photoresist, an organic, or a dielectric shape, exposing a portion of the disposable conductive layer, in the opening in the overlying shape.

[0010] It is still another object of this invention to electroplate, or electro-less plate, the desired metal pattern, in the opening in the photoresist shape, using the portion of disposable conductive layer, located under the defining shape, as a seed layer.

[0011] It is still yet another object of this invention to remove the portion of disposable conductive layer, not covered by the desired metal pattern, after removal of the overlying defining shape.

[0012] In accordance with the present invention a method of fabricating metal interconnect structures, and metal via structures, for semiconductor devices, using metal plating procedures, featuring underlying, disposable conductive layers, has been developed. A first disposable conductive layer is formed on an underlying, first metal via structure, followed by the formation of a first defining shape, comprised of an organic material, such as a photoresist, or comprised of a dielectric layer, featuring an opening, which exposes the top surface of the first metal via structure. A metal interconnect structure is formed on the portion of the first disposable conductive layer, exposed in the opening, in the first defining shape, via an electroplating, or electro-less plating procedure. After removal of the first defining shape, and removal of the portion of first disposable conductive layer, not covered by the metal interconnect structure, a dielectric layer is deposited, and planarized, exposing the top surface of the metal interconnect structure. After deposition of a second disposable conductive layer, overlying the exposed top surface of the metal interconnect structure, as well as overlying the planarized top surface of the dielectric layer, a second defining shape, comprised of either photoresist, other organic materials, or a dielectric, is formed, featuring an opening that exposes a region of the second disposable conductive layer, that directly overlays a portion of the top surface of the metal interconnect structure. A second metal via structure, or metal pillar structure, is formed on the portion of the second. disposable conductive layer, exposed in the opening in the second defining shape, via electroplating, or electro-less plating, procedures. After removal of the second defining shape, the portion of the second disposable conductive layer, not covered by the second metal via structure, is removed.

[0013] The object and other advantages of this invention are described in the preferred embodiment with reference to the attached drawings that include:

[0014] FIGS. 1, 2, 3, 4, 5, 6B, and 6C, which schematically, in cross-sectional style, show the key stages of fabrication used to create metal interconnect structures, and metal via structures, via the use of electroplating procedures, featuring underlying, disposable conductive layers.

[0015] FIG. 6A, which schematically shows a top view of the metal interconnect structure, and the metal via structure, obtained via the electroplating procedures.

[0016] A method used to fabricate metal interconnect structures, and metal via structures, using electroplating and electro-less plating procedures, performed in openings in defining shapes, such as photoresist shapes, and featuring disposable conductive layers, used to enhance the plating procedures, will now be describe in detail.

[0017] FIG. 1, shows a first metal via structure 2, in a first dielectric layer 1. First dielectric layer 1, can be comprised of silicon oxide, or boro-phosphosilicate glass, (BPSG), while first metal via structure 2, can be comprised of either copper, tungsten, tungsten silicide, or aluminum, or an aluminum based layer, such as aluminum-copper. First metal via structure 2, overlays and contacts, either an active device region in an underlying semiconductor substrate, (not shown in the drawings), or an underlying metal interconnect structure, (not shown in the drawings). First dielectric layer 1, in which a contact hole, or a via hole, would be formed in, to accept first metal via structure 2, would be formed on either the semiconductor substrate, or the underlying metal interconnect structure. A first disposable conductive layer 3, is formed on a planarized top surface, comprised of the top surface of first dielectric layer 1, and the top surface of first metal via structure 2. First disposable conductive layer 3, is comprised of either titanium, titanium nitride, tantalum nitride, or copper on tantalum nitride, obtained via R.F. sputtering procedures, at a thickness between about 500 to 1000 Angstroms. The conductive layer will serve as a seed layer for deposition of a subsequent electroplated, metal layer. A first defining shape 4, which can be comprised of photoresist, silicon oxide, silicon nitride, or other low dielectric constant organic, or inorganic materials, is next formed on first disposable conductive layer 3, with opening 15, exposing a first portion of first disposable conductive layer 3, in a region in which first disposable conductive layer 3, directly overlays the top surface of first metal via structure 2. In this description the defining shapes, will be comprised of photoresist. This is schematically shown in FIG. 1. The disposable conductive layers used in this invention, provide the seed layer needed to perform the subsequent electroplated and electro-less plated procedures, used to create the desired metal interconnect, and metal plug structures.

[0018] A metal interconnect structure 5, shown schematically in FIG. 2, is next formed in opening 15, via an electroplated, or via an electro-less plated, procedure. Metal interconnect structure 5, comprised of copper, at a thickness between about 2000 to 10000 Angstroms, can be obtained via an electroplating procedure, accomplished at a temperature between about 20 to 40° C., at a current density, between about 0.01 to 0.05 amps/cm², using a CuSO₄based solution. Metal interconnect structure 5, shown schematically in FIG. 2, is shown as a copper structure, however if desired, metal interconnect structure 5, can be comprised of nickel, obtained via an electroplating procedure, using a solution of NiSO₄, NiCl₂, and H₃BO₃, based at a temperature between about 40 to 70° C., at a current density between about 0.01 to 0.05 amps/cm², or using an electro-less plating procedure, using a solution of NiCl₂and (CH₃)₂NHBH₃, at a temperature between about 60 to 70° C.

[0019] After removal of photoresist shape 4, via plasma oxygen ashing and careful wet cleans, the portion of first disposable conductive layer 3, not covered by metal interconnect structure 5, is selectively removed, via a RIE procedures, using Cl₂or BCl₃as an etchant. A second dielectric layer 6, comprised of silicon oxide, or of polyimide, is next deposited to a thickness between about 5000 to 15000 Angstroms, completely covering metal interconnect structure 5. The silicon oxide option, for second dielectric layer 6, is obtained via a plasma enhanced chemical vapor deposition, (PECVD), procedure, while the polyimide option, for second dielectric layer 6, is obtained via spin on coating, and curing procedures. This is schematically shown in FIG. 3.

[0020] A chemical mechanical polishing procedure, is next employed to planarize the top surface of second dielectric layer 6, to create a smooth top surface, as well as to expose the top surface of metal interconnect structure 5. A second disposable conductive layer 7, is next formed on the smooth top surface of second dielectric layer 6, also overlying, and contacting, the top surface of metal interconnect structure 5. Second disposable conductive layer 7, shown schematically in FIG. 4, is again comprised of a titanium layer, obtained at a thickness between about 500 to 1000 Angstroms, via R.F. sputtering procedures.

[0021] A second defining shape 8, such as a photoresist shape, a silicon oxide, or silicon nitride shape, or a low dielectric constant, organic, or inorganic material, shape, is next formed on second disposable conductive layer 7, featuring opening 19, which exposes a first portion of second disposable conductive layer 7, in a region in which second disposable conductive layer 7, overlays a portion of metal interconnect structure 5. This is schematically shown in FIG. 5.

[0022] A metal via structure, or metal pillar structure 10, is next formed on the portion of second disposable conductive layer 7, exposed in opening 19, via electroplating, or electro-less plating, procedures, overlying and contacting a portion of the top surface of metal interconnect structure 5. Metal via structure, or metal pillar structure 10, is again comprised of copper, at a thickness between about 5000 to 15000 Angstroms, and formed using the identical electroplating, or electro-less plating conditions, previously used to form metal interconnect structure 5. The bottom of second disposable conductive layer 7, exposed at the perimeter of opening 19, provides the seed layer needed for the electroplated, or electro-less plated procedure. After removal of defining, or photoresist shape 8, via plasma oxygen ashing and careful wet cleans, the portion of the second disposable conductive layer 7, not covered by metal via structure 10, is selectively removed from the top surface of second dielectric layer 6, using conditions identical to the conditions previously used to selectively remove the desired portions of first disposable conductive layer 3, from the top surface of first dielectric layer 1. This is schematically shown, in cross-sectional style, for one direction, in FIG. 6B, and shown schematically, for a second direction, in FIG. 6C. FIG. 6A, schematically shows a top view of a configuration comprised of metal pillar structure 10,—metal interconnect structure 5—metal via structure 2, formed via electroplating, or electro-less plating procedures, accomplished using disposable conductive layers, as seed layers.

[0023] While this invention has been particularly shown and described with reference to, the preferred embodiments thereof, it will be understood by those skilled in the art that various changes in form and details may be made without departing from the spirit and scope of this invention.