Method and apparatus for mapping bits to an information burst

[0002] This application claims priority under 35 U.S.C. 119 to United States Provisional Application Ser. No. 60/136,977, filed Jun. 1, 1999 and entitled “Improved EGPRS Burst Mapping With Bit Skipping” the disclosure of which is hereby expressly incorporated herein by reference.

[0003] The present invention relates generally to digital communication systems and, more particularly, to a method and apparatus for mapping bits to an information burst in a digital wireless communication system.

[0004] In digital communication systems, information, such as data or voice, is carried in an encoded form on a communication channel. In a time division multiplexing (TDM) communication system the communication channel is a time slot or frame into which a burst of encoded information is inserted. In addition to the information being communicated, the burst will also necessarily include additional encoded information, such as header information, control information, synchronization, training or optimization information, and the like, as is well known in the art. On the receiving end, the information burst is decoded to recover the communicated information. If the information is not decoded correctly, errors occur. The rate at which errors occur in the decoded information is referred to as the bit error rate (BER). A related measure of decoded information reliability is the block error rate (BLER) of a group of information bits, where a block error is defined as one or more bit errors within the group of information bits. Reducing the BER or BLER enhances system performance by, for example, increasing the amount of data that may be communicated or, for voice communications, enhancing the perceived quality of the voice communication.

[0005] In an equalized communication system that transmits bursts of information over a time varying channel, where a burst consists of one or more known sequences of training symbols (encoded and modulated information used for optimizing the equalizer) and unknown data and header symbols (i.e., encoded and modulated information), the channel BER profile is generally a function of the coded symbol position. For example, the channel BER of Enhanced Data Rates for GSM Evolution (EDGE) Enhanced General Packet Radio System (EGPRS) is higher at the beginning and the end of the information burst than near the middle of the information burst where the training symbols are located. Furthermore, the BER of every third bit is roughly twice the BER of the first and second bits. This “symbol asymmetry,” due to the bit-to-symbol mapping scheme for Gray-coded 8-PSK (phase shift keying) used in EGPRS, occurs for many constellations and bit-to-symbol mappings.

[0006] The header symbols (throughout the term “header” is used to refer to a variety of header and control information including, without limitation stealing bits, coded USF (uplink status flag), coded RLC/MAC (Reliable Link Layer/Medium Access Control) header information, and the like) typically carry crucial information. Errors within the data symbols may result in slightly decreased data rates or slightly degraded voice quality. Errors in the header symbols can result in a loss of the entire information burst, which can result in significantly decreased data rates or significantly decreased voice quality. Therefore, communication of the header symbols should be made as reliable as possible.

[0007] One method for minimizing the decoded BER of the header symbols includes placing the header symbols adjacent to the training sequence. This method results in minimizing the interleaver gain while maximizing the effect of the BER profile as described above. Another method includes interleaving the data and header together. This method results in maximizing the interleaver gain while minimizing the effect of the BER profile. Neither method is superior for all channel conditions, and each method may cause a significant degradation to the data decoded BER.

[0008] Thus, there is a need for a method and apparatus for mapping symbols to an information burst that minimizes header decoded BER over many channel conditions without degrading data decoded BER.

[0009] FIG. 1 is a block diagram representation of a communication system in accordance with a preferred embodiment of the invention.

[0010] FIG. 2 is a functional block diagram representation of bit mapping apparatus in accordance with a preferred embodiment of the invention.

[0011] FIG. 3 is a bit-to-symbol map for 8-PSK modulation including Gray code mapping.

[0012] FIG. 4 is a graph illustrating bit error rate relative to symbol position for the 8-PSK modulation scheme illustrated in FIG. 3.

[0013] FIG. 5 is a graph illustrating average block error rate versus signal-to-noise ratio.

[0014] FIG. 6 is a bit-to-symbol map for 16-QAM modulation including Gray code mapping.

[0015] FIG. 7 is a diagram illustrating an initial bit mapping to an information burst in accordance with a preferred embodiment of the invention.

[0016] FIG. 8 is a diagram illustrating bit swapping subsequent to the bit mapping illustrated in FIG. 7.

[0017] FIG. 9 is a diagram illustrating an initial bit mapping to a burst in accordance with an alternate preferred embodiment of the invention.

[0018] FIG. 10 is a diagram illustrating bit swapping subsequent to the bit mapping illustrated in FIG. 9.

[0019] FIG. 11 is a diagram illustrating an initial bit mapping to a burst in accordance with an alternate preferred embodiment of the invention.

[0020] FIG. 12 is a diagram illustrating bit swapping subsequent to the bit mapping illustrated in FIG. 11.

[0021] The invention exploits the position-dependant property of the bit error rate (BER), caused by proximity to the training symbols and symbol asymmetry, to greatly improve the reliability of fields that carry preferred information, e.g., header symbols/bits while minimally impacting the decoded data BER. The header bits are first mapped to an information burst in close proximity to a training sequence. The remaining information to be communicated, e.g., data bits, is then mapped to the information burst. Header bits mapped to bit locations having a high probability of incurring a bit error are relocated to bit locations occupied by data bits having a low probability of incurring a bit error. The displaced data bits are relocated to bit locations previously occupied by the header bits.

[0022] In a method according to a preferred embodiment of the invention a first group of bits, e.g., header symbols/bits, are interleaved to form a first group of interleaved bits. A second group of bits, e.g., data symbols/bits, are interleaved to form a second group of interleaved bits. The first and second groups of interleaved bits are mapped to an information burst. The first and second groups of interleaved bits may be mapped to the information burst relative to a group of known symbols forming a training sequence. A disadvantaged bit location, i.e., a bit location within the mapping having a relative high probability of incurring a bit error, is identified and an advantaged bit location, i.e., a bit location within the mapping having a relatively low probability of incurring a bit error, is identified. A first group bit from the first group of interleaved bits mapped to the disadvantaged bit location is remapped to the advantaged bit location while a second group bit from the second group of interleaved bits mapped to the advantaged bit location is remapped to the disadvantaged bit location.

[0023] In another preferred embodiment of the invention, the disadvantaged bit location and the advantaged bit location within the mapping are known a priori and the first group bit is mapped to the advantaged bit location and the second group bit is mapped to the disadvantaged bit location.

[0024] In an alternate preferred embodiment of the invention, the bit locations of the first group bit and the second group bit are swapped after mapping of the first group of interleaved bits and the second group of interleaved bits to the information burst.

[0025] An apparatus according to a preferred embodiment of the invention includes operatively coupled an interleaver, a bit mapper and a bit swapper. The interleaver separately interleaves the header bits and data bits to provide interleaved header bits and interleaved data bits. Alternatively, the interleaver may interleave the header bits together with the data bits. The bit mapper maps the interleaved header bits and interleaved data bits to an information burst relative to a training sequence. The bit swapper then moves header bits from bit locations having a relatively high probability of incurring a bit error to bit locations, occupied by data bits, having a relatively low probability of incurring a bit error. The bit swapper then locates the displaced data bits to the bit locations formerly occupied by the displaced header bits.

[0026] Referring to FIG. 1 of the drawings, a digital communication network 10 includes a radio access network 12 including a base station 14 and a base station controller 16. The radio access network 12 is coupled to a switch fabric 18, which may be a circuit switch network or a packet data network. The base station 14 provides wireless communication services to mobile stations 20 operating within a coverage area of the base station 14. Preferably the base station 14 operates in accordance with one or more wireless communication standards, including without limitation the Enhanced General Packet Radio System (EGPRS) specified in the Global System for Mobile Communications (GSM) standard. In this regard, the base station 14 may further implement Enhanced Data Rates for GSM Evolution (EDGE) protocols. It will be appreciated by one of ordinary skill in the art; however, that the present invention has application to virtually any communication system type that transmits bursts of information over a time-varying channel.

[0027] Within the base station 14 are channel codec units (CCU) 22 that are coupled to a packet control unit (PCU) 24. The PCU 24 is coupled to the base station controller 16, and hence to the remainder of the communication network 10. While shown as part of the base station 14, the PCU 24 may be associated with the base station controller 16 or with another entity of the communication network 10. Moreover, while two CCUs are shown, it will be appreciated the number of CCUs within the base station 14 will depend on the desired capacity of the base station 14. The PCU 24 provides control of the communication of data packets to and from the base station 14, as well as other functionality as described for EPGRS.

[0028] Each CCU 22 operates to demodulate and decode uplink signals received from a mobile station 20 and to encode and modulate downlink signals for transmission to the mobile station 20. The CCU 22 further operates to provide the inventive method described herein. While the invention will be described in terms of a downlink encoding and modulation process, and will be particularly described in terms of the EGPRS downlink Modulation Coding Scheme (MCS)-5 to MCS-9, the invention is easily extended to the EGPRS uplink, other MCSs or other communication systems, as will be appreciated by one having ordinary skill in the art.

[0029] Referring to FIG. 2, the functional elements of CCU 22 are illustrated in block diagram form. These functional elements are preferably implemented in computer code operated on by a processing unit within the CCU 22. Of course, the particular implementation, either by way of computer code or otherwise, is not critical to the invention, and any suitable implementation may be employed without departing from the fair scope of the invention. As shown in FIG. 2, a first interleaver 30 receives a stream of header bits 32 that are to be mapped to an information burst. A second interleaver 34 receives a stream of data bits 36 that are also to be mapped to the information burst. The output of the interleaver 30 and the interleaver 34 are interleaved header bits 38 and interleaved data bits 40, respectively. A bit mapper 42 maps the interleaved header bits 38 and the interleaved data bits 40 to the information burst, and relative to a training sequence of the information burst. Finally, a bit swapper 44 provides for swapping of certain bits, predominantly header bits, from bit locations having a relatively high probability of incurring bit errors with data bits in bit locations having a relatively low probability of incurring bit errors. The result is a bit mapped information burst 46, with improved header information reliability without significant data degradation.

[0030] While described as separate functional entities, it will be appreciated that the functionality of the interleaver 30 and the interleaver 34 may be combined into a single functional interleaver element. Moreover, this single element further may embody the functionality of the bit mapper 42. In such an embodiment of the invention, the header bits 32 and the data bits 36 may be interleaved and directly mapped to the information burst by this single functional element. Still further, and well within the scope of the invention, all of the above described functional elements, header interleaver 30, data interleaver 34, bit mapper 42 and bit swapper 44 may be combined such that the header bits 32 and the data bits 36 are directly sequenced to the information burst, with swapping of disadvantaged bit locations for advantaged bit locations for the header bits 32 accomplished during such mapping. Various other combinations and sub-combinations of the above-described functional elements may be envisioned, and such combinations would be well within the scope of the present invention.

[0031] Referring to FIG. 3 and FIG. 4 it is possible to understand how the invention achieves the foregoing result. FIG. 3 illustrates a bit-to-symbol mapping for 8-PSK (phase shift keying) modulation. This particular mapping is Gray coded, with the leftmost bit in the symbol labeled bit 0, and the rightmost bit in the symbol labeled bit 2. The horizontal axis 50 illustrates the bit 0 decision line, the vertical axis 52 illustrates the bit 1 decision line and the 45 degree axes 54 and 56 illustrate the second bit decision lines. The probability of error of bit i in a symbol can be approximated as a function of the distance from the symbol to the closest bit i decision line. The approximation can be justified for many communication channels where the most likely symbol errors are closest to the correct symbol. Looking at symbol 1, it can be observed that there is a potential for a bit error due to selecting adjacent symbol 2 or symbol 8 in either bit 0 or bit 2. From symbol 2, it can be observed that there is a potential for a bit error due to selecting adjacent symbol I or symbol 3 in either bit 1 or bit 2. Continuing for each symbol Table 1 may be constructed, where an “X” indicates a potential for an error at the i-th bit of a symbol. As is evident from Table 1, there is a potential for error in bit 2 for every symbol, and one would expect to see increased probability of errors in bit 2. FIG. 4 bears this out, where traces 58 and 60 illustrate the block error rate by mapping position to the information burst for bit 0 and bit 1, while trace 62 illustrates the block error rate by mapping position to the information burst for bit 2. As can be seen, the block error rate for every mapping position of bit 2 is substantially higher than the block error rate for either bit 0 or bit 1. FIG. 4 further illustrates that for mapping positions nearer to the training sequence (positioned centrally in the mapping and indicated as 64), the block error rate declines. Thus, the interleaved header bits 38 are mapped in close proximity to the training sequence 64. Next, header bits that were mapped to locations corresponding to bit 2, a disadvantaged bit location, are swapped with data bits mapped to bit locations corresponding to bit 0 or bit 1, advantaged bit locations. In this manner, the decoded header BLER is improved. Unexpectedly, the decoded data BLER is not significantly degraded. This is illustrated in FIG. 5.

[0032] This “symbol asymmetry” is also present for other bit-to-symbol mappings for 8-PSK, and for other constellations such as 16-QAM. A bit-to-symbol mapping for 16-QAM is shown in FIG. 6. The particular mapping is Gray coded with the left most bit of a symbol labeled as bit 0 and the right most bit of a symbol labeled as bit 3. Axis 80 represents the bit 0 decision line, axis 82 represents the bit 2 decision line, axes 84 and 86 each represent the bit I decision lines and axes 88 and 90 represent the bit 3 decision lines. From the mapping illustrated in FIG. 6, Table II, below, may be constructed illustrating the potential for an error in the i-th bit of a symbol. As is seen from Table II, the approximate probability of an error is half for bit 0 and bit 2 as compared to either bit 1 or bit 3. Thus, one of ordinary skill in the art will readily appreciate that by applying the principles of the present invention, the decoded header BER for a communication system utilizing 16-QAM may be improved.

[0033] Referring to FIG. 5, the traces 70 and 72 illustrate average BLER versus signal-to-noise ratio for separately interleaved header and data bits, respectively, without application of the present invention, and the traces 74 and 76 illustrate average BLER versus signal-to-noise ratio for separately interleaved header and data bits, respectively, applying the principles of the present invention. As can be seen by comparing traces 70 and 74, there is substantial improvement in BLER. Comparing traces 72 and 76, it can be further seen that the improvement in decoded header BLER is achieved without a significant change in decoded date BLER.

[0034] The present invention may be further illustrated by way of the following examples for the EGPRS downlink. The examples include data and header fields that are mapped over multiple bursts, with the header field consisting of multiple header subfields. Two of the header subfields are interleaved with an identity interleaver (i.e., not interleaved). Though not required, the examples place the header information into the advantaged positions substantially uniformly distributed on both sides and adjacent a single training sequence that is located within the middle of the burst. The header information need not be mapped uniformly with respect to the training sequence, nor does the training sequence need to reside centrally within the burst. Moreover, there may exist additional training sequences within the burst, and portions of the header information may be mapped with respect to each of these training sequences so as to take advantage of the reduced probability for bit errors resulting from the information being mapped near to the one or more training sequences. Additional fields other than data, header, and training are often found in TDM communication systems (guard, preamble, etc)—the examples include guard fields at the beginning and end of the burst. The following are examples of the application of the present invention to a TDM communication system, and as such, these examples should not be taken as limiting of the invention.

[0035] Referring to FIGS. 7 and 8, let h(i), i=0,1, . . . , 95 be coded RLC/MAC header bits 100, u(i), i=0,1, . . . , 35 be coded USF bits 102, d(i), i=0,1, . . . , 1255 be coded data bits 104, sb(i), i=0,1,2,3 be stealing bits 106, g(i), i=0,1, . . . n_g−1 be guard bits 110 and e(B,i), i=0,1, . . . , 347 be the bits in the B-th burst (B=0,1,2,3) of a block. The header 112 includes the header bits 100, USF bits 102 and stealing bits 106. The 3^rdbit locations, or disadvantaged bit locations within the header 112 are known a priori and are designated with an “X.” In accordance with a preferred embodiment of the invention, the bits are mapped to an information burst 114 as follows:

[0036] Step 1: Interleave RLC/MAC Header

[0037] The coded RLC/MAC header is interleaved (scrambled) using any interleaving algorithm. For example, for i=0,1, . . . , 95, let ĥ(j)=h(i), where $j=24\times \left(i\mathrm{mod}4\right)+2\times \left(\left(5\lfloor \frac{i}{8}\rfloor \right)\mathrm{mod}12\right)+\lfloor \frac{i\mathrm{mod}8}{4}\rfloor$

[0038] Step 2: Interleave RLC Data

[0039] The RLC data is interleaved (scrambled) using any interleaving algorithm. For example, for i=0,1, . . . , 1255, let {circumflex over (d)}(j)=d(i), where $j=314\times \left(i\mathrm{mod}4\right)+2\times \left(\left(49i\right)\mathrm{mod}157\right)+\lfloor \frac{i\mathrm{mod}8}{4}\rfloor$

[0040] Step 3: Straightforward Mapping (FIG. 7)

[0041] For B=0,1,2,3, let $e\left(B,i\right)=\{\begin{array}{cc}\hat{d}\left(314B+i\right),& \mathrm{for}i=0,1,\dots ,156\\ \hat{h}\left(24B+i-157\right),& \mathrm{for}i=157,158,\dots ,168\\ u\left(9B+i-169\right),& \mathrm{for}i=169,170,171,172,173\\ \mathrm{sb}\left(B\right),& \mathrm{for}i=174\\ u\left(9B+i-170\right),& \mathrm{for}i=175,176,177,178\\ \hat{h}\left(24B+i-167\right),& \mathrm{for}i=179,180,\dots ,190\\ \hat{d}\left(314B+i-34\right),& \mathrm{for}i=191,192,\dots ,347\end{array}$

[0042] Note that the important bits 112 (stealing bits, coded USF, and coded RLC/MAC header) are mapped close to a training sequence 116. Mapping is illustrated for a single burst of the n possible bursts, where each additional burst is substantially similar.

[0043] Step 4: Bit Swapping (FIG. 8)

[0044] For B=0,1,2,3,

[0045] Swap e(B, 148) with e(B, 158);

[0046] Swap e(B, 150) with e(B, 161);

[0047] Swap e(B, 151) with e(B, 164);

[0048] Swap e(B, 153) with e(B, 167);

[0049] Swap e(B, 154) with e(B, 170);

[0050] Swap e(B, 156) with e(B, 173);

[0051] Swap e(B, 176) with e(B, 192);

[0052] Swap e(B, 179) with e(B, 193);

[0053] Swap e(B, 182) with e(B, 195);

[0054] Swap e(B, 185) with e(B, 196);

[0055] Swap e(B, 188) with e(B, 198).

[0056] Note that after this step is performed, none of the coded header and USF bits occupy the disadvantaged third bit “X”.

[0057] Referring to FIGS. 9 and 10, let h(i), i=0,1, . . . , 99 be coded RLC/MAC header bits 120, u(i), i=0,1, . . . , 35 be coded USF bits 122, d(i), i=0,1, . . . , 1247 be coded data bits 124, sb(i), i=0,1, . . . , 7 be stealing bits 126, g(i), i=0,1, . . . n_g−1 be guard bits 130 and e(B,i), i=0,1, . . . , 347 be the bits in the B-th burst (B=0,1,2,3) of a block. The header 132 includes the header bits 120, USF bits 122 and stealing bits 126. The 3^rdbit locations, or disadvantaged bit locations within the header 132 are known a priori and are designated with an “X.” In accordance with a preferred embodiment of the invention, the bits are mapped to an information burst 134 as follows:

[0058] Step 1: Interleave RLC/MAC Header

[0059] The coded RLC/MAC header is interleaved (scrambled) using any interleaving algorithm. For example, for i=0,1, . . . , 99, let ĥ(j)=h(i), where j=25(i mod 4)+((17i) mod 25)

[0060] Step 2: Interleave RLC Data

[0061] The RLC data is interleaved (scrambled) using any interleaving algorithm. For example, for i=0,1, . . . , 1247, let {circumflex over (d)}(j)=d(i), according to an explicit relation given in a table. The table may be constructed by defining a block interleaver with a 1392 bit block size (data plus header), removing data positions that will be mapped to header positions (Step 3 below), and renumbering to fill out the gaps without changing the relative order.

[0062] Step 3: Straightforward Mapping (FIG. 9)

[0063] For B=0,1,2,3, let $e\left(B,i\right)=\{\begin{array}{cc}\hat{d}\left(312B+i\right),& \mathrm{for}i=0,1,\dots ,155\\ \hat{h}\left(25B+i-156\right),& \mathrm{for}i=156,157,\dots ,167\\ u\left(9B+i-168\right),& \mathrm{for}i=168,169,173\\ \mathrm{sb}\left(2B+i-174\right),& \mathrm{for}i=174,175\\ u\left(9B+i-170\right),& \mathrm{for}i=176,177,178\\ \hat{h}\left(25B+i-167\right),& \mathrm{for}i=179,180,\dots ,191\\ \hat{d}\left(312B+i-36\right),& \mathrm{for}i=192,193,\dots ,347\end{array}$

[0064] Note that the important bits 132 (stealing bits, coded USF, and coded RLC/MAC header) are mapped close to a training sequence 136. Mapping is illustrated for a single burst of the n possible bursts, where each additional burst is substantially similar.

[0065] Step 4: Bit Swapping (FIG. 10)

[0066] For B=0,1,2,3,

[0067] Swap e(B, 142) with e(B, 155);

[0068] Swap e(B, 144) with e(B, 158);

[0069] Swap e(B, 145) with e(B, 161);

[0070] Swap e(B, 147) with e(B, 164);

[0071] Swap e(B, 148) with e(B, 167);

[0072] Swap e(B, 150) with e(B, 170);

[0073] Swap e(B, 151) with e(B, 173);

[0074] Swap e(B, 176) with e(B, 195);

[0075] Swap e(B, 179) with e(B, 196);

[0076] Swap e(B, 182) with e(B, 198);

[0077] Swap e(B, 185) with e(B, 199);

[0078] Swap e(B, 188) with e(B, 201);

[0079] Swap e(B, 191) with e(B, 202);

[0080] Swap e(B, 194) with e(B, 204).

[0081] Note that after this step is performed, none of the coded header and USF bits occupy the disadvantaged third bit “X”.

[0082] Referring to FIGS. 11 and 12, let h(i), i=0,1, . . . , 127 be the coded RLC/MAC header bits 200, u(i), i=0,1, . . . , 35 be the coded USF bits 202, d(i), i=0,1, . . . , 1223 be the coded data bits 204, sb(i), i=0,1,2,3 be the stealing bits 206, g(i), i=0,1, . . . n_g−1 be guard bits 210 and e(B,i), i=0,1, . . . , 347 be the bits in the B-th burst (B=0,1,2,3) of a block. The header 212 includes the header bits 200, USF bits 202 and stealing bits 206. The 3^rdbit locations, or disadvantaged bit locations within the header 212 are known a priori and are designated with an “X.” In accordance with a preferred embodiment of the invention, the bits are mapped to an information burst 214 as follows:

[0083] Step 1: Interleave RLC/MAC Header

[0084] The coded RLC/MAC header is interleaved (scrambled) using any interleaving algorithm. For example, for i=0,1, . . . , 127, let ĥ(j)=h(i), where $j=11\times \left(i\mathrm{mod}12\right)+\lfloor \frac{i}{12}\rfloor .$

[0085] Step 2: Interleave RLC Data

[0086] The RLC data is interleaved (scrambled) using any interleaving algorithm. For example, for i=0,1, . . . , 1223, let {circumflex over (d)}(j)=d(i), where $j=\{\begin{array}{cc}306\times \left(i\mathrm{mod}4\right)+2\times \left(\left(49i\right)\mathrm{mod}153\right)+\lfloor \frac{i\mathrm{mod}8}{4}\rfloor & \mathrm{for}\mathrm{MCS}-7\\ 306\times \left(2\lfloor \frac{i}{612}\rfloor +\left(i\mathrm{mod}2\right)\right)+2\times (\left(49i\right)\mathrm{mod}153+\lfloor \frac{i\mathrm{mod}8}{4}\rfloor & \mathrm{for}\mathrm{MCS}-8\mathrm{and}\mathrm{MCS}-9\end{array}$

[0087] Step 3: Straightforward Mapping (FIG. 11)

[0088] For B=0,1,2,3, let $e\left(B,i\right)=\{\begin{array}{cc}\hat{d}\left(306B+i\right),& \mathrm{for}i=0,1,\dots ,152\\ \hat{h}\left(32B+i-153\right),& \mathrm{for}i=153,154,\dots ,168\\ u\left(9B+i-169\right),& \mathrm{for}i=169,170,171,172,173\\ \mathrm{sb}\left(B\right),& \mathrm{for}i=174\\ u\left(9B+i-170\right),& \mathrm{for}i=175,176,177,178\\ \hat{h}\left(32B+i-163\right),& \mathrm{for}i=179,180,\dots ,194\\ \hat{d}\left(306B+i-42\right),& \mathrm{for}i=195,196,\dots ,347\end{array}$

[0089] Note that the important bits 212 (stealing bits, coded USF, and coded RLC/MAC header) are mapped close to a training sequence 216. Mapping is illustrated for a single burst of the n possible bursts, where each additional burst is substantially similar.

[0090] Step 4: Bit swapping (FIG. 12)

[0091] For B=0,1,2,3,

[0092] Swap e(B, 142) with e(B, 155);

[0093] Swap e(B, 144) with e(B, 158);

[0094] Swap e(B, 145) with e(B, 161);

[0095] Swap e(B, 147) with e(B, 164);

[0096] Swap e(B, 148) with e(B, 167);

[0097] Swap e(B, 150) with e(B, 170);

[0098] Swap e(B, 151) with e(B, 173);

[0099] Swap e(B, 176) with e(B, 195);

[0100] Swap e(B, 179) with e(B, 196);

[0101] Swap e(B, 182) with e(B, 198);

[0102] Swap e(B, 185) with e(B, 199);

[0103] Swap e(B, 188) with e(B, 201);

[0104] Swap e(B, 191) with e(B, 202);

[0105] Swap e(B, 194) with e(B, 204).

[0106] Note that after this step is performed, none of the coded header and USF bits occupy the disadvantaged third bit “X”.

[0107] The present invention has been described and illustrated in terms of several preferred embodiments, several alternate preferred embodiments and several examples. It will be appreciated that invention may be otherwise embodiment than as described herein without departing from the fair scope of the present invention. The described embodiments and examples are intended only to be illustrative of the invention, and not limiting thereof, the full and fair scope of invention being set forth in the subjoined claims.