Brokaw transconductance operational transconductance amplifier-based micropower low drop out voltage regulator having counterphase compensation

[0002] The present invention is generally related to voltage regulator circuits, and more particularly low quiescent current regulators.

[0003] The “dropout voltage” of a voltage regulator equals the minimum input-to-output voltage differential for which the circuit can maintain output regulation. Low-dropout (LDO) voltage regulators generally have dropout voltages of a few tenths of a volt at full rated current. In order to achieve such low dropout voltages, the circuit must use a PNP or PMOS pass element. FIG. 1 shows a simplified block diagram of a typical prior art PMOS LDO circuit 10. The pass element is MOS transistor M₁, which is driven by amplifier A₁. The amplifier in turn receives the voltage generated by an internal voltage reference VR₁, and the voltage produced by a voltage divider network R₁-R₂. The circuit 10 is connected so that the amplifier achieves equilibrium when the voltage on the tap T of the voltage divider equals the voltage generated by the reference VR₁.

[0004] Many LDO applications require that the regulator consume little current to power its internal circuitry. This quiescent current typically equals 100 μA for a modern PMOS LDO, and this changes little regardless of output current. The conventional topology of FIG. 1 can be extended to provide low-current operation, typically down to 10 μA. Lower currents require nonconventional circuit topologies.

[0005] The micropower LDO architecture contains multiple poles at relatively low frequencies, and therefore requires the insertion of compensating zeros to boost the phase, or otherwise the phase margin will deteriorate to the point that the circuit becomes unstable. These zeros are difficult to generate using integrated components because they must lie at relatively low frequencies (10-100 kHz), they must not use large amounts of die area, and they must not consume any current. There are two basic techniques that have been used to insert zeros in this type of LDO architecture:

[0006] 1) Placing a resistor Resr in series with the load capacitor C_Lproducing a zero at w=1/(R_esr×C_L). This can't make a low-frequency pole for a small capacitor value unless a large resistor R_esris used, which is undesirable. Since micropower architectures have low bandwidth, they require low-frequency poles and this isn't a good solution—by itself.

[0007] 2) Place a capacitor C (not shown) across the upper resistor R₁of the feedback divider; this produces a zero at w=1/(R₁×C). This doesn't work well for small divider ratios because the pole-zero separation becomes too small.

[0008] FIG. 1 is a schematic diagram of a prior art low-dropout (LDO) voltage regulator based on a Brokaw transconductance cell;

[0009] FIG. 2 is a schematic diagram of a Brokaw transconductance cell having a lower quiescent current by merging the amplifier and the voltage reference blocks into a single circuit with a minimum number of current limbs; and

[0010] FIG. 3 is a schematic diagram of the present invention including a Brokaw transconductance cell having a base current compensation resistor and a capacitor producing a zero frequency, the capacitor effecting only the two transistors of the Brokaw cell.

[0011] The present invention achieves technical advantages as a micropower low-dropout voltage regulator having a shunt capacitor at the counterphase input of a Brokaw transconductance cell including a base current compensation resistor.

[0012] This resistor and capacitor provides a zero frequency that does not depend upon the attenuation ratio of the feedback divider. The counterphase compensation capacitor provides a low-frequency zero using a reasonably sized capacitor, providing a pole-zero separation that does not depend upon the attenuator ratio, and which requires no additional current-consuming components. The present invention can be combined with both feedback bypass compensation and ESR compensation to provide a wide-range phase boost capable of compensating a micropower LDO based upon the Brokaw transconductance cell. The configuration can be generally applied to any amplifier based on the Brokaw cell.

[0013] According to the preferred embodiment of the present invention, a voltage regulator produces an output signal and has a Brokaw cell comprising a first transistor and a second transistor. A compensation circuit is coupled to the Brokaw cell and generates a pole-zero pair in the Brokaw cell. Each of the first and second transistors have a base, wherein the compensation circuit comprises a base-current compensating resistor coupled between the first and second transistor bases. The compensation circuit also comprises a capacitor coupled to the compensating resistor.

[0014] The first and second transistors operate in counterphase to generate respective output signals 180° out-of-phase to one another. The compensation circuit is configured to provide a phase boost approaching 90° and which is independent of the output signal of the voltage regulator. The compensation circuit is configured to compensate the voltage regulator even when the regulator has a low feedback attenuation ratio.

[0015] The pole-zero pair defines a pole-zero separation, wherein the pole-zero separation is independent of attenuation ratio of the voltage regulator. The compensation circuit can be combined with a feedback bypass compensation circuit and an ESR compensation circuit to provide a wide-range phase boost. Preferably, the Brokaw cell is configured as an operational transconductance amplifier (OTA).

[0016] One approach to reducing quiescent current consists of merging the amplifier and voltage reference blocks into a single circuit with a minimum number of current limbs. A class of operational transconductance amplifier (OTA) circuits based on the Brokaw transconductance cell fulfill this goal. FIG. 2 shows the basic topology of such a circuit 20. The Brokaw transconductance cell consists of bipolar transistors Q₁and Q₂and resistors R₃and R₄, shown at 22. The emitter area of transistor Q₁is an integer multiple N of the emitter area of transistor Q₂. At equilibrium, where I_C1=I_C2, the voltage imposed across resistor R₃equals:

[0017] V_R3=V_T1n(N)

[0018] where V_Tis the thermal voltage. The currents through transistors Q₁and Q₂are both imposed across R₄, so the voltage seen at the input of the Brokaw cell, V_bg, equals: $V_{\mathrm{bg}}=V_{\mathrm{be2}}+2V_T\frac{\mathrm{R4}}{\mathrm{R3}}\ln \left(N\right)$

[0019] This is the classic bandgap equation derived by Brokaw. If the input voltage to the cell is less than the equilibrium value V_bg, then I_C1>I_C2; if the input voltage is greater than V_bg, then I_C1<I_C2. The OTA architecture feeds the currents I_C1and I_C2into mirrors CM₁and CM₂, and then uses another mirror CM₃to invert the output of CM₁. Since CM₃operates against CM₂, the current into or out of node V_pequals I_C2−I_C1, and this current equals zero only when the circuit rests at equilibrium. Any disturbance from equilibrium causes a current I_C2−I_C1that seeks to restore equilibrium.

[0020] The OTA described above acts both as its own reference and as an amplifier, so it replaces components VR₁and A₁in FIG. 1. FIG. 2 shows how a complete LDO could be implemented around the OTA. This circuit has a very small number of current paths (five in all, four in the OTA and one in the resistor divider R₃and R₄), making it a candidate for a micropower LDO.

[0021] Referring now to the present invention comprising circuit 30 in FIG. 3, circuit 30 shows a practical implementation of a micropower LDO. Current mirrors CM₁and CM₂have been implemented as PNP transistors Q₃-Q₄and transistors Q₅-Q₆. Current mirror CM₃has been implemented as NPN transistors Q₉-Q₁₀with a MOS beta helper transistor M₂biased by diode-connected transistor Q₁₂. In order to prevent excessive current flow when transistor Q₁₀saturates, a current limiting component I₁(typically a depletion-mode MOS transistor) has been inserted above the beta helper.

[0022] In order to minimize the impedance at node V_p, it is traditional to insert a follower stage, in this case consisting of emitter follower transistor Q₈biased by a limb of the lower current mirror based on transistor Q₁₁. In order to obtain adequate headroom for transistor Q₈, transistor M₁must have a high threshold voltage (V_t>1 V). This arrangement doesn't necessarily reduce the impedance at node V_pas much as desired because the output impedance of transistor Q₈depends inversely upon its emitter current, and low currents therefore prevent one from taking full advantage of transistor Q₈. However, this stage is still necessary in order to allow proper implementation of a startup circuit, as will be explained below.

[0023] Because the Brokaw transconductance cell transistors Q₁-Q₂-R₃-R₄has a very low transconductance, the OTA must have a relatively high output impedance. This is achieved in part by adding a cascode transistor M₃to the output limb of the lower current mirror CM₃. This transistor can be biased from beta helper transistor M₁due to the addition of diode transistor Q₁₂, which ensures that the current through transistors M₁and M₂have a definite relationship to one another (as would not be the case if this diode were omitted). A cascode on transistor Q₆could provide a higher output impedance, but only at the price of degrading the already-minimal headroom of transistor Q₈. FIG. 3 shows a better solution, consisting of a backside-cascode transistor Q₇which holds the collector of transistor Q₄at virtually the same voltage as the collector of transistor Q₆, thus eliminating most of the output voltage variations that low gain would otherwise produce.

[0024] As with most Brokaw-derived amplifiers, the OTA circuit 30 of FIG. 3 has a secondary equilibrium point at zero bias. In order to perturb the circuit and ensure startup, a small current source I₂has been added which pulls down on the gate of transistor M₁to begin start-up. In practice, I₂could be a depletion-mode transistor. In order to prevent this current from disturbing the OTA, an isolation stage must be inserted between the output of the OTA and node V_p; in this circuit emitter follower transistor Q₈performs this function. Transistor M₄has been added to balance the limbs of mirror CM₃, but is not absolutely necessary.

[0025] Compensating the Micropower LDO

[0026] LDO voltage regulators are notoriously difficult to compensate. The typical LDO (FIG. 1) is dominated by two poles: a load pole formed by the load capacitance C_L, and a gate pole formed by the gate capacitance of transistor M₁looking into the output impedance of amplifier A₁. In micropower LDO circuits, the extremely low currents used in the amplifier cause it to exhibit a very high output impedance. Consider the case of the amplifier of FIG. 3, which uses an emitter-follower output stage biased at a current I₀, giving an output impedance of: $R_o=\frac{V_T}{I_o}$

[0027] which for a typical bias current I₀of 0.5 μA gives an output impedance of 52 kΩ. The gate pole frequency f_gdepends upon the gate capacitance C_gand equals: $\mathrm{fg}=\frac{1}{2\pi R_o{C}_g}$

[0028] assuming a typical gate capacitance of 100 pF, the gate pole falls at 31 kHz. The load pole falls at a frequency f_L: $f_L=\frac{1}{2\pi R_L{C}_L}$

[0029] This pole can move through a wide range of frequencies, depending upon the load resistance R_L. Typically, the stability becomes poorest for the lowest R_L(in other words, at the highest currents). Under these conditions, f_Lmoves out to a higher frequency and approaches (or even exceeds) the frequency of the gate pole. For example, for R_L=3Ω, C_L=1 μF; f_L=53 kHz. Given that f_gand f_Lappear at nearly the same frequency, this system is virtually guaranteed to become unstable and to oscillate in the 30-50 kHz band.

[0030] There are only two fundamental approaches to achieving stability: 1) push out the gate pole, and 2) insert zeros into the transfer function (lead compensation). Pushing out the gate pole to higher frequencies implies a reduction in the output impedance of amplifier A₁, which cannot be achieved without consuming larger currents or using smaller output transistors. This approach is therefore impractical in a micropower LDO, and some form of lead compensation must be used.

[0031] The two classical techniques of generating lead compensation in LDO's are the insertion of an ESR zero and the insertion of a feedback bypass capacitor. The ESR zero capacitor appears in FIG. 1 as R_esr. This resistor generates a zero by operating against load capacitor C_L, and the resulting ESR zero appears at a frequency f_esr: $f_{\mathrm{esr}}=\frac{1}{2\pi R_{\mathrm{esr}}{C}_L}$

[0032] Classically, stability is achieved by pushing out the gate pole at least a decade from the load pole, and by then dropping the ESR zero onto the gate pole to achieve a pseudo-one-pole system. This cannot be done in micropower LDO's because the gate pole lies at too low a frequency, and the ESR zero cannot reach these low frequencies with practical values of ESR resistance. Most users object to more than 0.5Ω of ESR, and in combination with a 1 μF load capacitor, the ESR can only reach down to about 300 kHz, which is far above the 31 kHz of the gate pole in the sample system discussed above.

[0033] The feedback bypass capacitor has better possibilities in micropower circuits. This capacitor appears in the circuit 30 of FIG. 3 as capacitor C₁. Assuming the input impedance of the amplifier is “large”, the transfer function V₀/V_iacross the feedback divider is: $H=\frac{R_2}{\left(R_1+R_2\right)}\frac{1+{\mathrm{SC}}_1{R}_1}{1+{\mathrm{SC}}_1\frac{R_1{R}_2}{R_1+R_2}}$

[0034] which provides a compensation zero at f_z: $f_z=\frac{1}{2\pi C_1{R}_1}$

[0035] Given a typical value of R₁of 1 MΩ, a 5 pF compensation capacitor would produce a zero at 32 kHz, which is exactly the frequency of the gate pole discussed above. Unfortunately, this compensation technique has a limitation that becomes increasingly severe for lower-voltage regulators. The feedback bypass capacitor actually produces a lead-lag network, with a pole f_pat: $f_p=\frac{R_1+R_2}{2\pi C_1{R}_1{R}_2}$

[0036] The presence of this pole limits the range over which the zero can provide a phase boost, and therefore the magnitude of the phase boost. In practice, the pole-zero separation f_p/f_zshould equal at least 3-5 to obtain good results from this circuit. The ratio f_p/f_zequals: $\frac{f_p}{f_z}=\frac{R_1+R_2}{R_2}$

[0037] The output voltage V_oof the regulator is related to the Brokaw bandgap voltage V_bgby the formula: $V_o=V_{\mathrm{bg}}\frac{R_1+R_2}{R_2}$

[0038] where V_bg=1.25 V or thereabouts for minimum temperature variation. This implies that the pole zero separation f_p/f_zequals: $\frac{f_p}{f_z}=0.8V_o$

[0039] This implies that the feedback bypass capacitor doesn't provide much benefit for output voltages below 3 V. Unfortunately, it is precisely these voltages that are of greatest importance in modem low-voltage applications. Therefore, the feedback bypass capacitor provides limited benefit. Many low-voltage LDO's still include feedback bypass capacitors because they neutralize the inevitable parasitic poles introduced by parasitic capacitance within the feedback divider.

[0040] Classical LDO designs generally combined ESR compensation with feedback bypass compensation. Such designs provided adequate performance so long as the output capacitor value and quiescent current remained relatively large. These conditions no longer universally apply.

[0041] Counterphase Compensation

[0042] According to the present invention, compensation of Brokaw transconductance cell arises from the inclusion of the Brokaw base-current compensating resistor R₅. This resistor cancels the error in output voltage caused by the base currents of transistors Q₁and Q₂flowing through divider R₁-R₂, providing that the value of R₅equals: $R_5=\frac{R_3}{R_4}\frac{R_1{R}_2}{R_1+R_2}$

[0043] The present invention derives technical advantages by adding a capacitor C₂that generates a pole-zero pair in the Brokaw transconductance cell. This can be explained intuitively as follows:

[0044] The current at the base of transistor Q₈equals IC₂−IC₁, so transistors Q₁and transistor Q₂operate in counterphase. In other words, an input to transistor Q₁will produce an output signal at node V_p180° out-of-phase to the output signal generated in response to an input to transistor Q₂. Since a capacitor from the base of transistor Q₂to ground would behave as a pole (90° phase lag), a capacitor from the base of transistor Q₁to ground should produce a zero (90° phase lead). Resistor R₅plays a vital role because it provides isolation between transistors Q₁and Q₂and allows the capacitor C₂to affect only one of the two transistors Q₁and Q₂. One would intuitively expect the zero to depend upon resistors R₃and R₄, since these lie in the ground path from capacitor C₂, and one would expect to find a pole dependent upon resistor R₅.

[0045] An analysis of the OTA transfer function with the addition of C₂reveals the following pole and zero frequencies: $f_p=\frac{1}{2\pi R_5{C}_2}$ $f_z=\frac{R_3}{2\pi R_5\left(r_e+R_3+2R_4\right)C_2}$

[0046] where r_eis the emitter resistance (V_T/I_C) of one of the Brokaw transistors Q₁-Q₂. Since resistors R₃and r_eare both considerably smaller than 2R₄, the zero frequency can be approximated as: $f_z\cong \frac{R_3}{4\pi R_5{R}_4{C}_2}$

[0047] and the pole-zero separation f_p/f_zequals: $\frac{f_p}{f_z}\cong \frac{2R_4}{R_3}$

[0048] One important conclusion can be immediately drawn from the above equation: to a first-order approximation, the pole-zero separation does not depend on R₁, R₂or R₅. In practice, the ratio R₄/R₃is forced to about six by the requirement that the Brokaw cell produce a bandgap voltage V_bg≈1.25 V, the value required for temperature independence. This implies a pole-zero separation of about 12, providing a phase boost approaching 90° which is independent of the output voltage of the LDO. This is an extremely important result, as it shows that the counterphase compensation has a quality lacking in feedback bypass compensation, namely, the ability to compensate low-voltage regulators that have low attenuation ratios. The frequency of the zero actually depends upon R₁and R₂, as can be seen by substituting equation of R₅above into the equation for f_zabove: $f_z=\frac{R_1+R_2}{4\pi R_1{R}_2{C}_2}$

[0049] The zero frequency does not depend upon the attenuator ratio, but does depend upon the parallel combination resistance R₁∥R₂, which approaches R₁for low attenuator ratios. Even so, the value of C₂can still be boosted to provide the necessary zero. A typical micropower regulator might have a parallel resistance R₁∥R₂=1 MΩ, and a 5 pF compensation capacitor C₂would provide a zero at 16 kHz.

[0050] In summary, the counterphase compensation capacitor provides a low-frequency zero using a reasonably sized capacitor C₂, whose pole-zero separation does not depend upon attenuator ratio, and therefore is independent of output voltage, and which requires no additional current-consuming components. This technique can be combined with both feedback bypass compensation and ESR compensation to provide a wide-range phase boost capable of compensating a micropower LDO based upon the Brokaw transconductance cell. The illustrated circuit 30 uses an OTA configuration about the transconductance cell, but the technique is more general and can be applied to any amplifier based on the Brokaw cell.

[0051] Though the invention has been described with respect to a specific preferred embodiment, many variations and modifications will become apparent to those skilled in the art upon reading the present application. It is therefore the intention that the appended claims be interpreted as broadly as possible in view of the prior art to include all such variations and modifications.