Apparatus and method of encapsulated copper (Cu) Interconnect formation

[0002] The present invention relates to integrated circuits and fabrication techniques for forming interconnect structure. More particularly, the present invention relates to integrated circuits and fabrication techniques for forming interconnect structure out of copper. Even more particularly, the present invention relates to integrated circuits and fabrication techniques for encapsulating interconnect structure that has been fabricated out of copper.

[0003] In semiconductor wafers utilizing multilayered circuits, damascene metal interconnect lines are used to conduct current through the layers using interconnect structure singularly termed a line and a via. A line is also sometimes referred to as a land and a via is sometimes also referred to as a feed-through hole. These interconnect structure were heretofore usually made of aluminum, but are increasingly being made of copper. Currently, semiconductor technology is moving away from the use of aluminum as the metal of choice in circuitry and toward the use of copper. This move toward the production of copper interconnect structure semiconductors is receiving intense research because copper conducts electricity with lower resistance than aluminum which results in increased microprocessor speed. Additionally, copper uses less power and costs less than aluminum. Also, the physical attributes of copper metal allow for space-saving circuitry design. A discussion of the move toward copper in semiconductor devices can be found in The Electron, “Smokin . . . Watch Out, Fast Computers are on the way Speed is now Pushing Computing Power,” by Andy Maslowski, April/May/June 1998, Vol. 25, No.2, pp. 1 and 20. The Electron is published at 4781 E. 355th St., Willoughby, Ohio 44094-4698.

[0004] A published article concerning the challenges to industry in making the move to copper interconnects in integrated circuits and a brief teaching of the fundamentals of copper electroplating is an article entitled “Tantalum, Copper, and Damascene: The Future of Interconnects” by Peter Singer, Semiconductor International, June 1998. The challenges have been accepted by industry, but have resulted in copper interconnect structures that need special encapsulating fabrication techniques to overcome the characteristic that copper diffuses into silicon and silicon dioxide and reacts with most metals and suicides such as Al, Ti, CoSi₂, NiSi, and TiSi₂, which are commonly used in microelectronic devices. See “Electroless CoWP Barrier/Protection Layer Deposition For Cu Metallization”, S. Lopatin et al., Material Research Society, 1997, pp. 463-468, “High Aspect Ratio Quarter-micron Electroless Copper Integrated Technology”, Yosi Shacham-Diamand et al., Microelectronic Engineering, 1997, pp. 77-88, and U.S. Pat. No. 5,695,810 to Dubin et al.

[0005] U.S. Pat. No. 5,695,810 teaches a technique of encapsulating copper circuit interconnect lines in a CoWP (cobalt-tungsten-phosphide) barrier including a capping step with the CoWP material. Other known fabrication techniques include single-Damascene process, or dual-Damascene process. In the single-Damascene process, either the interconnect lines, or the vias, are fabricated separately, while in the dual-Damascene process, both vias and interconnect lines are fabricated concurrently. The dual-Damascene fabrication process has the limitation of requiring high dielectric constant (i.e, high-k) layers that are used to overcome etch-uniformity problems that occur during trench etch fabrication steps. The dual-Damascene fabrication process also has the problem of maintaining adequate seed layer step coverage in designs involving a via or a trench structure whose cross-sectional area has a high aspect ratio (i.e., where the via or trench height to width ratio is at least 3:1). Further, dual-Damascene fabrication problems include concerns about via bottom opening to Cu and cleaning.

[0006] Thus, a primary object of the present invention is to provide an improved semiconductor device having copper interconnect structure that overcomes undesirable copper diffusion characteristic by using selective electroplated copper fabrication techniques.

[0007] A related object of the present invention is to provide an improved semiconductor device having copper interconnect structure that overcomes undesirable copper diffusion characteristic which is fabricated such that silicon nitride and silicon dioxide layers are not required.

[0008] Another related object of the present invention is to provide an improved semiconductor device having copper interconnect structure that overcomes undesirable copper diffusion characteristic and which is fabricated such that copper interconnect structure in the less that 0.25 μm range is facilitated.

[0009] Yet another related object of the present invention is to provide an improved semiconductor device having copper interconnect structure that overcomes undesirable copper diffusion characteristic and which is fabricated such that the copper interconnect structure formed by selective electroplated copper fabrication techniques is encapsulate in metal barriers.

[0010] Still another related object of the present invention is to provide an improved semiconductor device having copper interconnect structure that overcomes undesirable copper diffusion characteristic and which is fabricated such that the copper interconnect structure can be formed by with minimal concerns about seed layer step coverage.

[0011] Accordingly, and by example only, the foregoing objects are accomplished by providing a semiconductor device having copper interconnect structure fabricated by a process that comprises the steps of initially forming a blanket copper (Cu) layer formed by electroplating a Cu layer over a semiconductor device which has been previously fabricated to a stage having circuit elements in need of being electrically energized, and or, being electrically coupled to other circuit elements to perform an electronic function of the semiconductor device. By example, in formation of a copper via interconnect structure, a blanket of electroplated Cu layer structure is fabricated over a low dielectric constant material (referred to herein as low K1 material) such as poly(arylene ether) (“PAE”), fluorinated aromatic ether (“FLARE”), fluorinated polymide (“FPI”), benzocyclobutene (“BCB”), hydrogen silsesquioxane (“HSQ”), methyl silsesquioxane (“MSQ”), xerogel and fluorinated glass. The low K1 dielectric layer has previously undergone a photolithographic process and comprises at least one via for forming an interconnect structure. The via's sidewalls and the surface of the low K1 dielectric layer structure further comprise a metal barrier layer, such as tantalum (Ta), tantalum nitride (TaN) and tungsten nitride WN, fabricated such that the metal barrier covers the surface and extends into the via to form a sidewall liner structure. Using CU chemical vapor deposition and/or Cu electroplating techniques, a substantially thin (≦0.25 μm) blanket of copper is formed to cover the metal barrier surface and also fill the metal barrier-lined via structure. It should be emphasized that the filled via structure is also substantially thin (≦0.25 μm). A photoresist layer is then fabricated over the electroplated Cu layer and then by means of a photolithographic process, and by example only, a trench structure, is formed overlying the previously Cu-filled via structure. The trench structure is selectively Cu-electroplated such that it is substantially thicker than the previously Cu-filled via structure (>>0.25 μm) and bonds with the previously Cu-filled underlying via structure. After the photoresist is removed, an electropolishing step, or etching step removes the substantially thin blanket of copper formed on the metal barrier surface and shapes the bonded Cu-electroplated via-trench structure. The electropolishing step, or etching step, is further controlled to stop at the metal barrier on the surface of the low K1 material to assure that a metallic interface exists for the subsequent metallic capping step. In forming the metallic barrier cap and by controlling the electropolishing step, or etching step, the metal barrier on the surface of the low K1 material is removed, while regions of metal barrier that flare about the via structure are not removed. The metallic capping step comprises a selective electroless metal barrier deposition, preferably comprising CoWP (cobalt-tungsten-phosphide), over the bonded Cu-electroplated via-trench structure, and over to the edges of the portions of metal barrier liner material flaring from the via structure in the low K1 material. The bonded Cu-electroplated via-trench structure, termed the copper interconnect, is effectively encapsulated within the CoWP deposited metal barrier and the metallic barrier liner in the via structure. The encapsulated copper interconnect can be further processed to spin coat a low dielectric constant material layer (termed herein as low K2 material), using the same dielectric material that was used for the low K1 layer. The low K2 layer may then be further lithographically processed to form a via structure to provide further electrical interconnect means. The process of the present invention facilitates the use of low dielectric material which results in a semiconductor structure that is free of Si₃N₄or SiO₂, in the copper interconnect region and which comprises copper interconnect structure that overcomes undesirable copper diffusion characteristic.

[0012] Other features of the present invention are disclosed or apparent in the section entitled: “DETAILED DESCRIPTION OF THE INVENTION”

[0013] The features, characteristics, advantages, and the invention in general, will be better understood from the following detailed description of an illustrative embodiment when taken in conjunction with the accompanying drawings in which:

[0014] FIG. 1 is an enlarged cross-sectional view of the present invention (see also FIG. 3) showing a semiconductor circuit device fabricated having a metal barrier layer deposited over a low dielectric constant (low K) material layer and a substantially thin (≦0.25 μm) blanket of copper deposited over the metal barrier layer for forming an interconnect structure in accordance with the present invention.

[0015] FIG. 2 is an enlarged cross-sectional view of the present invention showing the semiconductor device of FIG. 1 further processed with a photoresist material having an overlying trench region selectively filled with a substantially thick (>>0.25 μm) amount of copper for forming an interconnect structure in accordance with the present invention.

[0016] FIG. 3 is an enlarged cross-sectional view of the present invention showing the semiconductor device of FIG. 2 further processed with the photoresist material and selected portions of the substantially thin layer of copper removed for delineating an elevated structure consisting of the substantially thicker (>>0.25 μm) amount of copper used to fill the trench region depicted in FIG. 2, in accordance with the present invention.

[0017] FIG. 4 is an enlarged cross-sectional view of the present invention showing the semiconductor device of FIG. 3 further processed by removing portions of the metal barrier layer, as depicted in FIG. 1, and deposition of a selective encapsulating metal barrier over the delineated elevated copper structure shown in FIG. 3, in accordance with the present invention.

[0018] FIG. 5 is an enlarged cross-sectional view of the present invention showing the semiconductor device of FIG. 4 further processed by spin coat formation of a low K dielectric layer formed about the encapsulated copper interconnect structure shown in FIG. 4, and overlying the first low K dielectric material layer, as depicted in FIG. 1, and having a via structure formed for forming additional interconnect structure.

[0019] Like numerals denote like parts throughout the several views.

[0020] FIG. 1 shows a semiconductor device 10 fabricated to a stage for having a composite copper interconnect structure (40, 53) fabricated by a process in accordance with the teaching of the present invention. More particularly, the semiconductor device has been previously fabricated to a stage having integrated circuit elements in need of being electrically energized, and or, being electrically coupled to other integrated circuit elements to perform an electronic function of the semiconductor device 10. The process of the present invention comprises forming a first insulating layer 20 over semiconductor substrate 10. First insulating layer 20 being formed and selected from a material group characterized as having a lower dielectric constant (low K1) than a dielectric constant of silicon dioxide (SiO₂) and silicon nitride (Si₃N₄). The preferred material group consisting material such as poly(arylene ether) (“PAE”), fluorinated aromatic ether (“FLARE”), fluorinated polymide (“FPI”), benzocyclobutene (“BCB”), hydrogen silsesquioxane (“HSQ”), methyl silsesquioxane (“MSQ”), and xerogel and fluorinated glass. The first insulating layer 20 has a first access means 21 formed to facilitate formation of an electrical interconnect path and accessing the underlying semiconductor device 10, said first access means having a walled structure which in a may be in the form of a via structure or a trench structure. As illustrated in FIG. 1, the access means 21 is preferably a via structure 21. FIG. 1 further shows a first metallic barrier 30 formed over first insulating layer 20. The first metallic barrier 30 comprises metal material such as tantalum (Ta), tantalum nitride (TaN) and tungsten nitride WN. First metallic barrier 30 being formed not only to blanket the upper surface 22 of first insulating layer 20, but also such that the metallic barrier material extends into and lines the walls of the via structure 21 with a metallic barrier measuring less than 25 nm in thickness. Via structure 21, by example has a diameters measuring less than 0.25 μm, and a depth dl that is substantially greater than 0.25 μm. These type of via structures are characterized as having a high aspect ratio and are known to present problems of via bottom opening and cleaning in prior art dual damascene processes. FIG. 1 further shows a first metal structure 40, 41 formed from a conductive metal material, which according to the present invention, comprises electroplating copper over planar regions of the metallic barrier 30 and within metallic barrier-lined via region 21. It should be emphasized that the filled via structure is also substantially thin (≦0.25 μm). The conductive metals contemplated by the present invention comprise metal, such as copper, which have undesirable diffusion characteristic and which need to be encapsulated to maintain the desirable conductive properties.

[0021] FIG. 2 shows a photoresist layer 50 having a thickness d2 (>>0.25 μm) that is substantially larger than d1. Photoresist layer 50 facilitates formation, by example, of a trench structure 51, formed over the previously metal filled via structure 40, or in accordance with the present invention, over the copper filled via structure 40. FIG. 2 further shows formation of a second metal structure 52 within trench structure 51. Metal structure 52, in accordance with the present invention, comprises selectively electroplating copper within trench structure 51. It should be appreciated that trench structure 51 comprises a second access means which could be formed as a via structure. Further, the trench structure 51 is selectively Cu-electroplated such that the copper is substantially thicker (>>0.25 μm) than the previously Cu-filled via structure and bonds at metal interface region 54, (see FIG. 4) with the previously Cu-filled underlying via structure 40.

[0022] FIG. 3 shows an enlarged cross-sectional view of the present invention showing the semiconductor device 10 of FIG. 2 further processed with the photoresist material 50 and selected portions of the second metal structure 52 removed. After the photoresist 50 is removed, an electropolishing step removes the substantially thin blanket of the first metal structure, or copper blanket portion 41 formed on metal barrier 30 to shape the bonded Cu-electroplated via-trench structure 53, 40. The electropolishing step is further controlled to stop at the metal barrier 30 on the surface 22 of the low K1 material 20 to assure that a metallic interface exists for the subsequent metallic capping, or encapsulating step. Essentially, by shaping second metal structure 52 and portions of first metal structure 40 delineates an elevated metal structure portion 53. Delineated elevated metal structure portion 53 being supported by exposed portions 61 of first metallic barrier 30. Elevated metal structure portion 53 and first metal structure portions 40 formed within via structure 21 form a composite metal interconnect structure 40, 53

[0023] As shown in FIG. 4 the metallic barrier 30 is selectively removed by controlling an electropolishing step down to the surface 22 of the low K1 material 20. As shown in FIG. 4, exposed metallic regions 61 of metallic barrier 30 flare about the metal-filled via structure 40 and are not removed. The metallic encapsulating step comprises forming a a second metallic barrier 60 over said composite metal interconnect structure 40, 53. The second metallic barrier being selective electroless metal barrier, preferably formed by deposition of CoWP (cobalt-tungsten-phosphide), over the composite metal interconnect structure 40, 53. Second metallic barrier 60 is formed to bond to the exposed metallic regions 61 flaring from the via structure 21 in the low K1 material 20. The composite metal interconnect structure 40, 53, in accordance with the present invention, comprise bonded Cu electroplated via-trench structure at region 54 and may be termed a copper interconnect structure. The first metallic barrier portion 30 and second metallic barrier 60 forms an encasement that effectively encapsulates the copper interconnect structure 40, 53.

[0024] As shown in FIG. 5, the encapsulated copper interconnect structure 40, 53 can be further processed to spin coat a low dielectric constant material layer 70 (termed herein as low K2 material), using the same dielectric material that was used for the low K1 layer. The low K2 layer may the be further lithographically processed to form a via structure 71 to provide further electrical interconnect means.

[0025] Accordingly, the process of the present invention facilitates the use of low dielectric material which results in a semiconductor structure that is free of Si₃N₄or SiO₂, in the copper interconnect region and which comprises copper interconnect structure that overcomes undesirable copper diffusion characteristic.

[0026] Other modifications, changes, and substitutions are intended in the foregoing disclosure and in some instances, some features of the invention can be employed without a corresponding use of other features. Accordingly, it is appropriate that the appended claims be construed broadly and in a manner consistent with the scope of the invention and not limited to the description of the preferred versions contained herein.