Nonvolatile semiconductor memory device and manufacturing process thereof

[0002] The entire disclosure of Japanese Patent Application No. Hei9-350738 filed on Dec. 19, 1997 including specification, claims, drawings and summary is incorporated herein by reference in its entirely.

[0003] 1. Field of the Invention

[0004] This invention relates to a nonvolatile semiconductor memory device, in particular to the forming of an electrode and a tunnel insulation film partially having a thin film portion.

[0005] 2. Prior Art

[0006] An EEPROM is conventionally known as a nonvolatile semiconductor device which can be switched between write and non-write states by transferring charges through a tunnel oxide film partially having a thin film portion. The manufacturing process for the EEPROM will be described in reference to FIG. 5.

[0007] As shown in FIG. 5A, N⁺ regions 5 and 7 are formed in a semiconductor substrate 2 using a resist (not shown).

[0008] Next, it is subjected to thermal oxidation and selective etching to form a tunnel window 13aas a thin film portion. After depositing a polysilicon layer over the entire surface by the CVD process, a resist is used to form a floating gate electrode 9 and a select gate 19 as shown in FIG. 5C. After forming an ONO film and a polysilicon layer over the entire surface, a resist is used to form an ONO film 14 and a control gate electrode 29 as shown in FIG. 6A. As shown in FIG. 6B, using the select gate electrode 19 and the control gate electrode 29 as masks, impurities are implanted into the substrate 2. As a result, sources 3 and 6, and a drain 4 of a memory transistor and a select transistor are formed in the semiconductor substrate 2.

[0009] The manufacturing process described above, however, has the following problems: First, since separate masks are used to form the N⁺ region 5, the tunnel window 13a,and the floating gate electrode 9, the size of a cell increases by the dimension for possible displacement of the masks. In other words, the conventional process cannot achieve minute dimensioning depending on the performance of the exposure device used.

[0010] If it is possible to reduce the size of the tunnel window 13a,minute dimensioning can be achieved without sacrificing the performance. The reason is as follows: If the size of the tunnel window 13acan be reduced, the floating gate electrode 9 can be made small while maintaining a coupling ratio. This makes it possible to reduce the cell size while maintaining a voltage applied to the tunnel oxide film relative to the voltage applied to the control gate electrode 29. In other words, the cell size can be made minute while maintaining writing speed and the like.

[0011] The object of the invention is to provide a nonvolatile semiconductor memory device and its manufacturing process capable of solving the above problem, reducing the effective dimensions of the tunnel window, and achieving minute dimensioning without sacrificing its performance.

[0012] The nonvolatile semiconductor memory device comprises a semiconductor substrate, a first region provided in the semiconductor substrate, a second region provided so as to form a region capable of creating an electric channel between the first region, and the region capable of forming the electric channel, the first insulation film having a thin film portion of a thickness smaller on the first region than on the region capbale of forming the electric channel a floating electrode provided over the first insulation film to store electric charges, the floating electrode having a conductive side wall located over the thin film portion, and a main part located in the vicinity of the thin film portion and a main part located in the vicinity of the thin film portion and above the region capable of forming the electric channel, a lower region formed between the side wall and the main part being electrically isolated by an isolation laver and an upper region formed between the side wall and the main part being electrically connected by a conductive connection part a second insulation film provided on the floating electrode, and a control electrode provided on the second insulation film.

[0013] A nonvolatile semiconductor memory device comprises a semiconductor substrate of a first conductive type region formed in the semiconductor substrate, a second conductive type region formed in the semiconductor substrate, a tunnel oxide film formed on the first conductive type region comprising having a thin film portion over the second conductive type region, and a floating electrode capable of switching between write and non-write states by transferring electric charges to and from the second conductive type region through the thin film portion, the floating electrode comprises a conductive side wall located over the thin film portion, and a main part located in the vicinity of the thin film portion and above part of the tunnel oxide film, a lower region formed between the conductive side wall and the main part being electrically isolated by an isolation layer and an upper region formed between the conductive side wall and the main part being electrically connected by a conductive connection part.

[0014] A process for manufacturing a nonvolatile semiconductor memory device capable of switching between write and non-write states by transferring electric charges between the floating electrode and the second conductive type region of the first conductive type substrate through the thin film portion of the tunnel oxide film, comprises the steps of forming a main part of the floating electrode for storing electric charges on the insulation film formed on the substrate, partially removing the insulation film around the side wall of the floating electrode using the floating electrode as a mask, forming the oxide film of a specified thickness on the substrate surface where the insulation film has been removed, thereby forming the tunnel oxide film having the thin film portion, forming the conductive side wall on the side wall of the main part and the thin film portion, and partially removing the insulation layer formed between the main part and the conductive side wall, thereby electrically connecting between the conductive side wall and the upper region of the main part.

[0015] The features, other objects, applications, and effects of the invention will become clearer in reference to the embodiments and appended drawings.

[0016] FIG. 1 is a cross-sectional view of an essential part of an EEPROM 1 of the invention.

[0017] FIGS. 2A through 2C show manufacturing steps of the EEPROM 1 of the invention.

[0018] FIGS. 3A through 3D show manufacturing steps of the EEPROM 1 of the invention.

[0019] FIGS. 4A through 4C show manufacturing steps of the EEPROM 1 of the invention.

[0020] FIGS. 5A through 5C show the conventional manufacturing process of the EEPROM.

[0021] FIGS. 6A and 6B show the conventional manufacturing process of the EEPROM.

[0022] The structure of the EEPROM 1 of the invention will be described in reference to the appended drawings. The EEPROM 1 has a memory transistor 1aand a select transistor 1b.In a substrate 2 are formed; a drain 4 as a first region of the memory transistor, and a source 3 as a second region of the memory transistor; and a source 6 of the select transistor. The drain 4 is shared with the memory transistor and the select transistor. In this embodiment, a P-type substrate 2 is used, with the drain 4, sources 3 and 6 being made as N⁺ regions. The drain 4 has an N⁺ region 5 containing a slightly lower impurity concentration.

[0023] The region between the drain 3 and the source 4 is a channel region 10 where an electric path can be formed.

[0024] A tunnel oxide film 13 as a first insulation film is formed on the drain 4 and the channel region 10. The tunnel oxide film 13 has on the drain 4 a tunnel window 13aas a thin film portion thinner than the part of the film located on the channel region 10.

[0025] A floating gate electrode 11 of the floating type is formed on the tunnel oxide film 13. The floating gate electrode 11 has a conductive side wall 23 located on the tunnel window 13a,a main part electrode 9 located in the vicinity of the tunnel window 13aand on the channel region 10, and a connecting portion 25. The connecting portion 25 is located between the conductive side wall 23 and the main part electrode 9 to electrically interconnect them.

[0026] An ONO film 14 as a second insulation film is formed over the floating gate electrode 11. A control gate electrode 29 is formed over the ONO film 14.

[0027] Conductive side walls 33, like in the memory transistor, are also formed on both sides of the gate electrode 19 of the select transistor 1b,and are electrically connected through a connecting portion 35 to the gate electrode 19.

[0028] Next, the manufacturing process for the EEPROM 1 will be described. First, as shown in FIG. 2A, a silicon oxide film (SiO₂) 13 of an approximate thickness of 350 angstroms is formed on the surface of the substrate 2. A main part electrode 9 and a select gate 19 are formed using the CVD process and a resist (not shown).

[0029] To form the N³⁰ region 5, and the tunnel window 13aas a thin film portion, as shown in FIG. 2B, a resist 41 is formed spaced from the main part electrode 9 by a distance W2, and the tunnel oxide film 13 is temporarily removed. In this state, N-type impurities are implanted with the resist 41 and the main part electrode 9 being used as masks. After that, the resist 41 is removed and a silicon oxide film of a thickness of 80 to 100 angstroms is formed. As a result, the tunnel window 13aas a thin oxide film is formed as shown in FIG. 2C. At this time, a silicon oxide film 51 is formed also on the surfaces of the main part electrode 9 and the select gate electrode 19.

[0030] A polysilicon layer 55 is deposited to a thickness of 0.2 micrometers as shown in FIG. 3A using the CVD process. From this state, the polysilicon layer 55 is etched back with anisotropic etching using reactive ion etching (RIE) so that the conductive side walls 23 are left as shown in FIG. 3B. By the way, even if the etching back is made for an extended period of time, the etching proceeds in the vertical direction only, so the width W1 of the conductive side wall 23 is little affected. Therefore, it is possible to precisely control the width W1 of the conductive side walls 23 (see Fig.1) . In other words, since the width W1 of the conductive side walls 23 are determined with the thickness of the polysilicon layer 55 which can be precisely controlled, the conductive side wall 23 may be formed more accurately than when a mask is used.

[0031] The silicon oxide film 51 is wet-etched to partially remove the silicon oxide film located between the main part electrode 9 and the conductive side walls 23 as shown in FIG. 3C. As a result, as shown in FIG. 3D, a gap 28 is formed in the upper part of the space between the main part electrode 9 and the conductive side walls 23. A gap is similarly formed with respect to the gate electrode 19 of the select transistor. The removal of the silicon oxide film between the main part electrode 9 and the conductive side walls 23 has only to be made to the extent that permits electrical interconnection between the main part electrode 9 and the conductive sidewalls 23. Depending on cases, it may be totally removed.

[0032] A polysilicon layer 71 of an approximate thickness of 500 angstroms is formed over the entire surface as shown in FIG. 4A. From this state, an anisotropic etching is made using the reactive ion etching (RIE). As a result, as shown in FIG. 4B, a connecting portion 25 of polysilicon is formed in the gap 28. The conductive side wall 23 and the main part electrode 9 are interconnected through the connecting portion 25.

[0033] After that, like the conventional process, ions of N-type impurities are implanted with the conductive side wall 23 , the main part electrode 9, and the select gate electrode 19 being used as masks. As a result, as shown in FIG. 4C, the sources and the drain of the memory transistor 1aand the select transistor 1bare formed. After that, the EEPROM 1 shown in FIG. 1 is completed by forming the ONO film, control gate electrode, and inter-layer insulation films, and making required wiring.

[0034] As described above, in the above EEPROM 1, the size (width) of the region having the substantial function of the tunnel window may be reduced. In other words, minute dimensioning may be achieved while maintaining the coupling ratio unchanged. The effective width W1 of the tunnel window 13afor transferring charges may be determined with the width of the conductive side wall 23 because the conductive side wall 23 is formed and connected to the main part electrode 9 on the tunnel window 13a.The width W1 of the tunnel window 13amay be accurately determined irrespective of the width W2 (shown in FIG. 2C) of the tunnel window 13adetermined with the resist since the width of the conductive side wall 23 may be determined with the silicon oxide film 55 shown in FIG. 3A.

[0035] While this embodiment is described as the case in which the invention is applied to the EEPROM having the select transistor, the invention may also be applied to flash memories or the nonvolatile memories having no select transistor. In other words, the invention may be applied to any nonvolatile semiconductor memory as long as it may be switched between write and non-write states by transferring charges between the floating electrode and the impurity region of the substrate through the thin film portion of the tunnel oxide film.

[0036] While this embodiment is constituted that the silicon oxide film (insulation material) present in the gap between the main part electrode 9 and the conductive side wall 23 is partially removed to form a polysilicon-made connecting portion as a means for interconnecting both of the parts, the means is not limited to such a constitution but any means for interconnecting the main part electrode 9 and the conductive side wall 23 may be used.

[0037] In the nonvolatile semiconductor memory device of this invention, the floating electrode has the conductive side wall and the main part located above the region capable of forming the electric path and in the vicinity of the thin film portion, and the conductive side wall is electrically connected to the main part. Therefore, the effective area of the thin film portion for transferring electric charges is determined with the size of the conductive side wall. As a result, minute dimensioning may be achieved.

[0038] In the nonvolatile semiconductor memory device of this invention, the floating electrode has the conductive side wall and the main part located in the vicinity of the thin film portion and above the tunnel oxide film excluding the thin film portion, and electrically connected to the conductive side wall. Therefore, the effective area of the thin film portion for transferring electric charges is determined with the size of the conductive side wall. As a result, minute dimensioning may be achieved.

[0039] According to the manufacturing process for the nonvolatile semiconductor memory device of this invention, a main part of the floating electrode for storing charges is formed on an insulation film formed on a substrate, and the insulation film around the side wall of the floating electrode is partially removed, with the floating electrode being used as a mask. An oxide film of a specified thickness is formed on the substrate surface from which the insulation film has been removed. Thus, a tunnel oxide film having a thin film portion is formed. A conductive side wall is formed over the thin film portion and on the side wall of the main part to electrically interconnect the main part and the conductive side wall. The effective area of the tunnel oxide film is determined with the size of the conductive side wall. As a result, minute dimensioning may be achieved.

[0040] According to the manufacturing process for the nonvolatile semiconductor memory device of this invention, the conductive side wall is formed on the side wall of the main part over the thin film portion by forming a conductive layer over the entire surface, followed by anisotropic etching. Therefore, the size of the conductive side wall may be determined with the thickness of the conductive layer. This makes it possible to manufacture a nonvolatile semiconductor memory device having a minute charge transfer window.

[0041] According to the manufacturing process for the nonvolatile semiconductor memory device of this invention, when part of the insulation film around the side wall of the floating electrode is removed, first conductive type impurities are implanted into the substrate with the floating electrode being used as a mask. Therefore, a mask for forming the region for introducing the first conductive type impurities into the substrate becomes unnecessary, and the relationship between the region for introducing the first conductive type impurities and the main part may be determined by self-alignment.

[0042] According to the manufacturing process for the nonvolatile semiconductor memory device of this invention, the electrical connection between the main part side surface and the conductive side wall is made by partially removing the insulation film between the main part side surface and the conductive side wall and depositing a conductive material layer between them. Therefore, no separate wiring is necessary for electrical connection between the two.

[0043] While the invention is described above in the forms of preferable embodiments, each term is used not for the purpose of limitation but explanation, and therefore, may be changed within the scope of the appended claims without departing from the scope and spirit of the invention.