US 6,248,632 B1Grant
Method of forming gate electrode with polycide structure in semiconductor device
Issue Date:2001-06-19
•4 Claims
•4 Drawing Sheets
Abstract
A method of forming a gate electrode with a polycide structure in a semiconductor device which can improve the interface roughness between a polysilicon layer and a silicon layer, is disclosed. According to the present invention, a gate insulating layer and a doped polysilicon layer on the gate insulating layer are formed on a semiconductor substrate. A nitrogenous polysilicon layer is then formed on the surface of the polysilicon layer by ion-implanting nitrogen ions (N2+) into the surface of the polysilicon layer or by thermal-treating the surface of the polysilicon under the atmosphere of gas containing nitrogen. Next, a metal silicide layer is formed on the nitrogenous polysilicon layer. Thereafter, the metal silicide layer, the nitrogenous polysilicon layer and the polysilicon layer are etched sequentially to form a gate electrode.
Metadata
Assignee
- Hyundai Electronics Industries Co., Ltd.
Inventors
- Se Aug Jang
- Heung Jae Cho
Application Information
Application Number:US 09/459,510
Filing Date:1999-12-13
Priority Date:1998-12-24
Art Unit:7
Classifications
IPC:
H01L 21336
Field of Search:
438261438264438528438910438585438258438655438592438683438652
Patent Drawings (4 sheets)
Description
Background of the Invention
[0002] 1. Field of the Invention
[0003] The present invention relates to a method of manufacturing a semiconductor device, particularly to a method of forming a gate electrode of a MOSFET, and more particularly to a method of forming a gate electrode with a polycide structure in semiconductor device.
[0004] 2. Description of the Related Art
[0005] In general, a gate electrode of a MOS transistor has been formed of a doped polysilicon layer. However, as high integration of semiconductor device, the line widths of a gate electrode and other patterns become fine. Recently, the line width is reduced below 0.15 μm. Therefore, there are problems that it is difficult to apply the doped polysilicon layer to a gate electrode material in a high speed device, since the doped polysiliocn layer has a high resistivity. These problems are also growing more and more serious as the high integration of the semiconductor. To overcome these problems, a gate electrode with a polycide structure in which a silicide layer using a refractory metal such as tungsten(W) and titanium(Ti) is formed on the polysilicon layer, has been researched.
[0006] FIG. 1A to FIG. 1C show a method of forming a gate electrode with a titanium polycide structure in accordance with a prior art.
[0007] As shown in FIG. 1A, a gate oxide layer 11 is grown on a semiconductor substrate 10 and a doped polysilicon layer 12 deposited thereon.
[0008] As shown in FIG. 1B, a titanium silicide(TiSix) layer of an amorphous phase is deposited on the polysilicon layer 12 by physical vapor deposition(PVD) using TiSix target. Next, the TiSixlayer of the amorphous phase is thermal-treated by rapid thermal processing(RTP) at a selected temperature for several seconds, to be transformed into a titanium silicide(TiSi2) layer 13 of a crystalline phase.
[0009] As shown in FIG. 1C, an oxide(or nitride) layer 14 is formed on the TiSi2layer 13, for a self-aligned contact(SAC) process which will be performed after. The oxide layer 14, the TiSi2layer 13, the polysilicon layer 12 and the gate oxide layer 11 are patterned by photolithography and etching process to form a gate electrode.
[0010] Conventionally several thermal processes such as a first thermal process for gate re-oxidation, a second thermal process for forming source/drain, a third thermal process for planarizing a intermediate insulating layer and a fourth thermal process for forming a capacitor and the like, are performed subsequently, after forming the gate electrode as above described.
[0011] FIG. 2 shows a cross sectional view of a gate electrode with a titanium polycide structure in which a TiSi2layer 23 is formed on a polysilicon layer 22 according to the prior art. However, when performing above thermal processes respectively, the TiSi2layer 23 is agglomerated to generate stress, so that Ti of TiSi2layer 23 is diffused into the polysilicon layer 22 and reacted with Si of the polysilicon layer 22, thereby deteriorating the interface roughness between the polysilicon layer 22 and the TiSi2layer 23(TiSi2layer/polysilicon layer), as shown in FIG. 2, after performing above thermal processes.
[0012] Furthermore, in case the interface roughness is extremely deteriorated, the TiSi2layer 23 comes in contact with a gate oxide layer 21, thereby deteriorating the property of the gate oxide layer 21. As a result, the reliability of a device is deteriorated.
[0013] As not above described, in FIG. 2, reference numbers 20, 24, 25 and 26 indicate a silicon substrate, a mask oxide layer, a spacer oxide layer and source/drain regions, respectively.
[0014] Moreover, although described on the gate electrode with the titanium polycide structure, these problems mostly occur in gate electrode with a polycide structure.
Summary of the Invention
[0015] It is therefore an object of the present invention to provide a method of forming a gate electrode with a polycide structure in a semiconductor device which can improve the interface roughness between a polysilicon layer and a silicon layer by preventing a refractory metal of a silicide layer from diffusing into a polysilicon layer when performing thermal processing subsequently, for solving the problems in the conventional art.
[0016] To accomplish this above object, in the present invention, a nitrogenous polysilicon layer is formed on the surface of the polysilicon layer, prior to forming the silicide layer, considering the refractory metal diffusing into the polysilicon layer because of the columnar structure of the polysilicon layer.
[0017] According to the present invention, a gate insulating layer and a doped polysilicon layer on the gate insulating layer are formed on a semiconductor substrate. A nitrogenous polysilicon layer is then formed on the surface of the polysilicon layer by ion-implanting nitrogen ions(N2+) into the surface of the polysilicon layer or by thermal-treating the surface of the polysilicon under the atmosphere of gas containing nitrogen. Next, a metal silicide layer is formed on the nitrogenous polysilicon layer. Thereafter, the metal silicide layer, the nitrogenous polysilicon layer and the polysilicon layer are etched sequentially to form a gate electrode.
[0018] Additional object, advantages and novel features of the invention will be set forth in part in the description which follows, and in part will become apparent to those skilled in the art upon examination of the following or may be learned by practice of the invention. The objects and advantages of the invention may be realized and attained by means of the instrumentalities and combinations particularly pointed out in the appended claims.
Brief Description of the Drawings
[0019] FIG. 1A to FIG. 1C are cross sectional views showing a method of forming a gate electrode with a titanium polycide structure in accordance with a prior art.
[0020] FIG. 2 is cross sectional view of a gate electrode with titanium polycide structure in accordance with a prior art.
[0021] FIG. 3A to FIG. 3E are cross sectional views showing a method of forming a gate electrode with a polycide structure in accordance with an embodiment of the present invention.
Detailed Description of the Invention
[0022] Hereinafter, preferred embodiment of the present invention will be explained with reference to accompanying drawings.
[0023] FIG. 3A to FIG. 3E are cross sectional views showing a method of forming a gate electrode with a titanium polycide structure according to an embodiment of the present invention.
[0024] Referring to FIG. 3A, a gate insulating layer 31 is grown on a silicon substrate 30 and a doped polysilicon layer 32 is deposited thereon.
[0025] Referring to FIG. 3B, a nitrogenous polysilicon layer 32ais formed on the surface of the polysilicon layer 32 by ion-implanting nitrogen ions(N2+) into the surface of the polysilicon layer 32 or by thermal-treating the surface of the polysilicon under the atmosphere of gas containing nitrogen such as N2, NH3and N2O. Preferably, the ion-implantation is performed to the energy of 10 to 30 keV and the dose of 1×1014to 1×1016ions/cm3. Furthermore, the thermal-treating is performed at the temperature of 700 to 900° C. for 10 to 60 minutes.
[0026] Referring to FIG. 3C, a titanium silicide(TiSix) layer of an amorphous phase is deposited on the nitrogenous polysilicon layer 32aby PVD using TiSixtarget. Next, the TiSixlayer of the amorphous phase is thermal-treated by RTP at a selected temperature for several seconds, to be transformed into a titanium silicide(TiSi2) layer 33 of a crystalline phase.
[0027] Referring to FIG. 3D, an oxide(or nitride) layer 34 is formed on the TiSi2layer 33, for a conventional self-aligned contact(SAC) process which will be performed after. Thereafter, the oxide layer 34, the TiSi2layer 33, the nitrogenous polysilicon layer 32a, the polysilicon layer 32 and the gate oxide layer 31 are etched sequentially to form a gate electrode, as shown in FIG. 3E.
[0028] According to this embodiment, the nitrogenous polysilicon layer is formed on the surface of the polysilicon layer using ion-implantation or thermal-treating prior to forming the TiSi2layer, so that TiSi2layer comes in contact with the nitrogenous polysilicon layer. Therefore, Ti of the TiSi2layer is prevented from diffusing into the polysilicon layer by the nitrogenous polysilicon layer, although stress is generated due to agglomeration of the TiSi2when performing thermal processing subsequently. As a result, the interface roughness between the polysilicon layer and the TiSi2layer, is improved, thereby improving the reliability of a device.
[0029] Furthermore, a method according to the present invention may be applied to a gate electrode with a polycide using a metal silicide such as a tungsten silicide(WSi2), a cobalt silicide(CoSi2), a vanadium silicide (VSi2), a chromium silicide(CrSi2), a zirconium silicide(ZrSi2), a niobium silicide(NbSi2), a molybdenum silicide(MoSi2), a hafnium silicide(HfSi2) as well as the TiSi2.
[0030] Although the preferred embodiment of this invention has been disclosed for illustrative purpose, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as described in the accompanying claims.
Claims
What is claimed is:
1. A method of forming a gate electrode with a polycide structure in a semiconductor device, comprising the steps of:
forming a gate insulating layer on a semiconductor substrate;
forming a doped polysilicon layer on the gate insulating layer;
forming a nitrogenous polysilicon layer on the surface of the polysilicon layer, wherein the nitrogenous polysilicon layer is formed by ion-implanting nitrogen ion (N2+) into the surface of the polysilicon layer or by thermal-treating the surface of the polysilicon under the atmosphere of gas containing nitrogen;
forming a metal suicide layer on the nitrogenous polysilicon layer, wherein the metal silicide is formed of a compound selection from the group consisting of vanadium silicide (VSi2), chromium silicide (CrSi2) and zirconium silicide (ZrSi2); and
etching the metal silicide layer, the nitrogenous polysilicon layer and the polysilicon layer sequentially to form a gate electrode.
2. The method according to claim 1, the ion-implanting is performed to the energy of 10 to 30 keV and the dose of 1×1014to 1×1016ions/cm3.
3. The method according to claim 1, wherein the thermal-treating is performed at the temperature of 700 to 900° C. for 10 to 60 minutes.
4. The method according to claim 1, wherein the gas containing nitrogen is one selected from a group consisting of N2, NH3and N2O.
Patent Citations (17)
| Patent | Date | Inventor | Cited By |
|---|---|---|---|
| US4470189 | 1984-09-01 | Roberts et al. | Examiner |
| US4833099 | 1989-05-01 | Woo | Applicant |
| US4897368 | 1990-01-01 | Kobushi et al. | Applicant |
| US5393685 | 1995-02-01 | Yoo et al. | Applicant |
| US5429974 | 1995-07-01 | Hsue et al. | Examiner |
| US5508212 | 1996-04-01 | Wang et al. | Applicant |
| US5648287 | 1997-07-01 | Tsai et al. | Applicant |
| US5710454 | 1998-01-01 | Wu | Examiner |
| US5723893 | 1998-03-01 | Yu et al. | Examiner |
| US6069041 | 2000-05-01 | Tanigami et al. | Examiner |
| US6074915 | 2000-06-01 | Chen et al. | Examiner |
| JP1245560 | 1989-09-01 | Applicant | |
| JP2031427 | 1990-02-01 | Applicant | |
| JP7202011 | 1995-08-01 | Applicant | |
| JP8195358 | 1996-07-01 | Applicant | |
| JP8250451 | 1996-09-01 | Applicant | |
| JP10303422 | 1998-11-01 | Applicant |