Method and equipment for optical communication

[0002] The invention relates to a device and a method for compensation of offset voltages during reception of a fibre optical signal.

[0003] Today's optical fibres have extremely small dispersion in relation to the light absorption in the fibre. This means that the optical signal in a receiver is characterized by extremely small distortion of the pulse shape. On the other hand, the signal amplitude is often extremely small. After conversion to the electrical form with the help of a light detector, e.g., a PIN-diode (Positive Intrinsic Negative), the signal amplitude is often as low as 5 mV and often superimposed on a direct current level of several volts. These low signal levels must be compared with the maximal specified offset voltage for e.g. a differential amplifier which normally is up to approximately 20 mV. In the case that the offset voltage is much higher than the signal amplitude, an extremely accurate offset compensation is required, and as the offset voltage is also temperature-dependent, an exact compensation is difficult to realize without the receiver being placed in an oven for constant temperature conditions. Such an arrangement should naturally be avoided as much as possible.

[0004] Another problem is the superimposed DC-level which the signal exhibits. It is not desirable to use an AC-coupling capacitor if an integrated manufacturing of the receiver circuit is desired, because the capacitor in general must be realized in a discrete process because capacitors with high capacities are difficult to realize in integrated designs because of their space requirements. Furthermore, even with an ideal AC-coupling there can only be achieved a zeroing of the time-average value of the signal. This average value only corresponds to a threshold level which lies in the middle between the high and low level of the signal when the transmitted signal exhibit a perfect pulse quotient of 50%, i.e., when the transmitted signal has exactly equal amounts of high symbols as low symbols in the signal. By pulse quotient in this connection is meant the number of high signals in the average in relation to the total number of symbols for a binary signal.

[0005] In the case where the pulse quotient continuously or more temporarily deviates from 50%, this threshold level will deviate from the zero level. This means that the signal after AC-coupling will show a certain displacement which, if this displacement is not compensated for, leads to reduced receiver sensitivity. For e.g. FDDI, Fibre Distributed Data Interfaces, which are ring-shaped high speed LAN/MAN-nets, a so-called 4B5B-code is used where the pulse quotient can vary between 40 and 60 percent. A pulse quotient of 40 percent means that the signal shows a DC-component of 40 percent of the signal's peak-to-peak value. This means that if a FDDI-signal is AC-coupled, the level which lies in the middle between the high and low level of the signal will be displaced 10 percent in relation to the idea level. This implies a reduction of the sensitivity of the receiver by theoretically about 1 dB.

[0006] For fibre optic signal transfer normally two level signals, i.e. binary signals, are used with some form of coding, such as e.g. 4B5B or Manchester-coding. In this way, a signal is achieved out of which the clock frequency is comparatively easy to extract.

[0007] Signal limiters which binarize the signal are normally used in fibre optic receivers, as this gives a relatively simple circuit solution for two-level signals, where the signal ideally only can attain two distinct levels. A further reason is that limiting can reduce the loss effects in the receiver, often up to 50 percent. Such a reduction of the loss effects can even itself contribute to a simpler implementation thanks to a reduced cooling requirement.

[0008] The problem of eliminating a DC-level on an incoming signal has earlier been solved for electrical signals. The American Patent Specification U.S. Pat. No. 4,966,529 solves such a problem, which might seem to be close to the above problem stated for fibre optical signals. U.S. Pat. No. 4,996,529 presents a technique intended for signal coding, such as analogue-digital converting, for the compensating of superimposed low frequency voltages. The circuit presented limits an analogue-electrical input signal and contains a feedback loop which in real time compensates for the DC-level of the input signal and adjusts the direct voltage level on the input signal to a limiter comprised in the circuit. Through sampling the limited signal with a large frequency in relation to the band width of the input signal, and accumulating the result, the limited signal is digitally integrated, whereafter it is fed back to the input of the limiter. In this way a negative feedback is achieved which implies an adjustment of the input signal of the limiter so that the output signal of the limiter attains the high signal level during an equally large amount of time as it attains the low level.

[0009] Oversampling of the signal requires that a clock signal is generated at a high frequency in relation to the signal which, because of the thereby resulting loss effects, reduces the field of use for the technique to low-frequency signals, such as speech signals.

[0010] It must, however, be obvious for the skilled person that the basic idea in the above described patent document in principle is applicable even to receivers for fibre optic signal transfer. In analogy with the above described technique, in this case an incoming signal converted to an electrical form is limited, and thereafter integrated and fed back to the limiter in such a way that the level on the fed back signal is adapted to the DC-level of the input signal so that this is compensated. In this way not only will the possible superimposed DC-voltage on the signal be compensated for, but also the offset voltage of the limiter.

[0011] This technique functions perfectly for signals where the pulse quotient is 50 percent. However, as this technique does not take account of the actual pulse quotient of the signal, the application of this technique is less suitable to optical signals where the pulse quotient permanently or somewhat more temporarily differs from 50 percent because of the not-inconsiderable reduction of the receiver sensitivity which thereby occurs. The field of use for this technique is thereby to some extent limited.

[0012] In the magazine Electronic Designfrom Jun. 12, 1995, a circuit is described with a feedback loop intended for signal transmission on twisted cable pairs with high band width. The feedback loop adjusts the DC-level on an incoming electrical three-level signal, where the signal ideally attains three different voltage values lying symmetrically around zero volts. Through the integration of the difference signal between the DC-adjusted signal and a theorectic wave form, developed from this signal, a DC-component is achieved which can be added to the signal. In this way the DC-draft which tends to occur in certain applications for wide band data communication over twinned copper wire conductors is compensated for.

[0013] The circuit measures the size of the superimposed low-frequency voltage which can occur because of asymmetric data on the copper wire network and compensates for the possible base line shifting through in real time shifting the DC-level on the incoming signal back to its original level. In order to achieve a value for the size of the superimposed low frequency voltage in the received signal, the circuit forms a theoretic wave form of how the incoming signal probably would have looked if the superimposed voltage had not been present. This idea signal is compared to the incoming signal in order to detect the size of its offset voltage and to correct the same with the help of a built-in DC-level adjuster.

[0014] As mentioned above, in receivers for fibre optical signals it is, because of the low signal levels, problematic to achieve an exact offset compensation which is of great weight since the offset voltage often are much greater than the signal amplitudes. A further problem of a number of applications is that the voltage levels which lie in the middle of the high and low levels of the signals are different from the direct voltage level of the signal because of the pulse quotient differing from 50 percent, which means that the symbols with high and low levels appear with uneven frequencies in the signal.

[0015] The present invention solves these problems through providing a feedback loop for automatic compensation of the DC-level of the incoming signal. During the feed-back account is taken of the true pulse quotient of the transmitted signal through the direct current level of the input signal being related to the time average value of the output signal, which corresponds to the pulse quotient.

[0016] By letting the incoming signal be binarized with the help of a limiter, which acts as a decision circuit having the task of performing a subtraction between the signals on its two inputs and comparing the result with its decision threshold level and controlling its binary output signal in accordance with this relationship, it is possible, based on the binarized signal, to reform the theoretically most possible sent-signal sequences with known techniques through, e.g., date generation with the help of a phase-locked loop (PLL). In this way the receiver circuit's output signal is obtained. By calculating the time average value of this output signal, a value for the pulse quotient of the transmitted signal can be obtained.

[0017] The decision threshold level of the limiter is ideally equal to zero but because of the offset voltage this generally can not be achieved. The decision threshold level will therefore deviate from zero. For a correct relationship between the direct voltage level of the incoming signal and the decision threshold level of the limiter, the limited signal's time average value essentially must correspond to the pulse quotient of the transmitted signal, which corresponds to the time average value of the output signal, in such a way that the limiter gives a high level out during an equally large amount of time that the output signal has a high level. The output signal is therefore compared with the binarized signal and an integrated signal is formed, which corresponds to an integrated form of a difference signal generated by the above comparison between the output signal and the binarized signal. This integrated signal, which corresponds to the difference between the binarized signal's average value and the output signal's average value is subtracted from the incoming signal and adapts the direct voltage level on the input signal of the limiter in such a way that a negative feedback is obtained.

[0018] In this manner the direct voltage level on the signal which the limiter binarizes will be adapted so that the output signal of the limiter, the binarized signal, will attain a high level during essentially an equally large amount of time as the transmitted signal, irrespective of the offset voltage of the limiter and of a possible direct voltage level on the optical signal converted to electrical form.

[0019] The feedback loop can advantageously be made very slow in relation to the frequency of the optical signal as the offset voltage of the limiter, which is to be compensated for, changes extremely slowly.

[0020] The intention of the present invention is consequently for an optical receiver to obtain an exact offset compensation while taking account of the actual pulse quotient of the transmitted signal.

[0021] An advantage of the invention is that it can be made in its entirety as an integrated circuit without external capacitors.

[0022] The invention is intended for receivers of optical two-level signals with arbitrarily high band width. On account of its construction which offers low loss effects, it is extremely suitable for high band widths up to several giga bits per second.

[0023] The invention will be explained more closely below with the help of examples of embodiments with reference to the accompanying drawings.

[0024] FIG. 1 shows a general block diagram of a fibre optic receiver according to the present invention.

[0025] FIG. 2 shows an electronic circuit diagram for a detail of an alternative embodiment in relation to the example shown in FIG. 3.

[0026] FIG. 3 represents a clear block diagram for a fibre optic receiver according to the present invention.

[0027] In FIG. 4, a block diagram for a detail of the example of an embodiment shown in FIG. 3 is depicted.

[0028] FIG. 5 shows a signal diagram of an example of the signal flow for the example of an embodiment depicted in FIG. 4.

[0029] FIG. 6 shows a signal diagram of an example of the signal flow for the example of embodiment depicted in FIG. 3.

[0030] FIG. 1 depicts a block diagram for a fibre optic receiver according to a basic embodiment of the present invention.

[0031] An optical signal O is detected with an opto electrical converter 1 which is built-up according to known techniques and consists of a PIN-diode or an avalanche-photo diode (APD) with peripheral components. The opto electrical converter is followed by an amplifier stage 2 which converts the diode current from the opto electrical converter into a corresponding electrical voltage. The amplifier stage 2 furthermore contains a certain filtering. The resulting electrical signal IN out of the amplifier stage is superimposed onto a direct voltage. This signal is binarized with the help of a limiter 3 which acts as a decision circuit having the task of subtracting its two input signals, the signal IN and a comparison signal INT, and comparing the result with its decision threshold level and thereafter controlling its output signal, the binarized signal S, so that it has a high or low level depending on the difference between the signals IN and INT being higher or lower than the decision threshold level. The decision threshold level is dependent on the offset voltage of the limiter.

[0032] The binarized signal S from the limiter 3 goes to a data regeneration circuit 6, in which the theoretically most likely signal sequence is regenerated with the help of a phase-locked loop (PLL) in a known manner. In this way the output signal UT is obtained, which has the same signal levels as the binary signal S. Naturally, instead of the phase-locked loop, some other known type of timing regeneration can be used.

[0033] The binarized signal S from the limiter 3 is filtered with a low-pass filter 7 which, in relation to the band width of the signal, has such a low cut-off frequency that its output signal substantially can be considered to be a time average value for the binarized signal S. In the same way the output signal UT is filtered with a low-pass filter 8 with an identical cut-off frequency to the low-pass filter 7.

[0034] These two filtered signals are compared by a difference signal former 4 which produces a difference signal D. The difference signal former functions in this way as a pure subtracter. The different signal D is integrated according to known techniques with an analogue integrator 5, the output signal of which, the comparison signal INT, goes into one of the two inputs of the limiter 3. In this way a loop with negative feeback is achieved.

[0035] The integrator 5 is accomplished using analogue techniques but the integration can naturally also be performed digitally. Several suitable techniques for this purpose have been presented. A conceivable advantage of digital integration is that the necessary capacitors can be made small, which is extremely suitable for integrated circuits.

[0036] With correct data regeneration the time average value of the output signal UT corresponds to the share of symbols with a high level in the transmitted signal. This share normally lies around fifty percent. With the correct choice of the limiter 3, the binarized signal S has an equally large share of high levels as the output signal UT. This is achieved through the integration of the difference signal D, which has the consequence that the comparison signal INT is adapted according to the average value of the difference signal. The comparison signal INT is subtracted from the signal IN+, IN− so that the direct voltage level on the signal resulting out of that is adapted to the decision threshold level of the limiter 33.

[0037] The negative feedback makes the comparison signal INT, the integrated signal, be adjusted in such a way that the time average value of the difference signal D goes towards zero. This means that the correct adjustment of the comparison signal INT for adaptation of the DC-level for the limiter is achieved with account taken for the real symbol content of the transmitted signal, i.e., the pulse quotient, and to the offset voltage of the limiter 3. Consequently, the circuit is responsible for the adaptation of the comparison signal to the input signal also when offset voltages and, should the occasion arise, the DC-level of the input signal are shifting.

[0038] As subtraction and integration are linear functions, it is equivalent to perform these in the opposite order. Consequently, it can be possible with an integrator device to integrate the binarized signal S and the output signal UT each by themselves and with a subtractor obtain a signal to feed back to the signal limiter 3.

[0039] In FIG. 1 all the function blocks are drawn with asymmetric inputs and outputs. It is, however, completely possible to make essentially all the signals after the amplifier stage 2 in symmetrical, i.e., differential, form. This is also evident from studying the example of an embodiment shown in FIG. 3.

[0040] the two low-pass filters 7 and 8 in FIG. 1 are identical. This is, however, not theoretically necessary, since only the average values of the signals are of interest. Low-pass filters can advantageously be used for simplifying the construction of the subsequent components as these in this case do not have to cope with equally high frequency components. The low-pass filters can, however, in principle be completely left out, which is evident from the subsequent example of an embodiment.

[0041] FIG. 3 shows a block diagram for a fibre optic receiver made according to an embodiment of the present invention. The optical signal O is converted to electrical form with the help of a PIN-diode 30 according to known technique. The signal is coupled via the input stage 31, which has symmetrical outputs IN+, IN− and contains some amplification, to a DC-level regulator 32 which adjusts the direct voltage level of the limiter 33 which binarizes the signal. A clock signal CL+, CL− is generated from the so obtained binarized signal S+, S−, using known technique with the help of a phase-locked loop 36ain the data regeneration circuit 36. With the help of the clock signal, the most probable transmitted signal series is reformed from the binarized signal in a data clock circuit 36bas the symmetrical output signal UT+, UT− in a known manner.

[0042] In analogy with the example of an embodiment in FIG. 1, a difference signal D is produced, which is integrated to a signal INT and fed back. In this example of an embodiment this takes place in the block 34. The output signal INT from this block 34 is connected to the DC-level regulator 32.

[0043] In certain cases it can be desirable, during the comparison between the binarized signal and the output signal, to let the first signal dominate somewhat over the latter. When starting up the receiver circuit, the comparison signal INT can be completely incorrect relative to the direct voltage level of the input signal IN+, IN−, so that the limiter 33 in extreme cases gives a constant output signal S+, S−, irrespective of the value of the input signal. Such a constant level of the binarized signal would with a realization of the invention as e.g. in FIG. 1, result in an likewise constant output signal. The consequence of this would be that the difference signal D would be constantly zero, whereby a balance is achieved and the comparison signal INT theoretically would lie still so that the DC-level error of the input signal would remain. In this way, the receiver could be locked in a position where all received symbols are the same.

[0044] In the example of a an embodiment in FIG. 3, the output signals UT+, UT− are attenuated with respect to the binarized signal S+, S− before the difference signal former 34b,which subtracts two differential signals and forms the difference signal D, which is integrated with the help of the integrator 34c.This attenuation takes place with the amplifier 34aand is indicated in the figures with a constant C_IN. By means of such a solution, with the help of the amplifier 34a,letting the binarized signal S+, S− dominate somewhat over the output signal UT+, UT−, the occurrence of the above described locking is prevented because equal signal levels in both of the input pairs to the block 34 in this case anyway implies a difference signal D which is different from zero. In this way, the comparison signal will let the input signal of the limiter 33 drift in towards a correct level.

[0045] In this example of an embodiment the amplifier 34ais controllable in such a way that the amplification C_IN, during the phase-in stage of the receiver before the feedback loop has adjusted itself, attains a value which is less than one, whereas in the normal working position after phasing-in of the receiver circuit, it is equal to one.

[0046] The binarized signal S+, S− from the limiter 33 and the clock signal Cl are connected to a circuit 36c,which produces an alarm on a synchronization alarm signal 39 in the case that the binarized signal and the clock signal are unsynchronized. Herewith, the amplification C_INin the amplifier 34aattains its lowest value until the phase-locked loop has regular flanks upon which it can lock. Thereby, the phasing-in criterion is fulfilled and the alarm on the synchronization alarm signal 39 is stopped. The amplification C_INin the amplifier 34ais raised to one and the feed-back can work under ideal conditions, i.e., with equally large priority for the binarized signal as for the output signal UT+, UT−.

[0047] A receiver circuit according to the invention can, as long as the clock signal is phased with the binarized signal S+, S−, work with very large variations for the pulse quotient for the transmitted signal. The timing regenerator, which in this example of the embodiment is constituted by the phase-locked loop 36a,can in principle also work with extremely large variations for the pulse quotient. However, that requires that flanks occur in the signal with a certain regularity. This requirement is, however, fulfilled according to known technique with suitable coding of the transmitted signal. This means that the timing regenerator can lock to the binarized signal as soon as pulses appear in the binarized signal.

[0048] The timing regenerator's ability to lock at the binarizeed signal S+, S− thus can be used as a criterion of whether the receiving circuit is working in the phasing-in state, in the case when the circuit has not phased in and the relevance of the output signal cannot be guaranteed, or in the normal working condition, when the circuit has phased in and the feedback loop works in accordance with the theory.

[0049] A more simple implementation of the receiver circuit is achieved if the amplification C_INin the amplifier 34aconstantly attains a value less than one. In accordance with the disclosure above, the above described locking of the circuit is hereby prevented. Allowing the binarized signal S+, S− in this way to dominate over the output signal UT+, UT− even in the normal working condition when the feedback loop has phased in implies, however, for the cases when the pulse quotient of the transmitted signal deviates from fifty percent, that the sensitivity of the receiver is lowered somewhat in relation to the idea condition where the amplification C_INis equal to one.

[0050] Certain optical communication systems, such as fibre optical network versions of Token Ring or Ethernet, use besides the two normal signal levels an optical interruption. During such a interruption, the optical effect level should be extremely low, e.g., less than −40 dBm (dB related to 1 mW). The present invention uses only two signal levels. It is, however, fully possible to combine a feedback loop, as in the example of the embodiment in FIG. 3 with a detector for optical interruptions. Several such detectors are known. Depending on the type of detector, it can be placed so that it detects interruptions in the signal before the input stage 31, where the signal is represented by the current through the PIN-diode 30, or so that it detects interruptions by measuring the signal level of the signal IN+, IN− after the input stage 31.

[0051] At the detection of an optical interruption, the integration by integrator 34cis appropriately broken so that the signal INT retains its value during the interruption. In this way, the feedback loop after the optical interruption can begin to work from a probably suitable starting point for correct binarization of the signal.

[0052] The limiter 33 in FIG. 3 can, if so desired, be provided with hystereses. By such a use of hystereses for the change-over level for the limiter, so that the threshold value for changing over from high to low level differs somewhat from the threshold value for changing over from low to high level, false flanks, produced by noise, in the binarized signal S+, S− can be counteracted.

[0053] FIG. 2 shows a method for the realization of the functionality of the block 34 in FIG. 3. The binarized signal S+ and S− from the limiter 33 equipped with differential outputs in FIG. 3 goes in to two bipolar transistors Q₂and Q₁, which form a differential amplifier stage. This differential amplifier stage is provided with current by a current source S₂. At the signal levels which apply in use, the differential amplifier stage is over-excited so much that it basically functions as a current switch for the current through the current source S₂. In the same way, the output signal UT+ and UT− from the data regeneration circuit 36 is coupled into two bipolar transistors Q₄and Q₃acting like current switches which control the current through a current source S₁.

[0054] The collectors belonging to the transistors Q₁and Q₄are joined and connected to a current mirror which is built up of two PMOS-transistors M₁and M₂in a known manner. The drains of these transistors are coupled to a supply voltage V_CCwhile their respective gates are coupled together. Since the transistors in this way will have the same voltage over gate and drain, the current through M₂, with the reference numeral i₂, will be equally large as the current through M₁, designated i₁, which is the sum of the currents through Q₁and Q₄. In an equivalent way, the current i₂is reflected in a current mirror built-up of two NMOS-transistors M₅and M₆. A current i₅through the transistor M₆thereby corresponds to the current i₂through the transistor M₅, which in turn has the same value as the current i₁.

[0055] In a corresponding way the collectors belonging to the transistors Q₁and Q₂are joined together and connected to a current mirror build up of two PMOS-transistors M₃and M₄. In the same way as described above, it therefore follows that a current i₄attains the same value as the current i₃.

[0056] The sources on the transistors M₄and M₆are both joined together to the output of the block 34. A capacitor C_Zlies between the output and signal earth. As the current through the output can be ignored, the current i₆through the capacitor will be equal to the difference between the currents i₄and i₅, which implies the following relationship: $u_{c_z}=u_0+\frac{1}{C_z}{\int }_{t_0}^t\left(i_4-i_5\right)dt=u_0+\frac{1}{C_z}{\int }_{t_0}^t\left(i_3-i_1\right)dt.$

[0057] Here u_Czmeans the voltage over the capacitor C_Zas a function of the time t, and u₀the voltage over the capacitor C_Zat a time point t₀.

[0058] The current i₃is the sum of the current through the transistor Q₂and the current through the transistor Q₃. The average value of the current through Q₂is equal to the share, in the following designated k_S, of the time during which the binarized signal S+, S− in average is at a high level, multiplied by a current I_S2through the current source S₂. In the same way, the average value of the current through Q₃is equal to the time share under which the output signal UT+, UT− is at a low level, multiplied by a current I_S1through the current source S₁. If the time share for high level in the output signal is designated k_UT, this means for and average value {circumflex over (l)}₃of the current i₃:

[0059] î₃=k_S·I_S2+(1−k_UT)·I_S1·

[0060] The average value {circumflex over (l)}₁of the current i₁will be in the same way:

[0061] î₁=k_UT·I_S1+(1−k_S)·I_S2·

[0062] From that it follows that:

[0063] î₆=(2·k_S−1)·I_S2−(2·k_UT−1)·I_S1·

[0064] If then the current I_S1is the same size as I_S2, then the value {circumflex over (l)}₆, the average value of the current i₆, will be proportional to k_S−k_UT, i.e. the difference of the share of high level in the average of the binarized signal S+, S− and of the output signal UT+, UT−.

[0065] If these two time shares correspond, i.e., if the signals S+, S− and UT+, UT− in the average have high level during an equally large share of the time, the value {circumflex over (l)}₆will become zero and the voltage u_Cz, which corresponds to the signal INT, will not change because the charge of the capacitor is unchanged. On the other hand, if the binarized signal attains a high level during a larger share of the time than the output signal, the value {circumflex over (l)}₆will become positive, which means that the charge on the capacitor increases and INT is raised. This implies in turn that the input signal to the limiter 33 is lowered and the binarized signal will attain a high level during a somewhat smaller share of the time. In this way, the feedback loop will be adjusted so that the signals S+, S− and UT+, UT− in average will attain a high level during an equally large part of the time.

[0066] If, on the other hand, the current I_S2is greater than the current I_S1, then the time share of high levels in the binarized signal S+, S− will dominate in the above expression in relation to the output signal UT+, UT−. This corresponds to the relationship with coupled-in attenuation in the amplifier 34ain FIG. 3. Equally large shares of high levels in the two signals will then imply a positive value for the average value {circumflex over (l)}₆of the current i₆. Thereby, in this case, the comparison signal INT will be raised and the feedback loop will tend to be adjusted to a balance where the binarized signal attains a high level during a somewhat longer time share than the output signal UT+, UT−. By letting the signal 39 from the phase-locked loop 36ain FIG. 2 control the current source S₂, the binarized signal S+, S− can be given a priority with respect to the output signal UT+, UT− during the phasing-in state of the receiver. In this way, a balance can be prevented from being achieved for constant levels on the binarized signal and the output signal.

[0067] When the phase-locked loop 36afinds flanks that it can lock on to, the binarized signal S+, S− obviously is not keeping a constant level. The feedback can in this case be allowed to work under idea conditions, i.e., at equally large priorities for the binarized signal as for the output signal UT+, UT−.

[0068] FIG. 4, which shows the synchronization alarm generator 36cof FIG. 3, illustrates together with the signal diagram in FIG. 5, which shows an example of signal flows for the mentioned signals, the production of the synchronization alarm signal, which as described above regulates the relationship between the binarized signal S+, S− and the output signal UT+, UT− during the formation of the difference signal D. In these FIGS. 4 and 5, all the signals are given as asymmetric signals. It is still completely equivalent for the function to use differential signals. In the following description, the signals in FIGS. 4 and 5 can therefore be considered to represent either asymmetric or differential signals.

[0069] The binarized signal S is delayed a half clock period with the help of a delay unit 41, whereafter this delayed signal and the non-delayed signal S are each fed to an input of an exclusive OR-gate 42, which realizes the function addition modulus 2. From the exclusive OR-gate 42, a flank pulse signal E is obtained with an equally large pulse width as the clock signal CL has. The flank pulse signal E is fed together with the clock signal to an exclusive OR-gate 44, from which a signal COR is obtained. This is filtered with a low-pass filter 45, which in relation to the clock signal CL has such a low cut-off frequency that the output signal CORM of the filter 45 in the main is to be considered as the time average value COR_averageof the signal COR. The voltage level of the time average value COR_averagein relation to the signal COR is given in FIG. 5. The signal CORM is compared with the help of a decision circuit 46 with a reference voltage V_REF. The decision circuit 46 can consist of a simple comparator which forms the synchronization alarm signal which in FIG. 3 has the reference numeral 39. This alarm signal, which is active high, has a high signal level when the voltage of the signal CORM from the low-pass filter 45 exceeds the reference voltage V_REFand a low signal level when it is below it.

[0070] FIG. 5 shows more closely the signals S, CL, E, COR and COR_averagein a diagram with time t on the abscissa and a voltage V on the ordinate. When the clock signal Cl is perfectly phased-in with the binarized signal S, the pulses in the signal E basically correspond to the pulses in the clock signal. The transmitted signal in this example has the characteristic that it in average has 0,5 signal level passes per clock period. This means that the minimum average level of the signal COR seen over a long time period is 0,25·A. As is evident from FIG. 5, A thereby represents the peak-to-peak value of the signal COR.

[0071] Because there is an uncertainty in the position of the flanks of the binarized signal S, the pulses in the signals E and CL even with perfect synchronization seldom correspond exactly. Therewith, the average value COR_averageon COR will be somewhat higher than the above stated value.

[0072] If, on the other hand, the binarized signal S and the clock signal CL are completely uncorrelated with each other, it is easy to see that the average value COR_averageof the signal will be equal to 0,5·A. For an adequate determination of whether the timing regenerator is locked on the binarized signal and the clock signal CL thereby synchronised with the transmitted signal, the reference voltage V_REFshould consequently lie at a suitable level between 0,25·A and 0,5·A.

[0073] In FIG. 6 the example of the embodiment in FIG. 3 is illustrated with a signal diagram which shows an example of signals. The differential signals represented in FIG. 3 are herein represented with signals in relation to earth. The IN-signal is consequently equal to IN+ minus IN−. The same is valid for the reference numerals of the rest of the signals presented here, which in FIG. 3 are given as differentials.

[0074] Upmost in the Figure there are illustrated the input signal IN converted to electrical form and the direct voltage level U_mon which this signal is superimposed. In the same diagram the signal INT is also given. This is substracted from the signal IN before binarization in the limiter with number 33 in FIG. 3. The limiter subtracts the signal level on its negative input from the signal level on its positive input and lets the result control the so binarized signal S in such a way that the limiter gives out a high level if this result is greater than its decision threshold level, and a low level if the result is less than the decision threshold level.

[0075] For better clarity, so that the change-over time point of the limiter appears, the voltage level TH on the decision threshold level of the limiter is also shown in relation to the IN-signal. This state corresponds to the true decision threshold level plus the signal INT. With an idea signal limiter the decision threshold level would be zero and the signal INT correspond to the voltage level TH. The discrepancy shown in the diagram between the signal INT and the voltage level TH is to be attributed to the offset voltage of the limiter.

[0076] The binarized signal S from the limiter and the output signal UT are also shown in the FIG. The output signal is taken from the data regeneration circuit 36 in FIG. 3 by determining a most probable signal level in each clock pulse period.

[0077] The difference signal D is here directly proportional to the difference between the signal S and the signal UT. The amplification C_INin the amplifier 34ais consequently equal to the value one in this example. The signal INT obtained by integration of the difference signal D, which is shown upmost in the Figure, is also shown at the bottom in the same FIG. 6. In order to emphasize the character of the signal, it is not, however, shown in the same scale as above in the Figure.

[0078] In this description of the signal diagram this is provided with references to FIG. 3. However, the references could be equally valid for FIG. 1, if the low-pass filters 7 and 8, which are not necessary for the function of the circuit, were left out.