Method for implementing a pseudo least recent used (LRU) mechanism in a four-way cache memory within a data processing system

[0002] 1. Technical Field

[0003] The present disclosure relates to a method for improving data processing in general and, in particular, to a method of implementing a pseudo Least Recently Used (LRU) mechanism in a cache memory within a data processing system. Still more particularly, the present disclosure relates to a method for implementing a pseudo LRU mechanism in a four-way cache memory within a data processing system.

[0004] 2. Description of the Prior Art

[0005] A data processing system typically includes both a system memory and a cache memory. A cache memory is a small and relatively high-speed memory interposed between a processor and the system memory. Information such as data or instructions may be copied from a portion of the system memory into the cache memory so that the information will be available to the processor in a relatively short amount of time when the requested information resides in the cache memory.

[0006] However, if the information requested by the processor cannot be found in the cache memory (i.e., a cache miss), the requested information must be obtained from the system memory. After the information has been obtained from the system memory, a copy of the information may also be placed in the cache memory for future usage, in addition to the immediate usage by the processor. Thus, when all possible storage locations for the information within the cache memory are completely filled, some of the information already stored in the cache memory has to be replaced by the new information via an operation known as linefill. Needless to say, it is important to have a strategy to decide what specific information already stored in the cache memory needs to be discarded in order to make room for the new information. Generally speaking, usually either a Least Recently Used (LRU) or a pseudo LRU strategy is employed to select a cache line of information to be replaced when a cache miss occurs. This is because statistical data has shown that for low associativity caches (caches that are configured as four-way set associative or less), an LRU type of replacement scheme can best minimize the cache miss ratio when compared to other cache replacement schemes such as random replacement or round-robin. The present disclosure provides a method for implementing a pseudo LRU cache replacement mechanism with fewer bits than prior art implementations.

[0007] Within a four-way set associative cache memory, each congruence class contains four cache lines. In accordance with a method of the present invention, each congruence class within the cache memory is associated to a least recently used (LRU) field that has four bits. Each of four cache lines within the congruence class is then assigned a respective set number. The set number of a cache line designated as a least recently used set among the four cache lines is stored in two bits of the LRU field. The set number of a cache line designated as a most recently used set among the four cache lines is stored in another two bits of the LRU field. In response to a determination that the set number of the least recently used set is higher than the set number of the most recently used set, one of the remaining two cache lines that has a higher set number is assigned to be a second least recently used set.

[0008] All objects, features, and advantages of the present invention will become apparent in the following detailed written description.

[0009] The invention itself, as well as a preferred mode of use, further objects, and advantages thereof, will best be understood by reference to the following detailed description of an illustrative embodiment when read in conjunction with the accompanying drawings, wherein:

[0010] FIG. 1 is a block diagram of a processor in which a preferred embodiment of the present invention may be incorporated;

[0011] FIG. 2 is a block diagram of a cache memory within the processor of FIG. 1, according to an illustrative embodiment of the present disclosure;

[0012] FIG. 3 depicts an example of a true LRU scheme;

[0013] FIG. 4 depicts a prior art implementation of a true LRU replacement mechanism for a four-way cache memory;

[0014] FIG. 5 is an implementation of a pseudo LRU replacement mechanism for a four-way cache memory, in accordance with a preferred embodiment of the present invention;

[0015] FIG. 6 is a high-level logic flow diagram of a rotating method for assigning the state of utilization of two non-recorded cache line sets, in accordance with a preferred embodiment of the present invention; and

[0016] FIG. 7 depicts an example of a pseudo LRU scheme according to a preferred embodiment of the present invention.

[0017] The present invention may be implemented in a variety of processors having at least one cache memory. The processor may be, for example, a reduced instruction set computer (RISC) processor or a complex instruction set computer (CISC) processor. For the purpose of illustration, a preferred embodiment of the present invention, as described below, is implemented on a RISC processor, such as one of the PowerPC™ family of processors that are manufactured by the International Business Machines Corporation of Armonk, N.Y.

[0018] Referring now to the drawings and in particular to FIG. 1, there is depicted a block diagram of a processor in which a preferred embodiment of the present invention may be incorporated. Within a processor 10, a bus interface unit 12 is coupled to a data cache 13 and an instruction cache 14. Both data cache 13 and instruction cache 14 are high speed set-associative caches which enable processor 10 to achieve a relatively fast access time to a subset of data or instructions previously transferred from a system memory (not shown). Instruction cache 14 is further coupled to an instruction unit 11 which fetches instructions from instruction cache 14 during each execution cycle.

[0019] Processor 10 also includes at least three execution units, namely, an integer unit 15, a load/store unit 16, and a floating-point unit 17. Each of execution units 15-17 can execute one or more classes of instructions, and all execution units 15-17 can operate concurrently during each processor cycle. After execution has terminated, execution units 15-17 store data results to a respective rename buffer, depending upon the instruction type. Then, any one of execution units 15-17 may signal a completion unit 20 that the instruction unit has finished execution of an instruction. Finally, instructions are completed in program order, and result data are transferred from the respective rename buffer to a general purpose register 18 or a floating-point register 19, accordingly.

[0020] With reference now to FIG. 2, there is depicted a block diagram of the organization of data cache 13 according to an illustrative embodiment of the disclosure. Data cache 13 is configured as a four-way set associative cache having way 0, way 1, way 2, and way 3. In other words, there are four cache lines within each congruence class of data cache 13. Each way of data cache 13 is further divided into two portions, namely, a tag portion and a data portion. As shown in FIG. 2, the tag portion includes tag set 22a, tag set 22b, tag set 22c, and tag set 22dfor way 0, way 1, way 2, and way 3, respectively. Similarly, the data portion includes data set 23a, data set 23b, data set 23c, and data set 23dfor way 0, way 1, way 2, and way 3, respectively. Each of tag set 22a-22dcorresponds to one of data set 23a-23d. Because all tag sets 22a-22dare of identical configuration and all data sets 23a-23dare of identical configuration, only tag set 22aand data set 23awill be described in detail as follows.

[0021] Each of tag set 22aand data set 23ahas 64 cache lines, from line 0 to line 63, and each cache line is indexed by bits 20-25 of an address 21. Each cache line of data set 23ais 64 bytes (or 16 words) wide while each cache line of tag set 22ais only 20 bits wide. Each cache line in data set 23acontains actual data that may be required by a processing unit, such as IU 15, LSU 16 or FPU 17 from FIG. 1, and each byte within the cache line is indexed by bits 26-31 of address 21. On the other hand, each cache line in tag set 22acontains an address tag that is utilized for comparison with bits 18-31 of address 21 in order to determine whether there is a cache “hit” or “miss.” Incidentally, a match between an address tag in one of tag sets 22a-22dand bits 18-31 of address 21 means a cache “hit.”

[0022] In addition to the tag portion and the data portion, each cache may also contain several other bits that are intended for various purposes. For example, there may be two state bits (not shown) per cache line for implementing the four-state MESI (modified, exclusive, shared, and invalid) protocol. However, for the sake of simplicity along with the fact that the implementation of such bits are well known to those skilled in the art of cache memory design, the illustration of those bits in FIG. 2 is omitted.

[0023] In order to implement an LRU cache replacement mechanism (whether a true LRU replacement scheme or a pseudo LRU replacement scheme) for data cache 13, an LRU field 24 is associated with each congruence class of data cache 13 in order to track the state of utilization of cache lines within the congruence class. Because there are four caches within each congruence class, there are four possible states of utilization for each cache line: the least recently used state, the second least recently used state, the second most recently used state, and the most recently used state, which are denoted by LRU, LRU+1, MRU−1 and MRU, respectively. The state of utilization of a cache line within a congruence class can be determined by simply interrogating the LRU field, such as LRU field 24, of that congruence class.

[0024] Referring now to FIG. 3, there is illustrated an example of a true LRU scheme. In cycle a, way 1 of a congruence class within data cache 13 is the LRU, way 0 of the same congruence class within data cache 13 is the LRU−1, way 2 of the same congruence class within data cache 13 is the MRU−1, and way 3 of the same congruence class within data cache 13 is the MRU. In cycle b, after a read access to way 0, way 0 becomes the MRU, way 3 shifts down to be the MRU−1, and way 2 shifts down to be the LRU+1 while way 1 remains the LRU. In cycle c, after a write access to way 1, way 1 becomes the MRU, way 0 shifts down to be the MRU−1, and way 3 shifts down to be the LRU−1 while way 2 becomes the LRU. In cycle d, after a read access has been made to way 0 of the cache lines, way 0 becomes the MRU, way 1 shifts down to be the MRU−1, way 3 and way 2 remain the LRU+1 and LRU, respectively. In cycle e, after a write access to way 2, way 2 becomes the MRU, way 0 shifts down to become the MRU−1, way 1 shifts down to the LRU−1, and way 3 becomes the LRU. Under the true LRU scheme, the information within the cache line that is in the LRU position will always be replaced by new information obtained from the system memory when there is a linefill operation, usually induced by a cache “miss.” With reference now to FIG. 4, there is illustrated a prior art implementation of a true LRU replacement mechanism for a four-way cache memory. As shown, LRU field 40 comprises eight bits. For the purpose of LRU scheme implementation, each tag within tag sets 22a-22dis assigned a two-bit set number. For example, tag set 22ais assigned set 00, tag set 22bis assigned set 01, tag set 22cis assigned set 10, and tag set 22dis assigned set 11. Each of the set numbers will be placed in LRU field 40 in accordance with the state of utilization of its associated cache line. As shown, both bit 40-0 and bit 40-1 are utilized to keep track of the LRU set among tag sets 22a-22d;

[0025] both bit 40-2 and bit 40-3 are utilized to keep track of the second LRU set among tag sets 22a-22d; both bit 40-4 and bit 40-5 are utilized to keep track of the second MRU set among tag sets 22a-22d; and both bit 40-6 and bit 40-7 are utilized to keep track of the MRU set among tag sets 22a-22d.

[0026] Referring now to FIG. 5, there is illustrated an implementation of a pseudo LRU replacement mechanism for a four-way cache memory, in accordance with a preferred embodiment of the present invention. As shown, only the LRU set and the MRU set are recorded in LRU field 24. Specifically, bits 24-0 and 24-1 are utilized to keep track of the LRU set among tag sets 22a-22d, and both bits 24-2 and 24-3 are utilized to keep track of the MRU set among tag sets 22a-22d. The set numbers for tag sets 22a-22dmay be assigned as 00, 01, 10, and 11. The two non-recorded sets are the second LRU set and the second MRU set. A rotating method is then utilized to assign the state of utilization of the second LRU set and the second MRU set such that all four sets will eventually roll through the ordering sequence.

[0027] With reference now to FIG. 6, there is illustrated a high-level logic flow diagram of a rotating method for assigning the state of utilization of the two non-recorded sets mentioned above, in accordance with a preferred embodiment of the present invention. Starting at block 50, a determination is made as to whether or not the set number stored in bits 24-0 and 24-1 (i.e., the LRU set) is greater than the set number stored in bits 24-2 and 24-3 (i.e., the MRU set), as shown in block 51. The set numbers for the four cache lines within a congruence class, as mentioned above, are 00, 01, 10, and 11. If the set number stored in the LRU set is higher than the set number stored in the MRU set, then one of the two non-recorded sets that has a higher set number should be the second LRU set, as depicted in block 52. Otherwise, if the set number stored in the LRU set is lower than the set number stored in the MRU set, then one of the two non-recorded sets that has a higher set number is designated as the second MRU set, as illustrated in block 53.

[0028] Referring now to FIG. 7, there is illustrated an example of a pseudo LRU cache replacement scheme according to a preferred embodiment of the present invention. Using the same access sequence example as depicted in FIG. 3, FIG. 7 illustrates the set numbers associated with each of the usage indications under the pseudo LRU cache replacement scheme of the present invention. As shown, the set numbers in FIG. 7 deviate from those of FIG. 3 only in cycles b and c. As the name implies, the pseudo LRU cache replacement scheme of the present invention does not provide exact ordering information; however, only four bits are needed to implement the pseudo LRU scheme and the decode timing latency for determining the LRU set is dramatically reduced.

[0029] As has been described, the present invention provides an improved method for implementing a pseudo LRU mechanism in a four-way cache memory within a data processing system. By using only four bits to implement a pseudo LRU cache replacement mechanism, storage area on an integrated device is reduced.

[0030] While the invention has been particularly shown and described with reference to a preferred embodiment, it will be understood by those skilled in the art that various changes in form and detail may be made therein without departing from the spirit and scope of the invention. For example, it should be understood by those skilled in the art that the present invention can be implemented with the position of block 52 and block 53 in FIG. 6 interchanged. Furthermore, LRU field 24 in FIG. 5 can be utilized to keep track of any two of the LRU, LRU+1, MRU−1, and MRU sets, other than the LRU and MRU sets as illustrated. For example, LRU field 24 can be utilized to keep track of the MRU and MRU−1 sets.