Apparatus and method for recovering information bits from a 64/256-quadrature amplitude modulation treliss coded modulation decoder

[0002] The present application is related to U.S. patent application having Ser. No. 09,066,048 filed on the same day herewith, entitled “A 64/256 QUADRATURE AMPLITUDE MODULATION TRELLIS CODED MODULATOR DECODER,” by inventors Dojun Rhee and Chanthachith Souvanthong, assigned to the assignee of the present application and is incorporated herein by reference in its entirety.

[0003] The present claimed invention relates to cable modems. More particularly, the present claimed invention relates to recovering information bits from quadrature amplitude modulation trellis coded modulation decoders.

[0004] Originally, cable networks were established to provide TV signals to a community that otherwise could not receive reliable TV signals. With subsequent addition of more channels, cable TVs have gained enormous popularity in the general segment as well. With the advent of the Internet and other digital communications, however, cable networks and channels have become a focus for transmitting digitized information at high speed and bandwidth. This is because a cable network can provide a high speed digital communication channel in addition to well known traditional cable services.

[0005] In cable networks, cable modems provide high speed data transporting functions between a cable network and a connected user. Cable modems typically implement a forward error correction (FEC) scheme. Prior Art FIG. 1 illustrates a conventional cable modem transmission block diagram 100 depicting an FEC scheme that complies with the standard of ITU-T Recommendation J-83 Annex B. The ITU-T Recommendation J-83 Annex B specifies using 64- and 256-quadrature amplitude modulation (QAM). The cable transmission block diagram 100 includes an FEC encoder 102, an FEC decoder 104, and a cable channel 106. The FEC encoder 102 encodes data using conventional FEC schemes for transmission to the FEC decoder 104 through the cable channel 106.

[0006] The FEC encoder 102 includes a Reed Solomon (RS) encoder 108, a convolutional interleaver 110, a randomizer 112 (e.g., scrambler), and a Trellis coded modulation (TCM) encoder 114. The RS encoder 108 sequentially receives 122 byte (i.e., symbol) packets with each byte containing 7 bits. Each packet contains 122 7-bit symbols or bytes. The RS encoder 108 adds six 7-bit redundancy bytes for correcting up to 3 symbol errors. The RS encoded 128 7-bit symbol packets are then transmitted to the interleaver 110 for convolutionally interleaving the symbols by modifying the order of the symbols in a packet. Convolutional interleaving is designed to reduce burst mode errors.

[0007] The interleaver 110 sequentially transmits the RS encoded and interleaved 128 7-bit symbol packets to the randomizer 112. The randomizer 112 adds a pseudorandom noise sequence of 7 bit symbols by performing bit-wise exclusive-OR operations to the symbols in an FEC frame (e.g., packet) to assure a random transmitted sequence. As used herein, an FEC frame refers to a packet that is processed in sequential fashion in the FEC encoder 102 and FEC decoder 104. The randomizer 112 thus provides even distribution of symbols in the constellation (e.g., 64 QAM, 256 QAM) to enable the modem to maintain proper phase lock during the transmission of data.

[0008] The randomized data packets, each of which includes 128 7-bit symbols, are then serially transmitted to the TCM encoder 114. As will be discussed below, the TCM encoder 114 adds redundancy to the data to improve the signal-to-noise ratio by increasing the symbol constellation without increasing the symbol rate. The TCM encoded data is then sent to the FEC decoder 104 over the cable channel 106. The conventional FEC encoder 102 including the RS encoder 108, the interleaver 110, the randomizer 112, and the TCM encoder 114 is known in the art and is described, for example, in a standard recommended by ITU-T (International Telecommunication Union) Recommendation J.83 entitled “Digital Multi-Programme Systems for Television Sound and Data Services for Cable Distribution,” which is incorporated herein by reference in its entirety. For example, the ITU-T Recommendation J.83 specifies a single chip 64/256-QAM TCM encoder, which may be used to encode the inner code for a concatenated decoding scheme of North American cable modem.

[0009] The FEC decoder 104 includes a TCM decoder 116, a de-randomizer 118, a convolutional de-interleaver 120, and an RS decoder 122. The TCM decoder 116 receives the data serially from the FEC encoder 102 via the cable channel 106 and decodes the TCM encoded data. The TCM decoded data is then transmitted to the de-randomizer 118 and de-randomizes the symbols in the 128 7-bit symbol packets. After de-randomizing, the convolutional de-interleaver 120 receives the de-randomized data and de-interleaves the symbols in the 128 7-bit symbol packets. The de-interleaver 120 then transmits the de-interleaved data to the RS decoder 116.

[0010] The RS decoder 116 decodes the received data by performing RS error detection and correction on the received data. This RS decoding removes the 6 7-bit redundancy symbols added by the RS encoder 108 and thereby generates the original MPEG framed data of 122 7-bit symbol or byte packets as output.

[0011] The concatenated FEC coding scheme described in the ITU-T standard employs trellis coding for the inner code. The use of the trellis coding introduces redundancy to improve the signal-to-noise ratio by increasing the symbol constellation without increasing the symbol rate. Such coding is referred to as “trellis coded modulation” or “TCM” for short.

[0012] Prior Art FIG. 2A illustrates a block diagram of a conventional TCM encoder 114. The TCM encoder 114 of Prior Art FIG. 2 is a 64-QAM TCM encoder, which encodes a group of four RS encoded symbols into five consecutive 64-QAM symbols for mapping into five consecutive 64 QAM signals. The 64-QAM TCM encoder 114 serially receives 128 7-bit FEC frames (e.g., packets). A parser 202 identifies a group of four 7-bit symbols as RS1, RS2, RS3, and RS4 and assigns the symbols RS1 and RS2 as in-phase “I” component and assigns the symbols RS3 and RS4 as quadrature “Q” component. The symbol RS1 includes seven bits I₀, I₁, I₂, I₃, I₄,I₅, and I₆; the symbol RS2 includes bits I₇, I₈, I₉, I₁₀, I₁₁, I₁₂, and I₁₃; RS3 includes 7 bits Q₀, Q₁, Q₂, Q₃, Q₄, Q₅, and Q₆; and RS4 includes bits Q₇, Q₈, Q₉, Q₁₀, Q₁₁, Q₁₂, and Q₁₃. Since each symbol contains 7 bits, the total number of input bits for the four symbols is 28 bits with 14 bits each for I and Q symbols.

[0013] In this parsing scheme, the parser 202 assigns the individual bits of the I and Q symbols RS symbols into two groups as follows: two upper or most significant uncoded bit streams 212 and 214 and one lower or least significant bit coded bit stream 206 and 208. For the I component, the parser 202 outputs two upper uncoded bit streams 212: one stream including bits I₁, I₄, I₇, I₁₀, and I₁₂, and the other stream including bits I₂, I₅, I₈, I₁₁, and I₁₃. For the lower coded bit stream 216 of the I component, the parser 202 outputs the bits I₀, I₃, I₆, and I₉for transmission to a differential encoder 204.

[0014] Likewise, for the Q component, the parser 202 outputs two upper uncoded bit streams 214: one stream including bits Q₁, Q₄, Q₇, Q₁₀, and Q₁₂, and the other stream including bits Q₂, Q₅, Q₈, Q₁₁, and Q₁₃. For the lower coded bit stream 218 of the Q component, the parser 202 outputs the bits Q₀, Q₃, Q₆, and Q₉for transmission to the differential encoder 204. The two upper uncoded bit streams 212 and 214 of I and Q components are transmitted to a 64-QAM mapper 210.

[0015] With reference still to Prior Art FIG. 2A, the differential encoder 204 receives the lower streams 216 and 218 of I and Q components in sequence and performs a 90 degree rotationally invariant trellis coding for each corresponding pair of I and Q bits as received. Specifically, the differential encoder 204 performs the rotationally invariant trellis coding for the I and Q bit pairs as they are received as follows: I₀and Q₀, I₃and Q₃, I₆and Q₆, and I₉and Q₉. This allows the information to be carried by the change in phase, rather than by the absolute phase. The differential encoder 204 then transmits the differentially encoded lower stream I and Q components to a pair of punctured binary convolutional encoders 206 and 208, respectively.

[0016] The punctured binary convolutional encoders 206 and 208 are rate ½ binary convolutional encoders and convolutionally encodes redundancy into the least significant bits of the I and Q symbols to improve signal-to-noise gain. The convolutional encoders 206 and 208 are 16-state non-systematic ½ rate encoders with the generator: G1=010 101 and G2=011 111 (25, 37) octal. This generator is equivalent to the generator matrix [1⊕D²⊕D⁴, 1⊕D⊕D²⊕D³⊕D⁴], where D represents a delay element “Z⁻¹.” The ½ rate encoder generates 8 output bits from the four input bits for each lower I and Q component streams 216 and 218.

[0017] The 8 output bits are fed into a puncture matrix: 0001 1111, where “0” denotes NO transmission and “1” represents transmission of the output signal. The puncture matrix essentially converts the rate ½ encoder to rate ⅘ to produce a single serial bit stream of 5 bits. Accordingly, the punctured binary convolutional encoders 206 and 208 encodes the 4 bits of the lower I and Q bit streams 216 and 218, respectively, to generate 5 coded bits of I₀′, I₁′, I₂′, I ₃′, and I₄′ as the convolutionally encoded lower I stream 220 and 5 coded bits of Q₀′, Q₁′, Q₂′, Q₃′, and Q₄′ as the convolutionally encoded lower Q stream 222. Since the TCM encoder 114 encodes a trellis group of 28 input bits to generate 30 bits, the overall trellis coded modulation of the 64-QAM TCM encoder 114 yields a {fraction (28/30)} rate.

[0018] The 64 QAM mapper 210 receives two upper streams 212 and 214 and one lower streams of the I and Q components for a total of six streams. Each of the streams includes 5 serial data bits. Since I and Q includes 3 data streams, both I and Q streams can be used to define 3 bits of data at any one time. For example, the bits I₀′, I₁, and I₂define an I component while the bits Q₀′, Q₁, and Q₂define a Q component.

[0019] The 3 bits of I and Q components can then used in a double mapping process to generate a QAM signal. Specifically, using the 3 bits of I and Q components as indices to a look-up table, the 64-QAM mapper 210 determines a QAM symbol defined by “X” and “Y” components. Each of the “X” and “Y” components is 3 bits and represent 8-PAM signal constellation. Prior Art FIG. 2B illustrates a 64-QAM table that can be used to generate the X and Y values. The TCM encoder 114 may also include a QAM constellation mapper to generate a QAM signal. That is, the QAM constellation mapper can use the X and Y components as indices to a 64 QAM constellation mapping table to generate a corresponding QAM signal. Prior Art FIG. 2C depicts a 64-QAM constellation mapping table. Given the five consecutive bits in each of the streams 212, 214, 220, and 222 of the I and Q components, this double mapping process generates 5 consecutive QAM signals corresponding to the 5 consecutive QAM symbols.

[0020] In addition to the 64-QAM encoding, the ITU-T Recommendation also specifies utilizing a 256-QAM encoding in the cable modem specification. Prior Art FIG. 3A illustrates a block diagram of a conventional 256-QAM TCM encoder 300. Unlike the 64-QAM TCM encoder, which encodes 4 symbols of 28 bits, the 256-QAM TCM encoder 300 encodes a trellis group of 38 bits into five consecutive 256-QAM symbols for mapping into five consecutive 64 QAM signals. The 256-QAM TCM encoder encodes the 38 input bits into 5 consecutive QAM symbols and signals.

[0021] The 256-QAM TCM encoder 300 serially receives 128 7-bit FEC frames (e.g., packets). A parser 302 identifies a trellis group of 38 bits and assigns 19 bits as in-phase “I” component and the remaining 19 bits as quadrature “Q” component. The trellis group of 38 bits may either be in a non-sync trellis group bit order as indicated in row 304 or a sync trellis group bit order as indicated in row 306. To form a trellis group from RS codeword symbols, the parser 302 serializes the RS symbol bits beginning with the most significant bits of the first symbol of the first RS codeword following the frame sync. Bits are then placed in trellis group locations from RS symbols in the order as indicated in rows 304 or 306. For the sync trellis group, RS bits begin at location I₁instead of I₀.

[0022] In this parsing scheme, the parser 302 assigns the individual bits of the I and Q symbols RS symbols into two groups as follows: three upper or most significant uncoded bit streams 308 and 310 and one lower or least significant bit coded bit stream 312 and 314. For the I component, the parser 302 outputs three upper uncoded bit streams 308: one stream including bits I₃, I₇, I₁₁, I₁₅, and I₁₈, another stream including bits I₂, I₆, I₁₀, I₁₄, and I₁₇, and the remaining stream including bits I₁, I₅, I₉, I₁₃, and I₁₆. For the lower coded bit stream 312 of the I component, the parser 302 outputs the bits I₀, I₄, I₈, and I₁₂for transmission to a differential encoder 316. In case of the sync trellis group, the lower coded I component bit stream 312 includes S₀, S₂, S₄, and S₆.

[0023] Similarly for the Q component, the parser 302 outputs three upper uncoded bit streams 310: one stream including bits Q₃, Q₇, Q₁₁, Q₁₅, and Q₁₈, another stream including bits Q₂, Q₆, Q₁₀, Q₁₄, and Q₁₇, and the remaining stream including bits Q₁, Q₅, Q₉, Q₁₃, and Q₁₆. For the lower coded bit stream 314 of the Q component, the parser 302 outputs the bits Q₀, Q4, Q₈, and Q₁₂for transmission to the differential encoder 316. In the case of the sync trellis group, the lower coded Q component bit stream 314 includes bits S₁, S₃, S₅, and S₇. The three upper uncoded bit streams 308 and 310 of I and Q components are transmitted to a 256-QAM mapper 318.

[0024] With reference still to Prior Art FIG. 3A, the differential encoder 316 receives the lower streams 312 and 314 of I and Q components in sequence and performs a 90 degree rotationally invariant trellis coding for each corresponding pair of I and Q bits as received. Specifically, the differential encoder 316 performs the rotationally invariant trellis coding for the I and Q bit pairs as they are received as follows: I₀and Q₀, I₄and Q₄, I₈and Q₈, and I₁₂and Q₁₂for a non-sync trellis group bit order and S₀and S₁, S₂and S₃, S₄and S₅, and S₆and S₇for a sync trellis group bit order. This allows the information to be carried by the change in phase, rather than by the absolute phase. The differential encoder 316 then transmits the differentially encoded lower stream I and Q components to a pair of punctured binary convolutional encoders 320 and 322, respectively.

[0025] The punctured binary convolutional encoders 320 and 322 are rate ½ binary convolutional encoders and convolutionally encodes redundancy into the least significant bits of the I and Q symbols to improve signal-to-noise gain. The convolutional encoders 320 and 322 are 16-state non-systematic ½ rate encoders with the generator: G1=010 101 and G2=011 111 (25, 37) octal. This generator is equivalent to the generator matrix [1⊕D²⊕D⁴, 1⊕D⊕D²⊕D³⊕D⁴], where D represents a delay element “Z⁻¹.” The ½ rate encoder generates 8 output bits from the four input bits for each I and Q component streams 312 and 314.

[0026] The 8 output bits are then fed into a puncture matrix: 0001 1111, where “0” denotes NO transmission and “1” represents transmission of the output signal. The puncture matrix essentially converts the rate ½ encoder to rate ⅘ to produce a single serial bit stream of 5 bits. Accordingly, the punctured binary convolutional encoders 320 and 322 encodes the 4 bits of the lower I and Q bit streams 216 and 218, respectively, to generate 5 coded bits of I₀′, I₁′, I₂′, I₃′, and I₄′ as the convolutionally encoded lower I stream 324 and 5 coded bits of Q₀′, Q₁′, Q₂′, Q₃′, and Q₄′ as the convolutionally encoded lower Q stream 326. Since the TCM encoder 300 encodes a trellis group of 38 input bits to generate 40 bits, the overall trellis coded modulation of the 256-QAM TCM encoder 300 yields a {fraction (38/40)} rate.

[0027] The 256 QAM mapper 318 receives three upper streams 308 and 310 and the lower streams 324 and 326 of the I and Q components for a total of six streams. Each of the streams includes 5 serial data bits. Since I and Q each includes 4 data streams, both I and Q streams can be used to define 4 bits of data at any one time. For example, the bits I₀′, I₁, I₂, and I₃define an I component while the bits Q₀′, Q₁, Q₂, and Q₃define a Q component.

[0028] The 4 bits of I and Q components can then used in a double mapping process to generate a QAM signal. Specifically, using the 4 bits of I and Q components as indices to a look-up table, the 256-QAM mapper 318 determines an 8-bit QAM symbol defined by “X” and “Y” components. Each of the “X” and “Y” components is 4 bits and represents 16-PAM signal constellation. Prior Art FIG. 3B illustrates a 256-QAM table that can be used to generate the X and Y values. The TCM encoder 300 may also include a QAM constellation mapper 328 to generate a QAM signal. That is, the QAM constellation mapper 328 can use the X and Y components as indices to a 256 QAM constellation mapping table to generate a corresponding QAM signal. Prior Art FIG. 3C depicts a 256-QAM constellation mapping table. Given the five consecutive bits in each of the streams 308, 310, 324, and 326 of the I and Q components, this double mapping process generates 5 consecutive QAM signals corresponding to the 5 consecutive 8-bit QAM symbols.

[0029] Conventional techniques and apparatus for decoding the 64/256-QAM TCM encoded data stream would typically require direct product of two 8-state trellis and two 16-state trellis for 64- and 256-QAM TCM encoded data, respectively. This is because both the quadrature and in-phase components of demodulated 64/256-QAM signals are needed to compute the squared Euclidian distance. Hence, the conventional technique and apparatus requires the use of a heavily connected 64 or 256-state trellis, resulting in complex trellis and branch metric processing.

[0030] Thus, what is needed is an apparatus and method for recovering information bits from the 64/256-QAM TCM encoded data stream using less trellis and branch metrics.

[0031] Broadly speaking, the present invention fills these needs by providing apparatus and method for recovering information bits from a 64/256-QAM TCM decoder. It should be appreciated that the present invention can be implemented in numerous ways, including as a process, an apparatus, a system, a device, or a method. Several inventive embodiments of the present invention are described below.

[0032] In one embodiment, the present invention provides an apparatus for recovering information bits from in-phase and quadrature components of a stream of quadrature amplitude modulation (QAM) trellis code modulation (TCM) signals. Each signal has an in-phase component and a quadrature component. The in-phase component includes a decoded bit and a plurality of uncoded in-phase bits and the quadrature component includes a decoded quadrature bit and a plurality of uncoded quadrature bits. The apparatus includes a reencode and puncturing circuitry, an inverse mapping circuitry, and a recovery circuitry. The reencode and puncture circuitry is adapted to receive the in-phase and quadrature components of a QAM TCM signal for encoding the decoded in-phase and quadrature bits. The reencode and puncture circuitry punctures the encoded in-phase bit with the uncoded in-phase bits to generate an in-phase component index. In addition, the reencode and puncture circuitry punctures the encoded quadrature bit with the remaining quadrature bits to generate a quadrature component index. The inverse mapping circuitry is coupled to the reencode and puncture circuitry to receive the in-phase component index and the quadrature component index for recovering a first set of in-phase bits and a second set of quadrature bits. The recovery circuitry is coupled to the inverse mapping circuitry to receive the first set of in-phase bits and the second set of quadrature bits. The recovery circuitry is also coupled to receive the decoded in-phase and quadrature bits. The recovery circuitry recovers a set of information bits by assembling the received bits.

[0033] In another embodiment, the present invention provides a method for recovering information bits from in-phase and quadrature components of a stream of QAM TCM signals. Each signal has an in-phase component and a quadrature component. The in-phase component includes a decoded bit and a plurality of uncoded in-phase bits and the quadrature component includes a decoded quadrature bit and a plurality of uncoded quadrature bits. The method includes: a) receiving the in-phase and quadrature components of a QAM TCM signal; b) encoding the decoded in-phase and quadrature bits of the in-phase and quadrature components, respectively; c) puncturing the encoded in-phase bit with the uncoded in-phase bits to generate an in-phase component index and puncturing the encoded quadrature bit with the remaining quadrature bits to generate a quadrature component index; d) recovering a first set of in-phase bits and a second set of quadrature bits using the in-phase component index and the quadrature component index; and e) recovering a set of information bits by assembling the first set of in-phase bits, the second set of quadrature bits, and the decoded in-phase and quadrature bits.

[0034] In yet another embodiment, the present invention provides an apparatus for recovering information bits from in-phase and quadrature components of a stream of QAM TCM signals. Each signal has an in-phase component and a quadrature component. The in-phase component includes a decoded bit and a plurality of uncoded in-phase bits and the quadrature component includes a decoded quadrature bit and a plurality of uncoded quadrature bits. The apparatus includes a re-encoding and puncturing means, a mapping means, and a recovering means. The re-encoding and puncturing means encodes the decoded in-phase and quadrature bits. Then, the reencode and puncture means punctures the encoded in-phase bit with the uncoded in-phase bits to generate an in-phase component index. In addition, the reencode and puncture means punctures the encoded least significant quadrature bit with the remaining quadrature bits to generate a quadrature component index. The mapping means recovers a first set of in-phase bits and a second set of quadrature bits from the in-phase component index and the quadrature component index, respectively. The recovering means recovers a set of information bits by assembling the first set of in-phase bits and the second set of quadrature bits and the decoded in-phase and quadrature bits.

[0035] Advantageously, the apparatus and method of the present invention provides the benefit of decoding in-phase and quadrature components independently and separately. Since in-phase and quadrature component of 64/256-QAM TCM code can be decoded independently, the present invention reduces branch metric calculation and trellis complexity. In addition, the apparatus and method of the present invention can decode 64- or 256-QAM TCM signals. Furthermore, by providing a synchronization circuitry, the present invention allows adjustment in synchronizing a depuncturing and puncturing scheme. Other aspects and advantages of the invention will become apparent from the following detailed description, taken in conjunction with the accompanying drawings, illustrating by way of example the principles of the invention.

[0036] The accompanying drawings, which are incorporated in and form a part of this specification, illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention.

[0037] Prior Art FIG. 1 illustrates a conventional cable modem transmission block diagram depicting a forward error correction scheme in accordance with standard of ITU-T Recommendation J-83 Annex B.

[0038] Prior Art FIG. 2A illustrates a block diagram of a conventional TCM encoder.

[0039] Prior Art FIG. 2B illustrates a 64-QAM table that can be used to generate the X and Y values.

[0040] Prior Art FIG. 2C depicts a 64-QAM constellation mapping table.

[0041] Prior Art FIG. 3A illustrates a block diagram of a conventional 256-QAM TCM encoder.

[0042] Prior Art FIG. 3B illustrates a 256-QAM table that can be used to generate the X and Y values.

[0043] Prior Art FIG. 3C depicts a 256-QAM constellation mapping table.

[0044] FIG. 4A illustrates a block diagram of a 64/256 QAM TCM decoder in accordance with one embodiment of the present invention.

[0045] FIG. 4B illustrates a block diagram of the 64/256 QAM TCM decoder including a serial-to-parallel circuitry.

[0046] FIG. 5 illustrates a block diagram of an apparatus 500 for recovering information bits from a stream of QAM TCM signals.

[0047] FIG. 6 illustrates an exemplary inverse mapping table for mapping (X′, Y′) values into (I′, Q′) values.

[0048] FIG. 7 illustrates a more detailed block diagram of the reencode and puncture circuitry in accordance with one embodiment of the present invention.

[0049] FIG. 8 illustrates a more detailed block diagram of the synchronization circuitry in accordance with one embodiment of the present invention.

[0050] FIG. 9 illustrates a more detailed diagram of the comparator in accordance with one embodiment of the present invention.

[0051] FIG. 10 illustrates a more detailed schematic diagram of the BCC encoder.

[0052] In the following detailed description of the present invention, apparatus and method for recovering information bits from 64/256-QAM TCM decoder, numerous specific details are set forth in order to provide a thorough understanding of the present invention. However, it will be obvious to one skilled in the art that the present invention may be practiced without these specific details. In other instances, well known methods, procedures, components, and circuits have not been described in detail so as not to unnecessarily obscure aspects of the present invention.

[0053] The present invention provides apparatus and method for recovering information bits using 64/256-Quadrature Amplitude Modulation (QAM) Trellis Coded Modulation (TCM) decoder, which may be used in the concatenated decoding scheme of North American cable modem. FIG. 4A illustrates a block diagram of a 64/256 QAM TCM decoder 400 in accordance with one embodiment of the present invention. The 64 QAM TCM decoder 400 includes a 64/256 QAM demodulator 402, a depuncture circuitry 404, and a rate-½ Viterbi decoder 406. In this configuration, the 64/256-QAM demodulator 402 receives an analog 64- or 256-QAM signal stream through a cable network and determines whether the received signal is a 64- or 256-QAM signal. In the preferred embodiment, the 64/256-QAM demodulator generates a 1-bit indicator signal for indicating whether the received signal is a 64- or 256-QAM signal and transmits the QAM indicator signal to other parts of the circuitry such as the depuncture circuitry 404 and the Viterbi decoder 406.

[0054] In this configuration, the QAM demodulator 402 receives a stream of QAM signals and demodulates each of the received QAM signals into an in-phase component X_Iand a quadrature component Y_Q. The in-phase component X_Iincludes five consecutive in-phase symbols (e.g., X₀, X₁, X₂, X₃, and X₄). The quadrature component Y_Qincludes five consecutive quadrature symbols (e.g., Y₀, Y₁, Y₂, Y₃, and Y₄).

[0055] The depuncture circuitry 404 receives the in-phase component X_Iand the quadrature component Y_Qand generates a depunctured in-phase component X_I′ and a depunctured quadrature component Y_Q′. Preferably, the depuncture circuitry 404 depunctures X_Iand Y_Qin accordance with a de-puncture matrix such as [P1,P2]=[0001:1111], where “0” indicates no transmission and “1” denotes transmission. Under the exemplary depuncturing scheme, the depuncture circuitry 407 generates the in-phase component X_I′ of [*, *, *, X₀: X₄, X₃, X₂, X₁] and the depuncture circuitry 408 produces the quadrature component Y_Q′ of [*, *, *, Y₀: Y₄, Y₃, Y₂, Y₁], wherein * denotes a dummy variable. The symbols in the in-phase component X_I′ and in the quadrature component Y_Q′ are transmitted pair wise in parallel. For example, the symbols X₀and X₁are transmitted to the Viterbi decoder 406 for simultaneous processing. Similarly, the symbols Y₀and Y₁are transmitted for processing by the Viterbi decoder 406.

[0056] In accordance with the de-puncture matrix, the depuncture circuitry 404 adds or inserts 3 dummy symbols (e.g., bits) to each of the received five bit X_Iand Y_Qcomponents and essentially converts the rate ⅘ soft output stream into rate ½ output stream. In this way, the in-phase and quadrature depuncture circuitry 407 and 408 generate a depunctured soft in-phase and quadrature outputs X_I′ and Y_Q′, respectively, for transmission to the Viterbi decoder 406.

[0057] The Viterbi decoder 406 includes an in-phase Viterbi decoder 412 and a quadrature Viterbi decoder 414. The in-phase Viterbi decoder receives the in-phase component X_I′ and generates a decoded in-phase (e.g., I_LSB) bit and uncoded bits or MSBs of the in-phase component (i.e., X_MSB). The quadrature Viterbi decoder receives the quadrature component Y_Q′ and generates a decoded quadrature (e.g., Q_LSB) bit and uncoded bits or MSBs of the quadrature component (i.e., Y_MSB) for each pair of symbols received. The Viterbi decoder 406 thus outputs in-phase component including I_LSBand X_MSBand quadrature component including Q_LSBand Y_MSB.

[0058] FIG. 4B illustrates a block diagram of the 64/256 QAM TCM decoder 400 including a serial-to-parallel circuitry 420. The serial-to parallel circuitry 420 includes an in-phase serial-to-parallel circuitry 422 and a quadrature serial-to-parallel circuitry 424. The in-phase serial-to-parallel circuitry 422 is coupled to the in-phase depuncture circuitry 407 to receive in-phase symbols X_I′ for arranging the in-phase symbols from a serial into a parallel sequence for input into the in-phase Viterbi decoder 412. The quadrature serial-to-parallel circuitry 424 is coupled to the quadrature depuncture circuitry 408 to receive quadrature symbols Y_Q′ for arranging the quadrature symbols from a serial into a parallel sequence for input into the quadrature Viterbi decoder 414. Preferably, the in-phase and quadrature serial-to-parallel circuitry 422 and 424 take two consecutive serial symbols and transmit the two symbols simultaneously in parallel into the in-phase and quadrature Viterbi decoders 412 and 414, respectively.

[0059] The Viterbi decoder 406 receives the depunctured in-phase and quadrature components from the depuncture circuitry 404 in parallel and decodes the soft in-phase and quadrature data streams from the 64/256-QAM demodulator 402 separately and independently. In the preferred embodiment, the Viterbi decoder 406 includes an in-phase Viterbi decoder 412 for decoding the in-phase component and a quadrature Viterbi decoder 414 for decoding the quadrature component. Each of the Viterbi decoders 412 and 414 generates one coded information bit for convolutional code and 4 uncoded bits for 64-QAM signals or 6 uncoded bits for 256-QAM signals for the respective component of the data stream.

[0060] The Viterbi decoder 406 receives the indicator signal from the QAM demodulator 402, which indicates whether the received signals are 64- or 256-QAM modulated signals. In response to the indicator signal, the Viterbi decoder 406 decodes the received signals as either 64- or 256-QAM TCM signals. In particular, the Viterbi decoders 412 and 414 decodes the in-phase and quadrature components, respectively, of the received signals in accordance with the indicator signal.

[0061] The 64/256 QAM TCM decoder 400 thus generates eight consecutive 3-bit pairs for parallel branches and 4 information bits from 8 consecutive in-phase component of 256-QAM signals. The 64/256 QAM TCM decoder 400 is discussed and illustrated in detail in a co-pending U.S. patent application filed on an even date herewith and entitled “A 64/256 QUADRATURE AMPLITUDE MODULATION TRELLIS CODED MODULATION DECODER,” by Dojun Rhee and Chanthachith Souvanthong, which is incorporated herein by reference in its entirety.

[0062] FIG. 5 illustrates a block diagram of an apparatus 500 for recovering information bits from a stream of QAM TCM signals. The apparatus includes a 64/256 QAM TCM decoder 400, a reencode and puncture circuitry 502, an inverse mapper 506, a synchronization circuitry 504, a recovery circuitry 508, and a delay unit 512. The 64/256 QAM TCM decoder 400 includes a QAM demodulator 402, a first-in-first-out (FIFO) buffer 510, a depuncture circuitry 404, and a Viterbi decoder 406. In the 64/256 QAM TCM decoder 400 configuration, the FIFO buffer 510 is adapted to provide an interface function between the demodulated in-phase and quadrature symbols and the depuncture circuitry 404.

[0063] In the 64/256 QAM TCM decoder 400 configuration, the QAM demodulator 402 receives a stream of QAM signals and demodulates each of the received QAM signals into an in-phase component X_Iand a quadrature component Y_Q. The in-phase component X_Iincludes five consecutive in-phase symbols (e.g., X₀, X₁, X₂, X₃, and X₄). The quadrature component Y_Qincludes five consecutive quadrature symbols (e.g., Y₀, Y₁, Y₂, Y₃, and Y₄). The FIFO buffer 510 receives the serial in-phase component X_Iand the quadrature component Y_Qand transmits X_Iand Y_Qto the depuncture circuitry 404. The depuncture circuitry 404 receives the in-phase component X_Iand the quadrature component Y_Qand generates a depunctured in-phase component X_I′ and a depunctured quadrature component Y_Q′.

[0064] The Viterbi decoder 406 generates a decoded in-phase (e.g., I_LSB) bit and a decoded quadrature (e.g., Q_LSB) bit for each pair of symbols fed into the Viterbi decoder 406. In addition, the Viterbi decoder 406 generates the uncoded bits or MSBs of the in-phase component (i.e., X_MSB) and the uncoded bits or MSBs of the quadrature component (i.e., Y_MSB). The Viterbi decoder 406 thus outputs in-phase component including I_LSBand X_MSBand quadrature component including Q_LSBand Y_MSB.

[0065] The reencode and puncture circuitry 502 receives four consecutive outputs of the Viterbi decoder 406 in sequence and performs binary convolutional encoding on the four consecutive decoded in-phase (I_LSB) bits and the four consecutive decoded quadrature (Q_LSB) bits independently. The binary convolutional encoding essentially reencodes the four Viterbi decoded in-phase I_LSBbits and four Viterbi quadrature Q_LSBbits using, for example, the convolutional encoder 206, 208, 320, or 322 described above. The reencode and puncture circuitry 502 then punctures the reencoded I_LSBand Q_LSBbits together with the uncoded in-phase component X_MSBand quadrature component Y_MSB. This puncturing is reverse of the depuncturing performed in the depuncture circuitry 404. In a preferred embodiment, the depuncture circuitry 404 transmits a puncturing synchronization signal to the reencode and puncture circuitry 502 through a delay buffer 512 for synchronizing the puncturing scheme with the depuncturing scheme of the depuncture circuitry 404.

[0066] For synchronization, the synchronization circuitry 504 is coupled to the reencode and puncture circuitry 502 to receive the X′ and Y′ components. In addition, the synchronization circuitry 504 is coupled to the FIFO 510 to receive soft X_Iand Y_Qsymbols for conversion into hard I′ and Q′ symbols. Then, the synchronization circuitry 504 compares the hard I′ and Q′ symbols with the X′ and Y′ symbols to determine equivalence. When the symbols are not same, an error signal is generated and the number of errors are accumulated. When the number of errors reaches a predetermined threshold value, the synchronization circuitry 504 transmits a synchronization signal to the depuncture circuitry 404 for resynchronizing the depuncturing scheme.

[0067] After reencoding and puncturing, the reencode and puncture circuitry 502 generates X′ and Y′ components of a signal. The inverse mapper 506 is coupled to the reencode and puncture circuitry 502 to receive the X′ and Y′ components. The inverse mapper 506 maps the received X′ and Y′ components onto an inverse mapping table using X′ and Y′ values as indices. The inverse mapper 506 then determines a digital signal bits described by I′ and Q′ components as (I′, Q′), which corresponds to the (X′, Y′) components. The I′ and Q′ components are then transmitted to the recovery circuitry 508.

[0068] In addition to the digital bits (I′, Q′), the recovery circuitry 508 receives the each of the four decoded in-phase (I_LSB) bits and the four decoded quadrature (Q_LSB) bits. The recovery circuitry 508 is configured to assemble or arrange the received input bits into original RS symbols. For 64-QAM signals, the recovery circuitry 508 generates 28 bits or 4 RS symbols. For 256-QAM signals, on the other hand, the recovery circuitry 508 generates 38 bits. In this manner, the recovery circuitry 508 essentially performs the reverse functions of the parser 202 and 302.

[0069] During the operation of the apparatus 500, it should be borne in mind that the QAM demodulator 402 generates a 64/256 QAM signal indicator for indicating whether the received signals are 64- or 256-QAM TCM signals. This signal indicator is transmitted to the FIFO buffer 510, the depuncture circuitry 404, the Viterbi decoder 406, the reencode and puncture circuitry 502, the inverse mapper 506, the recovery circuitry 508 and the synchronization circuitry 504. In addition, the depuncture circuitry 404 can generate a data valid bit, which may be transmitted to the Viterbi decoder 406, the reencode and puncture circuitry 502, the inverse mapper 506, the recovery circuitry 508, and the synchronization circuitry 504. The data valid bit is used to indicate whether the depunctured symbols generated by the depuncture circuitry 404 are valid or not.

[0070] As mentioned previously, the inverse mapper 506 maps the X′ and Y′ components as indices onto an inverse mapping table to determine corresponding (I′, Q′) symbol signals. The inverse mapper 506 is well known in the art and typically includes a memory unit that stores the values of the inverse mapping table. FIG. 6 illustrates an exemplary inverse mapping table 600 for mapping (X′, Y′) values into (I′, Q′) values.

[0071] Each of the elements in the apparatus 500 receives the indicator signal from the QAM demodulator 402, which indicates whether the received signals are 64- or 256-QAM modulated signals. In response to the indicator signal, the elements in the apparatus 500 the received signals as either 64- or 256-QAM TCM signals. For example, the Viterbi decoder 406, depuncture circuitry 404, reencode and puncture circuitry 502, inverse mapper 506, recovery circuitry 508, and the synchronization circuitry 504 process the in-phase and quadrature components of the received signals in accordance with the indicator signal from the QAM demodulator 402.

[0072] FIG. 7 illustrates a more detailed block diagram of the reencode and puncture circuitry 502 in accordance with one embodiment of the present invention. The reencode and puncture circuitry 502 includes a pair of binary convolutional code (BCC) encoders 702 and 704, a pair of delay buffers 706 and 708, a parallel-to-serial buffer 710, and a puncturing circuitry 712. The puncturing circuitry 712 includes an in-phase puncturing circuitry 714 and a quadrature puncturing circuitry 716.

[0073] With continuing reference to FIG. 7, the BCC encoders 702 and 704 receive, for encoding, a decoded in-phase (I_LSB) bit and a decoded quadrature (Q_LSB) bit, respectively, from the Viterbi decoder 406. The BCC encoders 702 and 704 reencodes the I_LSBand Q_LSBbits for subsequent puncturing. The ½ rate BCC encoders 702 and 704 generate 8 output bits each from the four consecutive input bits, I_LSBand Q_LSBbits, respectively. The BCC encoders 702 and 704 preferably implements the same convolutional encoding scheme of the conventional binary convolutional encoder of 206, 208, 320, and 322. The 2-bit outputs of the BCC encoders are transmitted in parallel to the parallel-to-serial buffer 710, which readies the data bits for puncturing.

[0074] The delay buffers 706 and 708 receive the uncoded in-phase and quadrature components X_MSBand Y_MSB, respectively. The number of X_MSBand Y_MSBbits differs depending on whether the received signals are 64- or 256-QAM TCM signals. For example, when the received signals are 64-QAM TCM signals, the number of X_MSBand Y_MSBbits are 4 bits each. On the other hand, when the received signals are 256-QAM TCM signals, the number of X_MSBand Y_MSBbits are 6 bits each. The delay buffers 706 and 708 provide a delay for synchronizing the subsequent puncturing with associated I_LSBand Q_LSBbits.

[0075] After an appropriate delay required for the synchronization, the uncoded in-phase and quadrature components X_MSBand Y_MSB, respectively, are transmitted to the parallel-to-serial buffer 710. In the preferred embodiment, the present invention utilizes 6 lines 720 and 724 for transmitting X_MSBand 6 lines 720 and 724 to transmit Y_MSB. Based on the signal selected by the signal indicator, the reencode and puncture circuitry 502 utilizes all 6 lines for 256-QAM signals or 4 lines for 256-QAM signals.

[0076] The parallel-to-serial buffer 710 is configured to serialize the incoming data for input to the puncturing circuitry 712. Specifically, the parallel-to-serial buffer 710 serializes each of the two parallel input bits of I_LSBand Q_LSBbits into two serial bits, which are then transmitted serially to the puncturing circuitry 712. On the other hand, the parallel-to-serial buffer 710 converts the uncoded in-phase X_MSBbits and the uncoded quadrature Y_MSBbits into one-half of the original width for input to the puncturing circuitry 712. Specifically, the parallel-to-serial buffer 710 employs a pair of three-lines 726 and 728 to transmit half of the uncoded in-phase X_MSBand the Y_MSB, respectively to the puncturing circuitry 712. Using these three-line pairs 726 and 728, the parallel-to-serial buffer 710 transmits 3 bits each over lines 726 and 728 for a 256-QAM TCM signal case and 2 bits each over lines 726 and 728 by disabling or ignoring one line for a 64-QAM TCM signal case.

[0077] The puncturing circuitry 712 includes the in-phase puncturing circuitry 714 for puncturing the in-phase component (I_LSBand X_MSBbits) and the quadrature puncturing circuitry 716 for puncturing the quadrature component (Q_LSBand Y_MSBbits). This puncturing scheme is a reverse process of the depuncturing performed in the depuncture circuitry 404 and is well known in the art. In a preferred embodiment, the puncturing circuitry 712 receives the puncturing synchronization signal from the depuncture circuitry 404 for synchronizing the puncturing scheme with the depuncturing scheme of the depuncture circuitry 404. The in-phase puncturing circuitry 714 thus generates punctured in-phase component X′ of 4 bits for 256-QAM TCM signals or 3 bits for 64-QAM TCM signals and the quadrature puncturing circuitry 716 produces punctured quadrature component Y′ of 4 bits for 256-QAM TCM signals or 3 bits for 64-QAM TCM signals. These components X′ and Y′ are then transmitted to the inverse mapper 506 and the synchronization circuitry 504 for further processing.

[0078] FIG. 8 illustrates a more detailed block diagram of the synchronization circuitry 504 in accordance with one embodiment of the present invention. The synchronization circuitry 504 includes a hard decision circuitry 802, a delay buffer 804, a comparator 806, and a decision logic circuitry 810. The synchronization circuitry 504 generates and transmits a synchronization signal to the depuncture circuitry 404 for resynchronizing its depuncturing sequence. In this configuration, the hard decision circuitry 802 receives an 8-bit soft in-phase symbol I_soft (e.g., X_I′) over eight lines 814 and an 8-bit soft quadrature symbol Q_soft (e.g., Y_Q′) over eight lines 812 from the FIFO 510. The hard decision circuitry 802 essentially converts the 8-bit soft symbols to 4-bit hard symbols. For 256-QAM symbols, the hard decision circuitry 802 converts from the 8-bits soft symbols ε[0 to 255] to 4-bit hard symbols ε{−15, −13, −11, −9, −7, −5, −3, −1, 1, 3, 5, 7, 9, 11, 13, 15}, which correspond to {1000, 1001, 1010, 1011, 1100, 1101, 1110, 1111, 0000, 0001, 0010, 0011, 0100, 0101, 0110, 0111}. On the other hand, for 64-QAM symbols, the hard decision circuitry 802 converts the 8-bit soft symbols ε[0 to 255] to 3-bit symbols ε{−7, −5, −3, −1, 1, 3, 5, 7}, which corresponds to {100, 101, 110, 111, 000, 001, 010, 011}. The hard decision circuitry 802 is well known in the art.

[0079] After the conversion, the hard decision circuitry 802 generates a 3-(for 64-QAM signals) or 4-bit (for 256-QAM signals) hard in-phase component I_hard over four lines 816. Simultaneously, the hard decision circuitry 802 produces a 3-(for 64-QAM signals) or 4-bit (for 256-QAM signals) hard quadrature component Q_hard over four lines 818. It should be borne in mind that when 3-bit signals are generated for 64-QAM signals, one of the four lines 816 and 818 are not used. The delay buffer 804 receives the I_hard and Q_hard signals and provides appropriate delay for input into the comparator 806 over lines 820 and 822, respectively.

[0080] The comparator 806 receives the hard in-phase component I_hard signals over lines 820 and the hard quadrature component Q_hard signals over lines 822. At about the same time, the comparator receives the in-phase component X′ and the quadrature component Y′ from the puncturing circuitry 712 over four lines 824 and 826, respectively. As mentioned previously, for 64-QAM signals, only three bit X′ and Y′ signals are generated and one of the four lines 824 and 826 are not utilized.

[0081] Upon receiving the input signals, the comparator 806 compares the signals from the puncturing circuitry 712 and the hard decision circuitry 802 to determine whether the signals are the same signals. If the signals are not the same signals, the comparator 806 generates an error signal, ERROR, and transmits it to the coupled decision logic circuitry 810 over line 828. If, on the other hand, the signals are the same, the error signal, ERROR, is not asserted.

[0082] The decision logic circuitry 810 is coupled to the comparator 806 to receive the error signal, ERROR, over line 828. Each time the comparator 806 generates or asserts the error signal, ERROR, over line 828, the decision logic circuitry 810 counts and accumulates the number of detected errors. When the number of errors exceeds a predetermined threshold number, the decision logic circuitry 810 generates a synchronization signal, SYNC, for transmission to the depuncture circuitry 404 over line 830. Thus transmitted synchronization signal, SYNC, synchronizes the depuncturing scheme of the depuncture circuitry 404 to another depuncturing sequence.

[0083] FIG. 9 illustrates a more detailed diagram of the comparator 806 in accordance with one embodiment of the present invention. The comparator 806 includes a pair of XOR gates 902 and 904, and an OR gate 906. The XOR gate 902 receives the hard in-phase signal I_hard over lines 820 and the in-phase component X′ over lines 824. On the other hand the XOR gate 904 receives the hard quadrature signal Q_hard over lines 822 and the quadrature component Y′ over lines 826. The XOR gates 902 and 904 then performs XOR operations on their respective inputs. The resulting output of the XOR gates 902 and 904 are then input into the OR gate 906. Based on the inputs from the XOR gates 902 and 904, the OR gate generates the error signal, ERROR, for transmission over line 828.

[0084] FIG. 10 illustrates a more detailed schematic diagram of the BCC encoder 702. It should be appreciated that the BCC encoder 704 can also be implemented using the BCC encoder 702. The BCC encoder 702 includes a pair of modulo-2 adders 1010 and 1012 and four shift registers 1002, 1004, 1006, and 1008 for storing input data bits. The BCC encoder 702 receives four consecutive decoded in-phase (I_LSB) bits in serial (e.g., I₀, I₃, I₆, and I₉) from the Viterbi decoder 406. The BCC encoder 702 reencodes the I_LSBbits for subsequent puncturing. The BCC encoder 702 is a 16-state non-systematic ½ rate encoder with the generator: G1=010 101 and G2=011 111 (25, 37) octal. This generator is equivalent to the generator matrix [1⊕D²⊕D⁴, 1⊕D⊕D²⊕D³⊕D⁴], where D represents a delay element “Z⁻¹.” The ½ rate BCC encoder 702 generates 8 output bits each from the four consecutive input bits, I_LSBand Q_LSBbits, respectively.

[0085] Advantageously, the apparatus and method of the present invention provides the benefit of decoding in-phase and quadrature components independently and separately. Since in-phase and quadrature component of 64/256-QAM TCM code can be decoded independently, the present invention reduces branch metric calculation and trellis complexity. In addition, the apparatus and method of the present invention can decode 64- or 256-QAM TCM signals. Furthermore, by providing a synchronization circuitry, the present invention allows adjustment in synchronizing a depuncturing and puncturing scheme.

[0086] While the present invention has been described in terms of several preferred embodiments, there are alterations, permutations, and equivalents which fall within the scope of this invention. It should also be noted that there are alternative ways of implementing both the method and apparatus of the present invention. It is therefore intended that the following appended claims be interpreted as including all such alterations, permutations, and equivalents as fall within the true spirit and scope of the present invention.