Diagnostic/control system using a multi-level I2C bus

[0002] This application makes reference to, incorporates the same herein, and claims all benefits accruing under 35 U.S.C. §119 from an application for A DIAGNOSTIC/CONTROL SYSTEM USING A MULTI-LEVEL I2C BUS earlier filed in the Korean Industrial Property Office on the 10^thof July 1997 and there duly assigned Ser. No. 32148/1997.

[0003] 1. Technical Field

[0004] The present invention relates to a diagnostic/control system using a multi-level I2C bus. More specifically, the invention relates to a diagnostic/control system using a multi-level I2C bus which embodies the I2C bus in a multi I2C bus structure using a multiplexer, and which makes system diagnosis/control possible by virtue of connecting the I2C devices needed in system diagnosis with a I2C bus, irrespective of the number of device, by adding a control circuit.

[0005] 2. Related Art

[0006] It is known in the art to connect a plurality of I2C bus master devices via a I2C bus to a plurality of other I2C bus master devices. It is also known in the art to connect a single bus master device via a I2C bus to a plurality of I2C bus slave devices. Finally, it is known in the art to connect a plurality of I2C bus master devices via a I2C bus to a plurality of I2C bus slave devices.

[0007] The latter arrangements enable the diagnosis/control of appropriate modules in each module of mini or large scale computers, and each bus master device is connected via bus cables. In this manner, an agent can manage an overall system.

[0008] However, a significant drawback of the prior arrangements resides in the fact that, in such arrangements, the number of bus devices which can be interconnected is limited. That is to say, there is a limitation as to the number of bus slave devices which can be connected in order to perform a system diagnosis/control function.

[0009] Therefore, there is a need for the development of a diagnostic/control system using a multi-level I2C bus in which the number of I2C bus devices which can be connected is not limited. There is also a need for the development of a diagnostic/control system using a multi-level I2C bus in which the diagnosis/control function of the system is not limited by any limitation on the number of I2C bus slave devices.

[0010] The following patents are considered to be representative of the prior art, and are burdened by the disadvantages set forth herein: U.S. Pat. No. 5,754,807 to Lambrecht et al., entitled Computer System Including A Multimedia Bus Which Utilizes A Separate Local Expansion Bus For Addressing And Control Cycles, U.S. Pat. No. 5,682,484 to Lambrecht, entitled System And Method For Transferring Data Streams Simultaneously On Multiple Buses In A Computer System, U.S. Pat. No. 5,627,965, entitled Method And Apparatus For Reducing The Effects Of Hardware Faults In A Computer System Employing Multiple Central Processing Modules, U.S. Pat. No. 5,604,918 to Hijsing et al., entitled Two-Line Mixed Analog/Digital Bus System And A Master Station And A Slave Station For Use In Such System, U.S. Pat. No. 5,598,538 to Cooper, entitled SCSI Multiplexer For Coupling A Computer Local Bus To A Shared Peripheral Global Bus, U.S. Pat. No. 5,555,372 to Tetreault et al, entitled Fault-Tolerant Computer System Employing AN Improved Error-Broadcast Mechanism, U.S. Pat. No. 5,522,050 to Amini et al, entitled Bus-To-Bus Bridge For A Multiple Bus Information Handling System That Optimizes Data Transfers Between A System Bus And A Peripheral Bus, U.S. Pat. No 5,448,703 to Amini et al., entitled Method And Apparatus For Providing Back-To-Back Data Transfers In AN Information Handling System Having A Multiplexed Bus, U.S. Pat. No. 5,376,928 to Testin, entitled Exchanging Data And Clock Lines On Multiple Format Data Buses, U.S. Pat. No. 4,825,438 to Bennett et al., entitled Bus Error Detection Employing Parity Verification, and U.S. Pat. No. 4,610,016 to Long et al., entitled Remote Multiplexer Terminal With Redundant Central Processor Units.

[0011] Therefore, in order to solve said problems, the object of the present invention is to provide a diagnostic/control system using a multi-level I2C bus comprising: multiple I2C bus master devices (MD0 to MDn) connected to a primary I2C bus; a I2C bus multiplexer module, which separates multiple secondary I2C buses from the primary I2C bus, and which can connect as many I2C bus slave devices (SD00 to SD0N, SD10 to SD1N, . . . , SDN1 to SDNN) as are necessary on the secondary I2C bus; I2C bus slave devices (SD00 to SD0N, SD10 to SD1N, SDN1 to SDNN) which, at any instant, can be accessed on a secondary bus by the I2C bus master devices (MD0 to MDn).

[0012] In one preferred mode, in accordance with the invention, it is preferable that a diagnostic/control system using a multi-level I2C bus includes multiple I2C bus master devices (MD0 to MDn) connected to a primary I2C bus; a I2C bus multiplexer module which separates multiple secondary I2C buses from the primary I2C bus, and which can connect with as many I2C bus slave devices (SD00 to SD0N, SD10 to SD1N, . . . , SDN1 to SDNN) as necessary on the secondary I2C bus; I2C bus slave devices (SD00 to SD0N, SD10 to SD1N, SDN1 to SDNN) which, at any instant, can be accessed on a secondary I2C bus by each of the I2C bus master devices (MD0 to MDn).

[0013] A more complete appreciation of the invention, and many of the attendant advantages thereof, will be readily apparent as the same becomes better understood by reference to the following detailed description when considered in conjunction with the accompanying drawings in which like reference symbols indicate the same or similar components, wherein:

[0014] FIG. 1 illustrates a block diagram of a I2C bus structure connected only with multiple I2C master devices.

[0015] FIG. 2 illustrates a block diagram of a I2C bus structure connecting a I2C master device and multiple I2C bus slave devices.

[0016] FIG. 3 illustrates a block diagram of a I2C bus structure connected to multiple I2C bus master devices and multiple I2C bus slave devices.

[0017] FIG. 4 illustrates a block diagram of a preferable I2C bus structure of the invention.

[0018] FIG. 5 illustrates a detailed circuit diagram of a I2C bus multiplexer of FIG. 4.

[0019] FIG. 6 illustrates a timing diagram showing basic protocol in a I2C bus write operation.

[0020] FIG. 7 illustrates a timing diagram of a primary I2C bus signal, a secondary I2C bus signal and other signals according to the secondary I2C bus change.

[0021] While the invention is susceptible to various modifications and alternative forms, specific embodiments thereof have been shown by way of example in the drawings and will herein be described in detail. It should be understood, however, that it is not intended to limit the invention to the particular forms disclosed, but on the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims.

[0022] FIG. 1 illustrates a block diagram of a I2C bus structure connected only with multiple I2C master devices. Referring to FIG. 1, the I2C bus structure is illustrated as being connected only with I2C bus master devices (MD0 to MDN) 10, . . . , 18.

[0023] The I2C bus structure contains I2C bus master devices, so as to diagnose/control the appropriate modules in each module of mini or large scaled computers, and each I2C bus master device is connected with I2C bus cables, this structure being a system by which an agent can manage an overall system.

[0024] FIG. 2 illustrates a block diagram of a I2C bus structure connected with a I2C master bus device (MD0) 20 and multiple I2C bus slave devices (SD0 to SDN) 22, 24, . . . , 26.

[0025] The I2C bus structure is a system wherein various diagnosis/control functions are offered by multiple I2C bus slave devices 22, 24, . . . , 26 in order to manage the system efficiently in the system under the server class, and the I2C bus slave device is controlled by a I2C bus master device 20. In the structure, the I2C bus master device 20 gives and takes needed information and commands by communication with a system host, as necessary, using its own program.

[0026] FIG. 3 illustrates a block diagram of a I2C bus structure wherein multiple I2C bus master devices (MD0 to MDN) 30, . . . , 32 are connected with multiple I2C bus slave devices (SD0 to SDn) 34, 36, . . . , 38. The I2C bus structure, which is a combination of the I2C bus structures of FIG. 1 and FIG. 2, is a management system to diagnose/control the system by constructing a main processor module part or a computer core part in the structure of FIG. 1 and in FIG. 2.

[0027] As noted above, it is possible for multiple I2C bus master devices 30, . . . , 32 and I2C bus slave devices 34, 36, . . . , 38 to be on the same I2C bus with the structure as shown in FIG. 3. In fact, it is possible that as many as 128 I2C bus master devices and as many as eight I2C bus slave devices can exist together on the same structure.

[0028] If the aforementioned I2C bus structure is used, however, the number of I2C bus devices which can be connected is limited. More specifically, limitation of the number of I2C bus slave devices causes limitation of the system diagnosis/control function, and makes various kinds of solutions impossible.

[0029] For example, in the case of the SDRAM DIMM module which is being produced at present, a method is provided to make it possible to manage information about the product through the I2C bus by using an EEPROM (Identification ROM) having a I2C interface, but it has problems managing only DMM. In addition, in the remote 8 bit I/O expander case, because the system structure is too complex, it is difficult to monitor the system status or to control the system. When more than eight devices are necessary, there is a restriction in such I2C bus structures. Moreover, because restriction of the number of I2C bus slave devices automatically restricts the management function, it is impossible to offer various solutions to a system user or a manager.

[0030] FIG. 4 illustrates a block diagram of a I2C bus structure of the present invention. As illustrated in FIG. 4, in order to overcome the limitation of the number of the I2C bus slave devices connected to the secondary I2C bus, the primary I2C bus is divided into multiple secondary I2C buses by using the I2C bus multiplexer 42, and multiple I2C bus slave devices (SD00, SD10, SD1N, . . . , SDN0 to SDNN) 43-48 are connected with multiple secondary I2C buses 0, 1, . . . , N.

[0031] A master device 40 (I2C bus master device 0) controlling the access of a I2C bus slave device among multiple I2C bus slave devices (SD00 to SD0N, SD10 to SD1N, . . . , SDN0 to SDNN) controls the I2C bus multiplexer 42, and the primary I2C bus connects to only one secondary I2C bus at any one moment.

[0032] Therefore, the master device 40 sets the I2C bus multiplexer 42 as a desirous secondary I2C bus before accessing the I2C bus slave device lying on one of said secondary I2C buses, and then accesses the corresponding I2C bus slave device.

[0033] FIG. 5 illustrates a detailed circuit diagram of the I2C bus multiplexer of FIG. 4. As illustrated, it is composed of a remote 8 bit I/O expander 50 connected to a primary I2C bus, converting the serial data of the I2C bus into parallel data; a register R1 determining a I2C bus slave device address of the remote 8 bit I/O expander 50; 8 bit multiplexer quick switches 51-54 multiplexing an SCL signal and an SDA signal of the primary I2C bus into 8 secondary I2C buses, respectively, by using 3 bits (P2, P1, P0) in the output of the remote 8 bit I/O expander 50 as a select input signal and by using a bit (P3) among the output of registers R2, R3 sourcing current via the primary I2C bus and the remote 8 bit I/O expander 50 as an output enable signal; an inverter 55 driving the output enable signal of the 8 bit multiplexer quick switches 51, 52 by virtue of inverting a bit of outputs of the remote 8 bit I/O expander 50, in order to distinguish an upper block (I2C15_xxx to I2C8_xxx) from a lower block (I2C7-xxx to I2C0_xxx) of the secondary I2C bus; and a pull-up resistive network RN1 to RN4 which transmits high current toward each 16 secondary I2C bus.

[0034] In the present invention, it is preferable that the I2C bus multiplexer module comprises: a remote 8 bit I/O expander 50 for the I2C bus, changing serial data of the primary I2C bus into parallel data by connecting with the primary I2C bus; a register R1 determining a I2C bus slave device address of the remote 8 bit I/O expander 50 for said I2C bus; registers R2, R3 transmitting high current to said primary I2C bus; 8 bit multiplexer quick switches 51-54 multiplexing an SCL signal and an SDA signal of said primary I2C bus into each 8 secondary I2C bus by using three bits (P2, P1, P0) of the outputs of said remote 8 bit I/O expander 50 for said I2C bus as select input signals, and by using a bit of the outputs of said remote 8 bit I/O expander 50 for said I2C bus as an output enable signal; an inverter 55 driving the output enable signal of the 8 bit multiplexer quick switches 51-54 in order to distinguish an upper block (I2C15_xxx to I2C8_xxx) from a lower block (I2C7_xxx to I2C0_xxx) of said secondary I2C bus by virtue of inverting a bit of the outputs of the remote 8 bit I/O expander 50 for the I2C bus; and a pull-up resistive network RN1 or RN4 transmitting high current toward each 16 secondary I2C bus.

[0035] It is preferable that each I2C bus master device taking charge of a I2C bus slave devices access on said secondary I2C bus, among said multiple I2C bus master devices 40, . . . , 41, communicates with the remote 8 bit I/O expander 50, sets the output ports P3 to P0 of the remote 8 bit I/O expander 50, controls the select input ports S2, S1, S0 of said 8 bit multiplexer quick switches 51-54, connects each output port of said 8 bit multiplexer quick switches 51-54 with its own input port, and communicates with the arbitrary I2C bus by enabling or disabling the output of said 8 bit multiplexer quick switches 51-54 with an OE input port value through said inverter 55 according to the output of the remote 8 bit I/O expander 50.

[0036] It is preferable that each I2C bus master device taking charge of a I2C bus slave device access on the secondary I2C bus, among said multiple I2C bus master devices 40, . . . , 41, communicates with any I2C bus slave device 43-48 on said secondary I2C bus by setting a value corresponding to the secondary I2C bus number on the output ports P3 to P0 of the remote 8 bit I/O expander 50 whenever change of any secondary I2C bus is needed.

[0037] It is preferable that said multiple secondary I2C buses generate the 32 output enable signals of said 8 bit multiplexer quick switches 51-54 using the 5 bits P7 to P3 of the output port of said remote 8 bit I/O expander 50, and that said secondary I2C bus is expanded into 256 buses at a maximum by controlling each 8 bit multiplexer quick switch 51-54, consisting of two parts multiplexing said SCL signal and SDA signal with an output enable signal.

[0038] It is preferable that the 32 output enable signals of the generated 8 bit multiplexer quick switches 51-54, are generated by the inverter 55 and expressed as Boolean expression as follows, or by a generation circuit having an equivalent function with said inverter:

[0039] !0E0=!P7 & !P6 & !P5 & !P4 & !P3;

[0040] !0E1=!P7 & !P6 &!P5 &!P4 & P3;

[0041] !0E2=!P7 &!P6 &!P5 & P4 &!P3;

[0042] !0E3=!P7 &!P6 &!P5 & P4 & P3;

[0043] !0E4=!P7 &!P6 & P5 &!P4 &!P3;

[0044] !0E5=!P7 &!P6 & P5 &!P4 & P3;

[0045] !0E6=!P7 &!P6 & P5 & P4 &!P3;

[0046] !0E7=!P7 &!P6 & P5 & P4 & P3;

[0047] !0E8=!P7 & P6 & !P5 & !P4 & !P3;

[0048] !0E9=!P7 & P6 &!P5 &!P4 & P3;

[0049] !0E10=!P7 & P6 & !P5 & P4 & !P3;

[0050] !0E11=!P7 & P6 &!P5 & P4 & P3;

[0051] !0E12=!P7 & P6 & P5 & !P4 & !P3;

[0052] !0E13=!P7 & P6 & P5 &!P4 & P3;

[0053] !0E14=!P7 & P6 & P5 & P4 &!P3;

[0054] !0E15=!P7 & P6 & P5 & P4 & P3;

[0055] !0E16=P7 & !P6 & !P5 & !P4 & !P3;

[0056] !0E17=P7 & !P6 & !P5 & !P4 & P3;

[0057] !0E18=P7 &!P6 &!P5 & P4 &!P3;

[0058] !0E19=P7 &!P6 &!P5 & P4 & P3;

[0059] !0E20=P7 &!P6 & P5 & !P4 & !P3;

[0060] !0E21=P7 &!P6 & P5 &!P4 & P3;

[0061] !0E22=P7 &!P6 & P5 & P4 &!P3;

[0062] !0E23=P7 &!P6 & P5 & P4 & P3;

[0063] !0E24=P7 & P6 &!P5 &!P4 &!P3;

[0064] !0E25=P7 & P6 &!P5 &!P4 & P3;

[0065] !0E26=P7 & P6 &!P5 & P4 &!P3;

[0066] !0E27=P7 & P6 &!P5 & P4 & P3;

[0067] !0E28=P7 & P6 & P5 &!P4 &!P3;

[0068] !0E29=P7 & P6 & P5 &!P4 & P3;

[0069] !0E30=P7 & P6 & P5 & P4 &!P3;

[0070] !0E31=P7 & P6 & P5 & P4 & P3;

[0071] In the latter regard, P is the output port of said 8 bit remote I/O expander 50 and !0E0 to !0E31 are the generated output enable signals.

[0072] The invention will now be further explained in detail, the important terms of the present invention being explained as follows:

[0073] I2C bus master devices 40-41: These devices can use a I2C bus and access other master or slave devices; they also sometimes operate as slave devices when accessed by other master devices.

[0074] I2C bus slave devices 43-48: These devices cannot use the I2C bus and are passive devices operating always according to access by a master device.

[0075] I2C bus address: This address has to communicate with a needful device by using the I2C bus address on protocol because each device connected with the I2C bus has its own address; it is possible to connect to 128 devices at a maximum on a I2C bus because the I2C address is composed of 7 bits.

[0076] I2C bus master device address: This address is distinguished using 7 bits of 8 bit registers within the device; the registers can be set up by a program.

[0077] I2C bus slave device address: 4 bits of the 7 bit address are used to distinguish device type, and the other 3 bits are used to divide devices of the same kind (i.e., on a bus, at best, 8 devices of the same kind can be connected).

[0078] I2C bus slave device type: This is denoted by 4 bits of the address; the devices are denoted as follows:

[0079] 00100: Remote 8 bit I/O Expander

[0080] 1001: Temperature Detector

[0081] 1010: EEPROM (ID ROM or for memory)

[0082] 0101: H/NV Monitor

[0083] The remote 8 bit I/O expander 50 illustrated in FIG. 5 is a I2C bus slave device connected to the primary I2C bus, and is controlled by the master device 40.

[0084] The secondary I2C bus (I2C15_XXX to I2C0_XXX) operates as an independent I2C bus.

[0085] In order to communicate with the arbitrary I2C bus slave device on the arbitrary secondary I2C bus, the master device 40 communicates with said remote 8 bit I/O expander 50 of multiplexer 40, and sets the output ports P3 to P0 of expander 50 at a value suitable for a desired secondary I2C bus number.

[0086] For example, to communicate with the secondary I2C bus number 12, if remote 8 bit I/O expander output ports P3, P2, P1, P0 are set to P3, P2, P1, P0=1, 1, 0, 0, the select input ports S2, S1, S0 of said 8 bit multiplexer quick switches 51-54 become S2, S1, S0=1, 0, 0, and output port B4 of each device 51-54 is connected with each input port A.

[0087] Because the 8 bit multiplexer quick switches 51-54 have a low active output enable port, the output P3 of the remote 8 bit I/O expander 50 having a value ‘1’ goes into the OE input port as a value ‘0’ the inverter 55, and then enables the outputs of 8 bit multiplexer quick switches 51, 52. Moreover, the 8 bit multiplexer quick switches 53, 54 become disabled because the OE input port has a value ‘1’.

[0088] The SCL of the primary I2C bus is connected with I2C12_SCL, and the SDA is connected with I2C12_SDA, so that the primary I2C bus and the secondary I2C bus are connected to each other.

[0089] Finally, the master device 40 communicates with the I2C bus slave device on secondary I2C bus number 12 after setting of the secondary I2C bus connection.

[0090] The master device 40 has to set the remote 8 bit I/O expander 50 to a suitable number whenever change of the secondary I2C bus is needed.

[0091] The secondary I2C buses can be expanded to a maximum of 256 if necessary, and that makes it possible to control the I2C multiplexers. To that purpose, it generates 32 output enable signals of the I2C multiplexer switch 42 using 5 bits P7 to P3 of the output port of the remote 8 bit I/O expander 50 for the I2C bus illustrated in FIG. 5, and controls the I2C multiplexers, respectively, consisting of two pairs mixing the SCL signal and the SDA signal with an output enable signal.

[0092] Then, the inverter 55 illustrated in FIG. 5 substitutes as an output enable generation circuit in accordance with the following Boolean expression:

[0093] !0E0=!P7 &!P6 &!P5 &!P4 &!P3;

[0094] !0E1=!P7 &!P6 &!P5 &!P4 & P3;

[0095] !0E2=!P7 &!P6 &!P5 & P4 &!P3;

[0096] !0E3=!P7 &!P6 &!P5 & P4 & P3;

[0097] !0E4=!P7 &!P6 & P5 &!P4 &!P3;

[0098] !0E5=!P7 &!P6 & P5 &!P4 & P3;

[0099] !0E6=!P7 &!P6 & P5 & P4 &!P3;

[0100] !0E7=!P7 &!P6 & P5 & P4 & P3;

[0101] !0E8=!P7 & P6 & !P5 & !P4 & !P3;

[0102] !0E9=!P7 & P6 &!P5 &!P4 & P3;

[0103] !0E10=!P7 & P6 & !P5 & P4 & !P3;

[0104] !0E11=!P7 & P6 &!P5 & P4 & P3;

[0105] !0E12=!P7 & P6 & P5 & !P4 & !P3;

[0106] !0E13=!P7 & P6 & P5 &!P4 & P3;

[0107] !0E14=!P7 & P6 & P5 & P4 &!P3;

[0108] !0E15=!P7 & P6 & P5 & P4 & P3;

[0109] !0E16=P7 & !P6 & !P5 & !P4 & !P3;

[0110] !0E17=P7 &!P6 &!P5 &!P4 & P3;

[0111] !0E18=P7 &!P6 &!P5 & P4 &!P3;

[0112] !0E19=P7 &!P6 &!P5 & P4 & P3;

[0113] !0E20=P7 &!P6 & P5 &!P4 &!P3;

[0114] !0E21 P7 &!P6 & P5 &!P4 & P3;

[0115] !0E22=P7 &!P6 & P5 & P4 &!P3;

[0116] !0E23=P7 &!P6 & P5 & P4 & P3;

[0117] !0E24=P7 & P6 &!P5 & !P4 & !P3;

[0118] !0E25 P7 & P6 &!P5 &!P4 & P3;

[0119] !0E26=P7 & P6 &!P5 & P4 &!P3;

[0120] !0E27=P7 & P6 &!P5 & P4 & P3;

[0121] !0E28=P7 & P6 & P5 &!P4 &!P3;

[0122] !0E29=P7 & P6 & P5 &!P4 & P3;

[0123] !0E30=P7 & P6 & P5 & P4 &!P3;

[0124] !0E31=P7 & P6 & P5 & P4 & P3;

[0125] In the latter regard, by way of example, !0E0 controls the output of 8 bit multiplexer quick switches 53-54 illustrated in FIG. 5 because !0E0 becomes ‘0’ when output ports P7 to P3 of said remote 8 bit I/O expander 50 are all ‘0’.

[0126] FIG. 6 illustrates a timing diagram showing the basic protocol for a I2C bus write operation.

[0127] In FIG. 6, if the I2C bus master device changes the SDA signal from high to low with a high SCL signal in order to write to an I2C bus slave device through the I2C bus, the start condition of the I2C bus occurs, and it drives 8 bits of the address of the I2C bus slave device in service wherein it communicates.

[0128] The I2C bus slave device appointed by the address informs the I2C bus master device of no problem by setting the SDA signal to low at the next clock of the last address bit (ACK operation). The I2C bus master device receives the ACK signal and operates on the 8 bits of data to write them in serial fashion onto the I2C bus according to the SCL signal, and the I2C bus slave device receives and saves the data.

[0129] The I2C bus slave device sends an ACK signal by setting the SDA signal to low when the data are received safely.

[0130] The I2C bus master device, having received the ACK signal, finishes the bus operation by changing the SDA signal from low to high, while the SCL signal is high.

[0131] FIG. 7 illustrates a timing diagram of a primary I2C bus signal, a secondary I2C bus signal, and other signals, while said master device 40 illustrated in FIG. 5 changes from the secondary I2C bus number 5 to secondary I2C bus number 12. In FIG. 7, output ports P3 to P0 of remote 8 bit I/O expander 50 change at time T with the rising edge of the SCL signal at the time of an ACK operation, and the secondary I2C bus connected to the primary I2C bus at the time T1 changes from number 5 to number 12.

[0132] In the timing diagram for number 12 of the secondary I2C bus, at time T, a start condition occurs and, at time T2, an end condition occurs. A dummy operation of a perfect cycle is made, but it does not affect the operation of I2C bus slave device because the cycle terminates normally.

[0133] The I2C bus slave device having address ‘0100010X’ on secondary bus number 12 responds to a start condition at T3.

[0134] In accordance with the present invention as described above, it is possible to embody a diagnostic/control system with various perfect functions by dividing the primary I2C bus into a maximum of 256

[0135] secondary I2C buses, and by making it possible to connect to as many I2C bus slave devices as can be connected to a I2C bus master device.

[0136] It should be understood that the present invention is not limited to the particular embodiment disclosed herein as the best mode contemplated for carrying out the present invention, but rather that the present invention is not limited to the specific embodiments described in this specification except as defined in the appended claims.