Method of reconstructing alignment mark during STI process

[0002] This application claims priority benefit of Taiwan application Serial no. 87117480, filed Oct. 22, 1998.

[0003] 1. Field of the Invention

[0004] The invention relates to a method of fabricating an integrated circuit, and more particularly to a method of reconstructing an alignment mark during shallow trench isolation (STI) process.

[0005] 2. Description of the Related Art

[0006] Photolithography is a key process in manufacturing semiconductor devices, so it plays an important role on the fabrication of the semiconductor. In the general process of fabricating a device, completion of the device requires approximately 10-28 patterning and exposure steps. In order to transfer the pattern of the mask accurately onto the wafer, masks between different levels should be aligned prior to the exposure of the photoresist to avoid wafer failure, which is due to transfer error of the pattern.

[0007] In a conventional exposure process, an alignment mark corresponding to a mask is formed on the wafer, which alignment mark is provided to form the semiconductor devices. A step height produced by the alignment mark may provide a scattering site or diffraction edge during alignment. When the light source, such as a He—Ne laser of a wavelength of about 635 nm, is provided to irradiate the whole wafer, a diffraction pattern produced by the light projected on the alignment mark is reflected to a alignment sensor and a first order diffraction interferometer alignment system to achieve alignment. However, the step height of the alignment mark, less than 200 Å, for example, is not high enough to obtain an obvious diffraction. As a result, the alignment signal is too weak or the noise ratio is too strong, which makes the alignment signal indiscernible by the alignment sensor and misalignment thus occurs.

[0008] FIGS. 1A-1E are schematic, cross-sectional views illustrating fabrication of a semiconductor device according to prior process. Referring to FIG. 1A, a substrate 100 having an alignment mark 101 is provided and a pad oxide layer 102 is formed thereon. A silicon nitride layer 104 serving as a mask layer is formed on the pad oxide layer 102. Since the alignment mark 101 formed within the substrate 100 has at least a depression 150 and there is a step height 170 between the surface 103 of the substrate 100 and the alignment mark 150, a recess 105 is therefore formed within the silicon nitride layer 104 above the alignment mark 101.

[0009] Referring to FIG. 1B, the silicon nitride layer 104 is patterned by photolithographic technique to form a patterned silicon nitride layer 104a, and the pad oxide layer 102 and the substrate 100 are successively etched using the silicon nitride layer 104aas a hard mask. A trench 108 is formed within the substrate 100.

[0010] Referring to FIG. 1C, a liner oxide layer 110 is formed on the exposed substrate 100 within the trench 108. A silicon oxide layer 112 is then formed to fill the trench 108. Since the step height 170 between the alignment mark 101 and the surface 103 of the substrate 100 is smaller than the depth 180 of the trench, the recess 105 within the silicon nitride layer 104aabove the alignment mark 101 can be filled with the silicon oxide layer 112 when the trench 108 is filled with the silicon oxide layer 112.

[0011] Referring to FIG. 1D, the silicon nitride layer 104ais used as a stop layer, the silicon oxide layer 112 on the silicon nitride layer 104ais removed by chemical-mechanical polishing (CMP) and a portion of the silicon oxide layer 112ais left in the trench 108. During CMP process, the silicon oxide layer 126 in the recess 105 also remains.

[0012] Referring to FIG. 1E, the silicon nitride layer 104ais removed to expose the pad oxide layer 102a, and the pad oxide layer 102ais then removed in a HF solution. The remaining silicon oxide layer 112aand the liner oxide layer 110 in the trench 108 serve as an isolation region 114.

[0013] The etching rate of the silicon oxide layer 112bis different from the etching rate of the silicon nitride layer 104a. During the process for etching the silicon nitride layer 104a, the silicon oxide layer 112bserves as a hard mask, which makes the silicon nitride layer 104aunder the silicon oxide layer 112bdifficult to remove. The silicon oxide layer 112bcan be removed by the HF solution for etching the pad oxide layer 102a, but the etching time in the HF solution is too short to completely remove the desired thickness of the silicon oxide layer 112b. Therefore, the step height 170 in the depression 150 is not high enough due to the residual silicon oxide layer 112band the silicon nitride layer 104ain the recess 105, and this causes misalignment.

[0014] In addition, the silicon oxide layer 112bcan be removed by prolonging the etching time when the pad oxide layer 102ais removed by the HF solution. However, because the etching time for etching the silicon oxide layer 112bis hard to control, the silicon oxide layer 112awithin the trench 108 is hence easily over-etched to cause damage to the isolation region 114.

[0015] Referring to FIG. 1F and FIG. 1G, in order to avoid the planarized silicon oxide layer 112bcovering the alignment mark 101 during STI process, a photoresist layer 116 is further formed over the substrate 100. The silicon oxide layer 112bin the recess 105 is removed in a HF solution. The photoresist layer 116 is then stripped, and the silicon nitride layer 104aand the silicon oxide layer 102aare removed successively. The alignment mark 101 is reconstructed. However, it is necessary to provide an additional mask to reconstruct the alignment mark and as a result, the fabricating time for etching is increased and the cost is also raised.

[0016] It is therefore an object of the invention to provide a method in which the residual material above the alignment mark can be removed after global planarization during STI process, and the alignment mark can be reconstructed without an additional mask.

[0017] To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method of reconstructing an alignment mark during a shallow trench isolation process. A mask layer is formed on the substrate and a cap layer is further formed to fill a recess within the mask layer above the alignment mark. A trench is then formed within the substrate. An insulating layer is formed to fill the trench and a CMP process is carried out to globally planarize the wafer until exposing the mask layer. The cap layer, the mask layer and the pad oxide layer are then successively removed. An isolation region is therefore formed in the trench and the alignment mark can be reconstructed.

[0018] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.

[0019] The accompanying drawings are included to provide a further understanding of the invention, and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings,

[0020] FIGS. 1A-1G are schematic, cross-sectional views illustrating fabrication of a semiconductor device of prior process known in prior art;

[0021] FIGS. 2A-2F are schematic, cross-sectional views illustrating reconstruction of an alignment mark during the formation of the STI in a preferred embodiment according to the invention; and

[0022] FIGS. 3A-3B are schematic, cross-sectional views illustrating reconstruction of an alignment mark during the formation of the STI after FIG. 2A in a preferred embodiment according to the invention and its result is shown in FIG. 2D.

[0023] Referring to FIG. 2A, a substrate 200 having an alignment mark 201 is provided and a pad oxide layer 202 is thermally formed on the substrate 200 to protect the substrate 200 from being damaged during the subsequent fabrication. A mask layer 204 is then formed on the pad oxide layer 202 and subsequently serves as an etching mask in the formation of the trench within the substrate 200. The alignment mark 201 has at least a depression 205 formed within the substrate 200 and the depression 250 has a step height 270 with the surface 203 of the substrate 200. The mask layer 204 above the alignment mark 201 has at least a recess 205 formed thereon due to the depression 250. The recess 205 is filled with a cap layer 206 formed over the substrate 200. The pad oxide layer 202 can be formed by thermal oxidation. The material of the mask layer 204 includes a silicon nitride layer formed by low-pressure chemical vapor deposition (LPCVD). The cap layer 206 has a different etching rate from that of the mask layer 204 and the isolation region subsequently formed, such that the cap layer 206 includes silicon-oxy-nitride, polysilicon or amorphous silicon and is formed by a process such as CVD.

[0024] Referring to FIG. 2B, the cap layer 206, the mask layer 204 and the pad oxide layer 202 are patterned by conventional photolithographic technique, and a trench 208 is formed within the substrate 200. A photoresist layer (not shown) is formed over the substrate 200, and the cap layer 206 and the mask layer 204 are etched by dry etching to form the patterned cap layer 206aand mask layer 204a. The pad oxide layer 202 and the substrate 200 are successively etched to form the trench 208 within the substrate 200. The photoresist layer is then stripped.

[0025] Referring to FIG. 2C, a liner oxide layer 210 is formed on the exposed substrate 200 within the trench 208 by a process such as thermal oxidation. An insulating layer 212 including silicon oxide is formed to fill the trench 208. The silicon oxide is formed by atmospheric pressure chemical vapor deposition (APCVD) and then densified at a high temperature to form a dense silicon oxide layer 212. Since the recess 205 above the mask layer 204ais filled with the cap layer 206a, the insulating layer 212 formed on the substrate 200 cannot fill the recess 205.

[0026] Referring to FIG. 2D, the cap layer 206aand the insulating layer 212 are removed from the mask layer 204ato globally planarize the wafer. A portion of the cap layer 206band the insulating layer 212arespectively remain in the recess 205 and the trench 208. Using the cap layer 206bas a stop layer, the insulating layer 212 on the cap layer 206ais removed by CMP. CMP is carried out to remove the cap layer 206aon the mask layer 204awhile using the mask layer 204aas a stop layer, and thus the insulating layer 212aand the cap layer 206bare left inside the trench 208 and the recess 205, respectively. Since the recess 205 is completely covered by the cap layer 206b, the insulating layer 212 does not remain in the recess 205 after planarization. Therefore, the problem as seen in prior art where the insulating layer is left in the recess 205 can be avoided.

[0027] Referring to FIG. 2E, the cap layer 206bis removed to expose the recess 205. The method to remove the cap layer 206bincludes anisotropic etching such as reactive ion etching (RIE) and isotropic etching such as wet etching. The etching rate of the cap layer 206bis different from that of the insulating layer 212aand the mask layer 204a, so that the cap layer 206bcan be selectively removed. Because the etching conditions to remove the cap layer 206bin the foregoing step are used, the insulating layer 212ain the trench 208 is not damaged by etching.

[0028] Referring to FIG. 2F, the mask layer 204aand the pad oxide layer 202aare removed successively to expose the depression 250 and the alignment mark 201 thus reappears. The remaining insulating layer 212aand the liner oxide layer 210 within the substrate 200 serve as an isolation region 214. The mask layer 204acan be removed isotropically by wet etching in a hot phosphoric acid, and the pad oxide layer 202ais then exposed. The pad oxide layer 202ais removed in HF solution and the alignment mark 201 is reconstructed.

[0029] The result as shown in FIG. 2D can be achieved by the fabricating method as shown in FIGS. 3A-3B when the pad oxide layer 202, the mask layer 204 and the cap layer 206 are formed on the substrate 200, as shown in FIG. 2A.

[0030] Referring to FIG. 3A, a portion of the cap layer 206 is removed to planarize the wafer and the remaining cap layer 206bcovers the recess 205. The mask layer 204 and the pad oxide layer 202 are patterned to form a trench 208 within the substrate 200. Using the mask layer 204 as a stop layer, a CMP process is performed to remove a portion of the cap layer 206, and the cap layer 206bis only left in the recess 205. A photoresist layer (not shown) is formed on the mask layer 204 and the mask layer 204 is patterned by dry etching. The pad oxide layer 202 and the substrate 200 are successively etched to form pad oxide layer 202awhen the mask layer 204aserves as a hard mask. A trench 208 is therefore formed with the substrate 200.

[0031] Referring to FIG. 3B, a liner oxide layer 210 is formed on the exposed substrate 200 within the trench 208 by a process such as thermal oxidation. An insulating layer 212 including silicon oxide is formed to fill the trench 208. The silicon oxide is formed by atmospheric pressure chemical vapor deposition (APCVD) and then densified at a high temperature to form a dense silicon oxide layer 212. Since the recess 205 above the mask layer 204ais filled with the cap layer 206b, the insulating layer 212 formed on the substrate 200 cannot fill the recess 205.

[0032] Referring back to FIG. 2D, the cap layer 206aand the insulating layer 212 are removed from the mask layer 204ato globally planarize the wafer in FIG. 3B. A portion of the cap layer 206band the insulating layer 212arespectively remain in the recess 205 and the trench 208. Using the cap layer 206bas a stop layer, the insulating layer 212 on the cap layer 206ais removed by CMP. CMP is carried out to remove the cap layer 206aon the mask layer 204awhile using the mask layer 204aas a stop layer, and thus the trench 208 and the recess 205 have insulating layer 212aand cap layer 206bleft inside, respectively. Since the recess 205 is completely covered by the cap layer 206a, the insulating layer 212 does not remain in the recess 205 after planarization. Therefore, the problem as seen in prior art where the insulating layer is left in the recess 205 can be avoided.

[0033] As described above, this invention includes some features:

[0034] 1. The alignment mark within the substrate can be reconstructed without additional photolithographic technique and exposure. Therefore, both the fabricating time and the cost can be reduced to enhance the throughput of the products.

[0035] 2. The insulating layer in the STI is not over-etched and damaged when the pad oxide layer is over etched to remove the remaining insulating layer above the alignment mark.

[0036] Other embodiments of the invention will appear to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.